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Messages from 650

Article: 650
Subject: Re: NeoCAD Experience
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 27 Jan 1995 14:37:53 GMT
Links: << >>  << T >>  << A >>
In article h0h@news.tv.tek.com, bobe@prebman.tv.tek.com (Bob Elkind) writes:
> davelec@extro.ucc.su.OZ.AU (David le Comte) writes:
> >kenn@neocad.com (Kenn Perry) writes:
> >
> >>   ...   PC prices begin
> >>at $995 U.S. list.  NeoCAD's new, low-cost Access system
> >>provides support for all vendor's devices under 3K gates
                                              **************

> >>(approximate), timing-driven place and route, an EDA vendor
> >>integration kit for $2,995.  This configuration has been very
>                       | 
>                       I *think* you mean $12,995. -- be
> 
> >>attractive to new users of FPGAs.

I think the $2,995 is a *new* deal from NeoCAD.  Notice the *under 3K gates*.
Sounds smart to me.  This is a cheap way to get vendor independence and 
try out NeoCAD.  The other $4,995 single vendor deals claim to give you a 
"better" router with a *path* to vendor independence.  You might try getting 
a new quote if less than 3K gates does anything for you.


---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 651
Subject: Question on 22v10 fitting in Warp2
From: sugiura@tcp-ip.or.jp (Akinori Sugiura)
Date: Sat, 28 Jan 1995 15:43:42 +0900
Links: << >>  << T >>  << A >>
The Cypress Warp2 VHDL compiler supports 22v10 devices. The entity code for 
24-pin devices exist, however there is no entity code for 28-pin devices. 

   - Does anybody know if it is possible to use 28-pin 22v10 in Warp2?
   - Does anybody have any idea for fitting designs into 28-pin 22v10 in Warp2?

I would appreciate any help.
-- 
Akinori Sugiura 
Email: sugiura@tcp-ip.or.jp
Tel & Fax: +81 532 25 8374


Article: 652
Subject: Re: Problems programming Intel FX780
From: devb@jazzmin.vnet.net (David Van den Bout)
Date: 28 Jan 1995 20:21:26 -0500
Links: << >>  << T >>  << A >>
In article <D31C10.2tM@world.std.com>,
Bryan Butler <butler@world.std.com> wrote:
>I am having problems programming an in-circuit Intel/Altera FX780 device.
>I get frequent verify errors and occasional "unable to open device" messages.
>Also, it seems like once I program it, I have to cycle the power to program it
>again. (I'm only trying to program the SRAM at this point, not the PROM).
I've never seen this happen before.  The command for programming the RAM
goes over the JTAG port and should not need a power-on reset to be effective.

>
>I'm using the Intel flex cable and programming software (pengn). Although I
>lengthened the cable for convenience, this doesn't seem to have any negative
>effect. If anything, it seems more reliable with the longer cable!
The only time I've seen this is with noise on the TCK signal.  You might
try a 7414 to clean up the clock at the 780 end of the cable.  How did
you lengthen the Intel cable?

>
>Anyone else notice problems with these devices?
>
>--
>-------
>Bryan Butler
>butler@world.std.com


-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 653
Subject: [shin]Synthesis tools ported to Linux available???
From: gshin@netcom.com (George Shin)
Date: Sun, 29 Jan 1995 07:46:14 GMT
Links: << >>  << T >>  << A >>
Hello, i'm looking for following synthesis tools for the Linux platform. I
believe most of them if not all are University tools. Thanks much.

bdsyn
espresso
sis/misII

-gshin

PS BTW, i'm in search of tool like bdsyn but can directly work on FSM rather
   than just on the combinatoric logic portion.



Article: 654
Subject: looking for room mate, FPGA 95 - Monterey
From: thakur@cs.utexas.edu (Shashidhar A. Thakur)
Date: 29 Jan 1995 14:22:24 -0600
Links: << >>  << T >>  << A >>
Hi,
 I am looking for someone to share a room during the FPGA Symposium
in Monterey from 12-14 Feb. If you are looking for a room-mate
please contact me by email.

Thanks,
Shashidhar
-- 
--
E-mail: thakur@cs.utexas.edu     Phone: (512) 471-9753     
Office: PAI 5.38
World-Wide-Web: http://www.cs.utexas.edu/~thakur/


Article: 655
Subject: Inefficiency(?)
From: eleventh@nyx10.cs.du.edu (Edward Leventhal)
Date: 30 Jan 1995 07:04:17 -0700
Links: << >>  << T >>  << A >>

Hi,
 
   I was wondering how people are dealing with the following situation or
similar situations.

   I am using Viewlogic's Prosynthesis to target an XC4000 Xilinx FPGA
from a VHDL-based design.  The VHDL has been written, the logic gates
have been synthesized, and the resulting logic has been simulated.
The simulation looks good, and I am now about to use the XACT 5.0 tools
to go through the PPR process.
   
   However, since the synthesis tools, only use basic parts of the
XC4000 library (i.e. AND, NAND, NOR, OR gates and FDCE (flip flops), etc),
the FPGA targetting appears extremely inefficient.  I created a 
"top-level" which consisted of hierarchical elements which totalled about
4000 "cells" (gates and flip flops).  I used the "estimate" option on
the PPR, and I targeted a 4013 FPGA.  The estimate was that
95% of the function generators were needed to be used.

  My understanding is that the only way around this poor use of resources
is to instantiate the library parts in the VHDL code.  That is,
XC4000 adders, multiplexers, etc. that would map to the FPGA more
efficently could be explicitly used. This seems to
take a away from the whole point of the VHDL design in the first place!
I would have just used a schematic capture approach instead!

  Please tell me if there are any solutions to this dilemma.  Is this
inefficient use of FPGA resources just a consequence of a high-level
design approach (i.e. VHDL) that must be endured?  

Thanks,

   Ed






Article: 656
Subject: Re: NeoCAD Experience
From: bobe@prebman.tv.tek.com (Bob Elkind)
Date: 30 Jan 1995 18:22:51 GMT
Links: << >>  << T >>  << A >>
In article <3gb0g1$68h@aurns1.aur.alcatel.com> wolf@aur.alcatel.com writes:
>In article h0h@news.tv.tek.com, bobe@prebman.tv.tek.com (Bob Elkind) writes:
>> davelec@extro.ucc.su.OZ.AU (David le Comte) writes:
>> >kenn@neocad.com (Kenn Perry) writes:
>> >
>> >>   ...   PC prices begin
>> >>at $995 U.S. list.  NeoCAD's new, low-cost Access system
>> >>provides support for all vendor's devices under 3K gates
>                                              **************
>
>> >>(approximate), timing-driven place and route, an EDA vendor
>> >>integration kit for $2,995.  This configuration has been very
>>                       | 
>>                       I *think* you mean $12,995. -- be
>> 
>> >>attractive to new users of FPGAs.
>
>I think the $2,995 is a *new* deal from NeoCAD.  Notice the *under 3K gates*.
>Sounds smart to me.  This is a cheap way to get vendor independence and 
>try out NeoCAD.  The other $4,995 single vendor deals claim to give you a 
>"better" router with a *path* to vendor independence.  You might try getting 
>a new quote if less than 3K gates does anything for you.
>
>- Bill Wolf, Raleigh NC
>- My opinions, NOT my employer's

You are right.  Kenn Perry from Neocad replied via email to clear up
my confusion.

To sum up:

Neocad has three product lines --
  Access   -- under 3K gates, entry level product, starting at $995 US
  Catalyst -- up to (and including) 15K gates
  Paragon  -- includes >15K gate devices

If there are differences in the place/route tools, or just differences
in the supported device libraries (for the different size ranges of devices),
I'm not sure.

There are options within the Catalyst and Paragon lines for single/dual/all
vendor/FPGA/lib support (e.g. Xilinx 3K, ATT 2C, Actel, Moto, etc.)

There are upgrade paths from the lower product lines to the higher product
lines.  Talk to a NeoCad rep (or kenn@neocad.com) for specific prices.

There!  I've told you all that I know (and perhaps a bit more!).
I don't work for NeoCad, I'm just a customer.

Bob Elkind, Tektronix TV Products



Article: 657
Subject: Seeking Info on LPM
From: mrhenry@sandia.gov (Matthew R Henry,2274,4-2630)
Date: Mon, 30 Jan 1995 20:30:06 GMT
Links: << >>  << T >>  << A >>
Can anyone tell me how or where to obtain specifications for the
Library of Paramterized Modules (LPM)?  Thanks for your help.

Matt Henry
Sandia National Laboratories



Article: 658
Subject: Re: Exemplar vs. NeoCAD
From: david@fpga.demon.co.uk (David Pashley)
Date: Mon, 30 Jan 1995 22:07:52 +0000
Links: << >>  << T >>  << A >>
Mark,

Your options are actually as follows:

Synthesis:                             Implementation:

Exemplar/                      \       XACT/
MINC (with VHDL option)/   ----->      NeoCAD
ABEL (with VHDL option)/       /
another synthesis tool


The synthesis options in the first column (amongst many others) will 
each provide an output suitable for implementation with Xilinx XACT 
or NeoCAD's FPGA Foundry (these are the only two implementation 
tools on the market for Xilinx). The means of conveying the data 
from the synthesis tool to the implementation tool is usually either 
an EDIF or XNF netlist.
 
I won't comment on the merits of the tools mentioned, since I'm not 
impartial (my employer is UK VAR for two or three of the products 
you mention)!

You will only get back-annotated design files for simulation out of 
the implementation tools (XACT and NeoCAD) since Xilinx performance 
is non-deterministic before place-and-route. For the same reason, 
timing simulation is a worthwhile activity. 

Sorry, we don't have a FAQ for this group (yet), the nearest FAQ is in 
comp.lang.vhdl, which lists all available synthesis tools.

Hope this helps.

BTW, don't worry, you *do* get a download cable with NeoCAD's FPGA 
Foundry! 

David Pashley                 <
 ------------------------  <  <  <  ---------- Email: david@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
| *The EDA Source*         <  <  <               Fax: +44 1280 705196      |
 ---------------------------  <  ------------------------------------------
In article <3g8835$59o@doc.armltd.co.uk> msnook@armltd.co.uk writes:

"I currently have a number of behavioral VHDL models that I need to target
"into Xilinx FPGAs. I currently use the Model Tech VHDL simulator and am
"evaluating the best route to a routed Xilinx 3000 series part. I am not
"interested in automatic partioning or other vendors FPGAs at this stage. I
"am Sun Sparc based so price comparisons with PCs are not really valid.
"
"As I see it I have four options:
"
"1> NeoCAD
"2> Exemplar coupled with XACT
"3> MINC VHDL input filter and XACT
"4> ABEL VHDL input filter and XACT
"....<snip>



Article: 659
Subject: Re: Xilinx Chips
From: kky@itd.dsto.gov.au (Ken Yiu)
Date: 30 Jan 1995 22:21:54 GMT
Links: << >>  << T >>  << A >>
In article MsB@indirect.com, seeker@indirect.com (Stan Eker) writes:
>Ken Yiu (kky@itd.dsto.gov.au) wrote:
>: Hi. 
>: This is not an appropriate forum for this question,
>: so my apologies in advance. I am, however, not aware
>: of any appropriate news group.
>
>None of the normal groups want to encourage suppliers and vendors to trash
>the 'net.  Your normal recourse should be through alternate distribution,
>and especially NOT through this group.  Try calling the factory, first, as
>they'll have a better handle on who has what parts.
>
>If you don't think distributors & vendors are slavering at the thought of
>forcing their vapid advertising in the faces of 10 million possible
>customers, then you aren't very familiar with the breed.  Most salesmen have
>all the tact and morals of a weasel, for the same reasons.
>

I appreciate your views - and share them to an extent.
I have tried Xilinx direct, and the Xilinx worldwide
distributors network - in fact this post was a last 
resort/act of desperation.  

FYI, it seem that independant component distributors (e.g. 
America II etc) are the most useful group in this type of
situation. The factory is NOT useful, as they always 
quote you 2 month lead times. The distributor is more
likely to be able to source (limited) stocks. 

I apologise if I offended/bothered you with the post.

Regards,
Ken. 

Disclaimer: These views are not necessarily those of my employer.




Article: 660
Subject: Re: [shin]Synthesis tools ported to Linux available???
From: pegu@scimiar.dolphinics.no (Petter Gustad)
Date: 30 Jan 1995 23:19:26 GMT
Links: << >>  << T >>  << A >>
George Shin (gshin@netcom.com) wrote:
: Hello, i'm looking for following synthesis tools for the Linux platform. I
: believe most of them if not all are University tools. Thanks much.

: bdsyn
: espresso
: sis/misII

: -gshin

: PS BTW, i'm in search of tool like bdsyn but can directly work on FSM rather
:    than just on the combinatoric logic portion.

I compiled espresso on my Linux PC more than a year ago and I think
it compiled straight out the box without any modifications. Try archie
to search for espresso.

--
--------------------------------------------------------------------
Petter Gustad                             E-mail: pegu@dolphinICS.no
Hardware Design Engineer                  Tel.: +47 22 62 70 00
Dolphin Interconnect Solutions A.S.       Fax.: +47 22 62 71 80
Street address:                           Mailing address:
Olaf Helsets vei 6                        P.O. Box 70, Bogerud
Oslo, Norway                              N-0621 Oslo, Norway
--------------------------------------------------------------------


Article: 661
Subject: Re: Inefficiency(?)
From: cshelor@onramp.net (Charles Shelor)
Date: 31 Jan 1995 13:25:07 GMT
Links: << >>  << T >>  << A >>

>
>Hi,
> 
>   I was wondering how people are dealing with the following situation or
>similar situations.
>
>   I am using Viewlogic's Prosynthesis to target an XC4000 Xilinx FPGA
>from a VHDL-based design.  The VHDL has been written, the logic gates
>have been synthesized, and the resulting logic has been simulated.
>The simulation looks good, and I am now about to use the XACT 5.0 tools
>to go through the PPR process.
>   
>   However, since the synthesis tools, only use basic parts of the
>XC4000 library (i.e. AND, NAND, NOR, OR gates and FDCE (flip flops), etc),
>the FPGA targetting appears extremely inefficient.  I created a 
>"top-level" which consisted of hierarchical elements which totalled about
>4000 "cells" (gates and flip flops).  I used the "estimate" option on
>the PPR, and I targeted a 4013 FPGA.  The estimate was that
>95% of the function generators were needed to be used.
>
>  My understanding is that the only way around this poor use of resources
>is to instantiate the library parts in the VHDL code.  That is,
>XC4000 adders, multiplexers, etc. that would map to the FPGA more
>efficently could be explicitly used. This seems to
>take a away from the whole point of the VHDL design in the first place!
>I would have just used a schematic capture approach instead!
>
>  Please tell me if there are any solutions to this dilemma.  Is this
>inefficient use of FPGA resources just a consequence of a high-level
>design approach (i.e. VHDL) that must be endured?  
>
>Thanks,
>
>   Ed
>


The _SOLUTION_ to this problem requires the synthesis vendors to SYNTHESIZE
to higher level constructs.  Then when they TARGET a particular device they
can take advantage of the special features within that device.  You might
be able to get Exemplar or Synopsys to benchmark your VHDL code as both
of them utilize SOME but not ALL (yet) of the Xilinx special functions.

A compromise is to instantiate only the largest of the inefficient blocks
and let the synthesis tool generate the others.  Typically, counters and
adders are the only components that need to be instantiated.  Actually you
will still receive significant benefits from using HDLs in the random logic
and state machine areas.

Be sure to complain loudly to the synthesis vendors or they will not move
their intermediate synthesis form to a higher level representation!

Good Luck,

Charles

SHELOR ENGINEERING              VHDL Training, Consulting, and models
3308 Hollow Creek Rd            (817) 467-9367
Arlington,  TX  76017-5346      cfshelor@acm.org





Article: 662
Subject: hi-power FPGA applications
From: bobe@prebman.tv.tek.com (Bob Elkind)
Date: 31 Jan 1995 20:25:04 GMT
Links: << >>  << T >>  << A >>



Article: 663
Subject: hi-power FPGA applications
From: bobe@prebman.tv.tek.com (Bob Elkind)
Date: 31 Jan 1995 20:45:11 GMT
Links: << >>  << T >>  << A >>
I am interested in experiences with FPGA designs in applications that
demand >1 watt per package, specifically:

1.  Packaging/cooling  Do you have access to the package/cooling you
    need/want?

2.  AC specs vs. junction temp:  Did you have to derate AC specs
    because of elevated temp operation, did you even check the
    temp vs. speed specs, or did you cross your fingers?

3.  What clock frequencies are you using?  Were you limited
    in gate utilisation and/or operating frequency by power
    and/or cooling considerations?

4.  Did you have unforseen problems?  Surprises? etc.  Or did your
    design tools give you some warning/hint that there might be
    timing vs. power/heat vs. utilisation problems?

5.  If you had probs, what did you do (specifically) to address
    them to complete your project, and what are your plans for
    avoiding similar probs in the future?  Do you see FPGA vendors
    responding to your past problems and/or future aspirations?

5a. (Essay Question [optional, extra credit!])  What are your
    convictions about the *technical* solutions to your specific
    or general problems?  Be as specific or general as you like.

As this list of questions probably intimates, we *have* had
problems with heat vs. pkg. vs. timing;  my agenda is to do some
of the technical marketing research (across the net) that I think
the FPGA vendors need/should do themselves.  Depending upon the
responses, I may find myself alone in an isolated FPGA applications
backwater.  We'll see.

Naturally, the results will be posted to this newsgroup, edited to
avoid commercialism, protect confidentiality, etc.
Thank you for taking the time to respond.

I have no financial interest in *any* FPGA or FPGA/EECAD vendor.

Bob Elkind, Tektronix TV Test & Measurement
bobe@tv.tv.tek.com   503.627.4417


Article: 664
Subject: Re: XC4000 boundary scan configuring. How??
From: barton@qcktrn.com ( Barton Quayle )
Date: 31 Jan 1995 20:54:07 GMT
Links: << >>  << T >>  << A >>
In article rad@darum.uni-mannheim.de, kugel@mp-sun6.informatik.uni-mannheim.de (Andreas Kugel) writes:
> We want to use the JTAG port of the XC4000 familiy to configure these
> devices. Unfortunately there is no detailed description on this topic
> available.

First, I suggest reading the XAPP note in the Xilinx 1994 Data Book (pp 8-37)
It has quite a few details on data format, etc.
 
> In detail my questions are:
> 	how long must I wait from the UPDATE-IR state (instruction
> 	configure) to the SCAN-DR state ? May I go there directly or
> 	only thru the IDLE state ?

I personally don't have any experience with this as we us a uP to drive the
Jtag and always spend quite a bit of time in the Idle state. But I believe
from discussion with Xilinx engineers, that passing through Idle is not required.

> 
> 	If in SHIFT-DR state, may I load all config bits in one sequence
> 	or must I go thru UPDATE-DR after every bit / frame / something ?

The entire bitstream (as defined in the XAPP Note mentioned above) can be 
loaded as one Shift-DR. We do it regularly.

> 
> 	If there is a DSDL file floating around ? (copy please)

Sorry, I confess my ignorance, what is a DSDL.

Be glad to answer any other questions (within myknowledge, of course)

Barton Quayle
Barton@qcktrn.com
Quickturn Design Systems, Inc




Article: 665
Subject: Re: Seeking Info on LPM
From: hage@netcom.com (Carl Hage)
Date: Wed, 1 Feb 1995 09:05:11 GMT
Links: << >>  << T >>  << A >>
mrhenry@sandia.gov (Matthew R Henry,2274,4-2630) writes:
: Can anyone tell me how or where to obtain specifications for the
: Library of Paramterized Modules (LPM)?  Thanks for your help.

Ask for EIA/IS-103 "EDIF Library of Paramterized Modules (LPM)"

published by:

          Electronic Industries Association
          Standard Sales Department (Attn: Cecelia Fleming)
          2001 Pennsylvania Avenue, N.W.
          Washington D.C. 20006, USA
 
Available from:
	Global Engineering Documents 1-800-854-7179 or 1-303-792-2181


Article: 666
Subject: "on-fly" reprogrammable devices/research
From: mvasilko@bournemouth.ac.uk (Milan Vasilko)
Date: 1 Feb 1995 06:51:06 -0600
Links: << >>  << T >>  << A >>
Hello !


I wonder if anyone has any information about:

- commercially available "on-fly" reprogrammable devices, i.e. devices
  which can be programmed during their operation (or better part of the
  chip can be reprogrammed while another parts are still operational).
  I am interested in any type of device FPGA, PLD etc.
  (I am only aware of AT6000 family from Atmel)

- any research activities on-going in this area

Thanks in advance for any references or comments on this.


Milan.


o--------------------------------o-------------------------------o
|   Milan VASILKO   (Mr.)        |     School of Electronics     |
|                                |    Bournemouth  University    | 
|   mvasilko@bournemouth.ac.uk   |          Fern Barrow          |
|   tel: +44-(0)202-595 101      |     Poole, Dorset BH12 5BB    |
|   fax: +44-(0)202-595 314      |         UNITED KINGDOM        |
o--------------------------------o-------------------------------o


Article: 667
Subject: Interesting DA Sources - issue 101 (Feb 95)
From: info <info@cadmazing.com>
Date: 1 Feb 1995 15:30:57 GMT
Links: << >>  << T >>  << A >>
This is our second posting to the internet of interesting
design automation sources throughout the world-wide web.
There was a very large volume of newsgroup readers who
visited our "DA-related Information on the WEB", that we
decided to continue offering this free public service. We also
received additional pointers from our readers. If you have
any additional favorites of your own, send them to
webmaster@cadmazing.com and we will include them in next
month's update. We will try to update this monthly (as
time allows) so check back next month for intersting
pointers.


Here are the updates for Feb 95. To access these, set your

url to http://www.cadmazing.com/cadmazing


Power Modeling
Electronic Design Automation Brief of Grand Unification Theory
Grand Unification Theory List of EDA- and Design-Related Software
Microelectronics and Computer Technology Corporation
Multichip Systems Design Advisor (MSDA)
Ptolemy
VHDL Tid-Bits
NanoFab Home Page
ASIC & EDA September 1993 Issue (*demo*)
SRC University Fabrication Facilities Database
Directory of ISDATA
Microelectronic Systems Newsletter
Universities Listing of the U.C. Berkeley Design Technology Warehouse

News groups
Engineering-related newsgroups
Newsgroup: comp.lsi.cad
Newsgroup: comp.cad.cadence
Newsgroup: comp.cad.compass
Newsgroup: comp.cad.synthesis
Newsgroup: comp.lang.verilog
Newnews: Sci.electronics.cad by date
Newnews: Comp.arch.fpga by date
ESNUG (Synopsys user group) Archive by date




Article: 668
Subject: unsubscribe
From: ckwok@netcom.com (Chris Kwok)
Date: Wed, 1 Feb 1995 17:53:33 GMT
Links: << >>  << T >>  << A >>
Please unsubscribe me from the mailing list. Thanks. 



Article: 669
Subject: Re: "on-fly" reprogrammable devices/research
From: devb@jazzmin.vnet.net (David Van den Bout)
Date: 1 Feb 1995 14:17:43 -0500
Links: << >>  << T >>  << A >>
In article <22093.9502011123@bmth.ac.uk>,
Milan Vasilko <mvasilko@bournemouth.ac.uk> wrote:
->- commercially available "on-fly" reprogrammable devices, i.e. devices
->  which can be programmed during their operation (or better part of the
->  chip can be reprogrammed while another parts are still operational).
->  I am interested in any type of device FPGA, PLD etc.
The Altera FLEXlogic 8160 has this feature in a more limited sense than
the Atmel part: half of the 8160 can be reprogrammed while the other
half is running.


-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 670
Subject: emacs mode for AHDL? VHDL?
From: timsc@hwcae.Honeywell.COM (Tim Schneider)
Date: 1 Feb 1995 17:02:12 -0700
Links: << >>  << T >>  << A >>

I have an emacs mode for verilog.. I *thought* there was
one out there for VHDL.  Anyone seen or heard of one
for Altera's HDL (AHDL)

thanks in advance !

 -tim

schneider@email.iac.honeywell.com




Article: 671
Subject: Re: "on-fly" reprogrammable devices/research
From: aaronf@cats.ucsc.edu (Aaron Ferrucci)
Date: 2 Feb 1995 03:34:56 GMT
Links: << >>  << T >>  << A >>

In article <22093.9502011123@bmth.ac.uk>,
Milan Vasilko <mvasilko@bournemouth.ac.uk> wrote:
>I wonder if anyone has any information about:
>
>- commercially available "on-fly" reprogrammable devices, i.e. devices
>  which can be programmed during their operation (or better part of the
>  chip can be reprogrammed while another parts are still operational).
>  I am interested in any type of device FPGA, PLD etc.
>  (I am only aware of AT6000 family from Atmel)
>

Look into the CLAy family from Nat'l Semiconductor-
they claim partial reconfigurability at the 'cell'
level. A CLAy cell can implement functions of several
gates and an optional flip-flop, so it's fine-grain
reconfigurability.  My only experience with these
devices is a glance at their preliminary data sheet,
so I can't advise on their practical utility.  For more 
info, contact Tim Garverick, garv@berlioz.nsc.com.

The usual disclaimer applies.
-Aaron Ferrucci



Article: 672
Subject: [shin]Anyone ported or have patches for OCTTOOLS to Linux?
From: gshin@netcom.com (George Shin)
Date: Thu, 2 Feb 1995 06:54:33 GMT
Links: << >>  << T >>  << A >>
Hello, does anyone tried or have ported OCTTOOLS to Linux or have the
patches to build them with gcc? Currently i have ported 'mustang',   
'espresso' and got the 'sis' (successor to earlier 'misII'). Any help
would be greatly appreciated. Thanks much...

-gshin

PS Is OCTTOOLS even available as PD or $$$ needed to Berkeley?

PSS I have the Linux ported Ptolemey and was wondering if Ptolemey is part
    of OCTTOOLS package?



Article: 673
Subject: Re: "on-fly" reprogrammable devices/research
From: khurley@ea.com
Date: 2 Feb 1995 16:50:07 GMT
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Check out Lattice Semiconductor ISPLSI, a starter kit that 
includes window's software to compile logic blocks,  
In-Circuit Programmable/ very easy to use, the starter kit
only contains ability to use 1016 devices which has 32 i/o
pins and some input/clk pins as well and is $99.00.
The upgrade is more expensive, I picked it up for $650.00
and includes more complex devices.




In article <22093.9502011123@bmth.ac.uk> mvasilko@bournemouth.ac.uk (Milan Vasilko) writes:
>Hello !
>
>
>I wonder if anyone has any information about:
>
>- commercially available "on-fly" reprogrammable devices, i.e. devices
>  which can be programmed during their operation (or better part of the
>  chip can be reprogrammed while another parts are still operational).


Article: 674
Subject: Configuring XC4000 with Xchecker/JTAG
From: dch@acsu.buffalo.edu (David C Hoffmeister)
Date: Thu, 2 Feb 1995 17:22:16 GMT
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I am currently working on a board that will use XC4013's and possibly a
XC4005H and/or XC4003H.  I was thinking about using the Xchecker cable
supplied by Xilinx to configure the chips on the board until the design 
is stable enough to warrant using PROM's.  Has anyone ever tried this?
Is it possible/worhtwhile?  Specifically, is it possible to configure
multiple chips in daisy-chain fashion using the Xchecker cable?  Would
using the JTAG port be a better option?

We are also planning on using the boundary scan capability to check the
design.  However, we are having difficulty finding suppliers of the 
equipment necessary, especially since we are still not sure exactly what
equipment we would need ( Hey, we're only students after all ).  Does
anyone know what companies I could contact for catalogs/databooks/information?

Thanks in advance for any advice.

David Hoffmeister
University of Buffalo




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