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Messages from 825

Article: 825
Subject: Re: DSP in FPGA ?
From: rob@vanbc.wimsey.com (Rob Semenoff)
Date: 7 Mar 1995 17:11:24 -0800
Links: << >>  << T >>  << A >>
I should be more specific. I am looking at using
DSP chips for a graphics application, because of their
high arithmetic power, and I'd like to know if I can implement fast
polynomial, and other, calculations in FPGA with better
price/performance. 

In article <3jgvu4$bee@vanbc.wimsey.com>,
Rob Semenoff <rob@vanbc.wimsey.com> wrote:
>
>Hi everybody,
>
>I want to implement a special purpose DSP algorithm in FPGA,
>hoping that it will be faster,cheaper than the
>alternatives which are:
>
> A general purpose DSP microprocessor
> An ALU chip using an external state machine
>
-rob
--


Article: 826
Subject: Looking for someone to share room in hotel for ISCAS-95
From: dasgupta@risky.ecs.umass.edu (Aurobindo Dasgupta)
Date: 8 Mar 1995 19:03:50 GMT
Links: << >>  << T >>  << A >>

Hi,
I am looking for someone with whom I could share a room in 
Seattle on May 1,2 and 3. I will be presenting a paper in ISCAS-95.

Thanks,


Aurobindo Dasgupta




Article: 827
Subject: Bit serial multipliers in FPGAs
From: tessier@ROEBLING.LCS.MIT.EDU (Russ Tessier)
Date: 8 Mar 1995 21:05:15 GMT
Links: << >>  << T >>  << A >>


I am interested in learning more about implementations of bit-serial
multipliers in lookup-table based FPGAs. Input operands for my design
are eight bits long.
 
A pointer to any relevant literature with implementation examples would
be appreciated.
 
 
Thanks
 
Russ Tessier 
MIT Lab for Computer Science




Article: 828
Subject: XNF translator
From: linchih@guitar.ece.ucsb.edu (C. C. Lin)
Date: 8 Mar 95 21:59:22 GMT
Links: << >>  << T >>  << A >>

Hi,

  Are there any tools available to translate BLIF
FORMMAT to Xilinx XNF format, and vice versa?

Any comment and hints?

Thanks for your help!

Chih-chang Lin


Article: 829
Subject: goof on cheaper Xilinx price ($1K US, not $100)
From: seeker@indirect.com (Stan Eker)
Date: Thu, 9 Mar 1995 04:35:48 GMT
Links: << >>  << T >>  << A >>
Yep, I heard $995 as $99.50.  Oops.

As an aside, the lower-priced version is the same CD and books that sell for
$5K or so, just without the 4K/5K support since it's missing the dongle.
I guess the 5.1 version will run 2K/3K and EPLD parts without the infamous
dongle (if you're looking for a second copy, this is a hint).  Not that I'm
suggesting you void your user agreement on this seriously overpriced package.

And yeah, we fell for it and bought BOTH systems, foolishly thinking there
was more of a difference than merely a missing dongle.  Silly us.



Article: 830
Subject: Inverse-Fourier waveform synthesis
From: lfadden@harris.com (Lee Fadden)
Date: Wed, 8 Mar 1995 21:48:07
Links: << >>  << T >>  << A >>
I may be in the wrong forum for this, but I've seen FFT and the like 
mentioned from time to time; so I thought I'd give it a try.

My application involves generating complex sound waves by adding and
mulitplying together sines waves of many frequencies and relative phases.
I thought I would generate the waves using Forth (for speed) and feed the
amplitude stream to a DAC.  But, having not tested the idea yet, I fear that 
bandwidth might still be a problem event on a 90 Mhz Pentium, since I have
to do alot of math in real time to generate 44,100 16-bit amplitude values
per second.

So, can anyone suggest a less borderline way of doing this, say,
with a DSP card?  I know that DSPs can be implemented with FPGAs, but I'm
not certain this is necessary.  I guess the best way is to get the DSP to
do all the math (that solves the bandwith problem).  Can anyone recommend
a DSP card and development software, or point me to a forum?  Thanks.

Lee



Article: 831
Subject: Re: Inverse-Fourier waveform synthesis
From: petersr@fpga.ee.byu.edu (Russell Petersen)
Date: 9 Mar 1995 10:28:27 -0700
Links: << >>  << T >>  << A >>

In article <lfadden.69.0015CDF9@harris.com>, lfadden@harris.com (Lee Fadden) writes:
|> I may be in the wrong forum for this, but I've seen FFT and the like 
|> mentioned from time to time; so I thought I'd give it a try.
|> 
|> My application involves generating complex sound waves by adding and
|> mulitplying together sines waves of many frequencies and relative phases.
|> I thought I would generate the waves using Forth (for speed) and feed the
|> amplitude stream to a DAC.  But, having not tested the idea yet, I fear that 
|> bandwidth might still be a problem event on a 90 Mhz Pentium, since I have
|> to do alot of math in real time to generate 44,100 16-bit amplitude values
|> per second.
|> 
|> So, can anyone suggest a less borderline way of doing this, say,
|> with a DSP card?  I know that DSPs can be implemented with FPGAs, but I'm
|> not certain this is necessary.  I guess the best way is to get the DSP to
|> do all the math (that solves the bandwith problem).  Can anyone recommend
|> a DSP card and development software, or point me to a forum?  Thanks.
|> 
|> Lee
|> 


	Check out comp.dsp for an answer to this question.  You could
do this with an FPGA but since you are interested in audio rate processing
a DSP may be better, depending on the number of multiplications you expect
to be doing per output sample.

- Russell Petersen
  petersr@fpga.ee.byu.edu


Article: 832
Subject: Re: Bit serial multipliers in FPGAs
From: petersr@fpga.ee.byu.edu (Russell Petersen)
Date: 9 Mar 1995 10:35:18 -0700
Links: << >>  << T >>  << A >>

In article <3jl66b$5pe@GRAPEVINE.LCS.MIT.EDU>, tessier@ROEBLING.LCS.MIT.EDU (Russ Tessier) writes:
|> 
|> 
|> I am interested in learning more about implementations of bit-serial
|> multipliers in lookup-table based FPGAs. Input operands for my design
|> are eight bits long.
|>  
|> A pointer to any relevant literature with implementation examples would
|> be appreciated.
|>  
|>  
|> Thanks
|>  
|> Russ Tessier 
|> MIT Lab for Computer Science
|> 
|> 

	I have been working on results of FPGA multiplication for
part of my thesis.  My experience so far with bit-serial mults. is
that they are simple to build if both operands are unsigned but the
implementation can get a bit ugly with FPGAs if you want two's
complement multiplication, depending on how you want to feed in your
operands.  With unsigned bit-serial multipliers I have achieved 80 Mhz
clock rates.  Lyon's paper on bit-serial multiplication is pretty much
a standard reference for bit-serial mult. but the paper does have an
error.  Look for "Two's Complement Pipeline Multipliers" by R.F. Lyon in
IEEE transactions on Communications, April 1976 pgs. 418-424.

 ___________________________          ----- 
   Russell Petersen                   || BYU ||
   Brigham Young University           ||     || 
   Reconfigurable Hardware Lab          ----- 
   petersr@fpga.ee.byu.edu            ---------  
   voice: (801) 378-7206             |  -    - | 
   ___________________________        ---------  


Article: 833
Subject: FPGA related papers
From: a.osama@ic.ac.uk
Date: Thu, 9 Mar 1995 19:03:42 GMT
Links: << >>  << T >>  << A >>
  Hi,

  If anyone would like to receive a PostScript copy of the 
  following papers, please e.mail me.
  
  1. ISCAS'94 - Virtual Hardware and the Limits of Computational Speed-up
  2. ICCD'94  - Area & Time limitations of FPGA-based Virtual Hardware
        
    (both by Albaharna, Cheung, & Clarke)

--------------------------------------------------------------------------
-- Osama T. Albaharna <a.osama@ic.ac.uk>                                --
--                                                                      --
-- Information Engineering Section                                      --
-- Department of Electrical and Electronic Engineering                  --
-- Imperial College, Exhibition Road, SW7-2BT, London, U.K.             --
--                                                                      --
-- Tel: +44-171-589-5111(ext 56210)               Fax: +44-171-581-4419 --
--------------------------------------------------------------------------


Article: 834
Subject: RE: FPGA Custom Computing Machine
From: a.osama@ic.ac.uk
Date: Thu, 9 Mar 1995 19:06:36 GMT
Links: << >>  << T >>  << A >>

   linchih@guitar.ece.ucsb.edu (Chih-chang Lin) wrote:

>  
>  I am looking for the information (call for paper, 
>  registration)for "FPGA Custom Computing Machine workshop".
>

   See info in http://www.super.org:8000/FPGA/caf.html

-- Osama Albaharna <a.osama@ic.ac.uk>



Article: 835
Subject: RE: Bit serial multipliers in FPGAs
From: a.osama@ic.ac.uk
Date: Thu, 9 Mar 1995 19:19:11 GMT
Links: << >>  << T >>  << A >>

   tessier@ROEBLING.LCS.MIT.EDU (Russ Tessier) wrote:

>  I am interested in learning more about implementations of bit-serial
>  multipliers in lookup-table based FPGAs. Input operands for my design
>  are eight bits long.
> 
>  A pointer to any relevant literature with implementation examples would
>  be appreciated.
 
Hi Russ,

    See  "Implementation and Performance Evaluation of Cellular Array
         Multipliers using FPGAs"
    
    by   Arindam Saha  &  Rangasayee Krishnamurthy
         (Missisippi State University)

    in   Proc. of the 26th Southeastern Symposium on System Theory, 
         20-22 March, 1994. 

-----------------------------------
Osama Albaharna <a.osama@ic.ac.uk>
Information Engineering Section
Imperial College, U.K.
-----------------------------------



Article: 836
Subject: Re:FPGA bit serial multipliers, correction
From: randraka@ids.net
Date: Thu, 9 Mar 95 20:10:13 GMT
Links: << >>  << T >>  << A >>
Oops!  I oversimplified my brief description of the bit serial multiplier in my
earlier post.  The bit cell is a full adder with registers on the sum and carry
outputs and with the carry output wrapped back around to the input as I stated. 
One of the other inputs to the cell comes from the sum output of the previous
cell, and the other is fed with the AND of the serial input and the
corresponding bit in the parallel input.  For a fixed parallel input, the ANDs
get eliminated and the serial input gets fed only to cells corresponding to
ones in the parallel input.  The zero bits can be reduced to a single register

The individual 'carry-save' adders can be extremely fast.  The performance of
the bit serial multiplier is limited by the distribution of the serial input
across the cells in most of the FPGA architectures.  A sixteen bit (on the 
parallel input) multiplier in the Atmel/NSC parts can do better than a 30 MHz 
bit rate, even with the local/global bus connections.
 
My apologies if I caused any confusion in the earlier post.

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
email randraka@ids.net  


Article: 837
Subject: Smith's web page (Was: Limits on on-chip FPGA virtual .....)
From: kee@das.harvard.edu (Kee Chan)
Date: 9 Mar 1995 22:07:23 GMT
Links: << >>  << T >>  << A >>
There have been a few requests on the work of Razdan and Smith.  You can access
their papers thru Prof. Smith's homepage.

	http://das-www.harvard.edu/users/faculty/Michael_Smith/Michael_Smith.html

well, if that is too long, follow the link from http://das-www.harvard.edu/
and find out new and exciting research at Harvard :-)

-- 
- Kee
kee@das.harvard.edu


Article: 838
Subject: How to partitions the design by ppr ?
From: fengwct@ku.ac.th (Wichai Tang)
Date: 10 Mar 1995 00:59:52 GMT
Links: << >>  << T >>  << A >>
Hi everybody,
	Does anybody around here use the XACT program from xilinx ? ....
	I need some help. I need to know that if we design the circuit 
that fit on xc4010. But we want to separate it into several chips such as 
2 of xc4005. How can we do ?  Can we use PPR program to do that for us ?
Or we must cut the circuit down into 2 circuits ourself ? 
	Any help would be appreciate.
Regard,
Wichai Tang


Article: 839
Subject: Re:FPGA bit serial multipliers
From: mtmason@ix.netcom.com (martin mason)
Date: 10 Mar 1995 08:14:14 GMT
Links: << >>  << T >>  << A >>
In <3joqgq$9f@paperboy.ids.net> randraka@ids.net (Ray Andraka)writes: 

stuff deleted.....

>The individual 'carry-save' adders can be extremely fast.  The performance of
>the bit serial multiplier is limited by the distribution of the serial input
>across the cells in most of the FPGA architectures.  A sixteen bit (on the 
>parallel input) multiplier in the Atmel/NSC parts can do better than a 30 MHz 
>bit rate, even with the local/global bus connections.

The critical path for this type of macro is usually in routing to the arithmetic 
logic and this can be 'reduced' by registering (pipelining) the 
incoming/outgoing data to push data rates extreamly high (>70Mhz in some cases).

Atmel is currently building a bit serial multiplier macro generator for its 
SRAM reconfigurable FPGA family, to compliment its growing set of arithmetic 
parameterizable macros such as : pipelined parallel multipliers; several 
different flavors of accumulator and adder; FIR filters; etc., more are being 
added - let us know what you would like to see.  Questions, comments or 
literature requests should be sent to martin@atmel.com.

Martin Mason
FPGA Apps Engineer
Atmel Corp.  (San Jose)
martin@atmel.com or fpga@atmel.com


Article: 840
Subject: Re: Can I implement a digital PLL in an FPGA??
From: olsson@plasma.kth.se (Goran Olsson, Plasma Physics, KTH)
Date: 10 Mar 1995 09:03:58 GMT
Links: << >>  << T >>  << A >>
In article <3j034s$rn6@newshound.uidaho.edu>, lharold@mrc.uidaho.edu (Len Harold) writes:
>David Hough (dave@sectel.com) wrote:

>: Most designers I know are willing to work pretty hard to avoid analog things
>: like VCOs.

>Most definitely.

Looks like you are unfortunate to know few designers competent in analog
design. ;-)

In The Real World synchronization by a PLL & VCO sometimes is
unavoidable: In a system collecting samples, the phase jitter of +- one
tick introduced by digital PLL-less synchronization is the last thing
you want.

In a digital system receiving asynchronous inputs, there is always
the problem with setup and hold times getting violated. The designer
must address the problem of metastable states and be up to the job of
verifying the error rate to an acceptable figure. (It can't be zero.)

The digital part of a PLL can be as simple as a single XOR gate.  

I am presently designing a system architecture where the ~50MHz clock
for entire digital system including the microprocessor is phase locked
to a 136 kbit/s telemetry channel. Metastable states are avoided and
equidistant sampling is assured. The PLL will most likely be executed as
part of an FPGA.

=========================================================================
                              Goran Olsson
 Alfven Laboratory, Plasma Physics, Space Group, Electronic Engineering,
         KTH (Royal Institute of Technology), Stockholm, Sweden
        F1 - The Electric Field Experiment on the FREJA satellite
                      Two years in orbit 6 Oct 1994
                           olsson@plasma.kth.se
                 http://www.plasma.kth.se/alfven-lab.html
=========================================================================


Article: 841
Subject: Re: Questions of implementing asynchronous circuits using FPGAs.
From: holger@eiss.ira.uka.de (Holger Hellmuth)
Date: 10 Mar 1995 16:13:15 +0100
Links: << >>  << T >>  << A >>
AMD:

I have the data books of the Mach devices of AMD, and in it the Mach215
is expressively designated for asynchronous operation.
Each output macrocell can be clocked by its own product term. The polarity
of the clock is programmable for each macrocell. Individual 
asynchronous reset and preset and three-state product terms for 
each macrocell. 

Furthermore all the Mach3 and Mach4 devices are able to do asynchronous
operation. They have everything the Mach215 has except the programmable
clock polarity, and only one of asynchrounous reset or preset is
(alternatively) available at a macrocell. And they are able to
build RS- and JK-flipflops, not only D-, T-flipflops and Latch.

So it gets down to this: if individual clocks and either a reset or preset
are good enough for you, you have a wide choice, if you need both 
asynchronous reset and preset, only the Mach215 applies. 

XILINX:

Their EPLD line (XC7xxx) is not designed for asynchronous operation. They have
no individual clock. But they have one individual product term for asynch.
reset and preset, so it is remotely possible to use it asynchronously.

The XC3000 devices have individual clocks and individual reset (one for both flipflops
in a CLB/macrocell), but no preset.

The XC4000 family is somewhat comparable with the Mach3 and Mach4 family in that it has
either an asynchronous reset or preset, but not both in a flipflop.

Hope this helps,
							Holger.
-- 

Holger Hellmuth at Uni Karlsruhe
<hellmuth@ira.uka.de>


Article: 842
Subject: Re: Inverse-Fourier waveform synthesis
From: seamang@westminster.ac.uk (Graham Seaman)
Date: Fri, 10 Mar 1995 17:44:25 GMT
Links: << >>  << T >>  << A >>
In article <lfadden.69.0015CDF9@harris.com> lfadden@harris.com (Lee Fadden) writes:
>My application involves generating complex sound waves by adding and
>mulitplying together sines waves of many frequencies and relative phases.
>I thought I would generate the waves using Forth (for speed) and feed the
>amplitude stream to a DAC.  But, having not tested the idea yet, I fear that 
>bandwidth might still be a problem event on a 90 Mhz Pentium, since I have
>to do alot of math in real time to generate 44,100 16-bit amplitude values
>per second.
>
>So, can anyone suggest a less borderline way of doing this, say,
>with a DSP card?  I know that DSPs can be implemented with FPGAs, but I'm
>not certain this is necessary.  I guess the best way is to get the DSP to
>do all the math (that solves the bandwith problem).  Can anyone recommend
>a DSP card and development software, or point me to a forum?  Thanks.
>
>Lee
>
This may be very out of line depending on your particular application,
but have you considered doing the same thing but using Walsh functions
as your basis instead? They're very easy to generate using FPGAs
(you just need lots of XORs) and to sum, and there are relationships
with sine/cosine functions ('cal' and 'sal') you can use for your
phase shift... I once built a little system with old TTL parts for
this

Graham


-- 
--------------------------------------------------------------------
Graham Seaman, School of Computer Science, 
University of Westminster, 115 New Cavendish St.  London W1M 8JS 
email:  seamang@wmin.ac.uk www: http://www.wmin.ac.uk/~seamang


Article: 843
Subject: FPGA multi-chip modules ?
From: rob@vanbc.wimsey.com (Rob Semenoff)
Date: 10 Mar 1995 13:16:12 -0800
Links: << >>  << T >>  << A >>
I presume vendors are increasing FPGA density by going
for bigger dies and smaller feature size.

Are any trying to get more logic into a package for
less money by interconnecting dies in a package
in some programmable, or customer-specified way ? 

-rob


Article: 844
Subject: SNUG 95 in 12 Days! OVI in 17 Days!
From: jcooley@world.std.com (John Cooley)
Date: Fri, 10 Mar 1995 21:52:10 GMT
Links: << >>  << T >>  << A >>

Head's Up!  SNUG's happening in 12 days!  OVI's happening in 17 days!
NOW's the time to register for these conferences, reserve those hotel
rooms and book those flights to San Jose, California before they sell
out!  (I've included the SNUG '95 info sheet in this message; you
can get the OVI info from comp.lang.verilog on the Internet.)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

P.S.  For you SNUG '95 attendees: if you need any materials to do a quick
Verilog/VHDL -> Synopsys design (like coding style templates, etc.) make
sure you bring it with you to SNUG '95.  I'm judging the Design Contest
where you'll be given 1 1/2 hours to create a quickie design from a spec
and synthesize it to the fastest or smallest gate design you can get.  
This will be a good test of not only synthesis prowess but how you handle
HDL coding styles.

P.P.S  Oh, yea, the winner or the winning team gets $1000.00!

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3196 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

-----------

Welcome to SNUG 1995

Synopsys invites you to the Fifth Annual Synopsys Users Group (SNUG)
Conference at the Red Lion Hotel in San Jose, California, on March
22-24, 1995.

What is SNUG?  SNUG is an open forum that provides Synopsys' users an
opportunity to exchange ideas, discuss problems and explore solutions.
It also gives users a chance to meet with Synopsys executives,
developers and application engineers.

The program is highly technical and developed by users with an emphasis
on customer issues.  The SNUG Technical Program Committee is
responsible for the content of all breakout sessions.  If you would
like to participate in this process, contact Jeff Flieder at the
address shown below.

Why is it important?
SNUG provides a unique opportunity to meet other Synopsys users.  The
program is designed to address a variety of design issues.  User
breakout sessions provide unique solutions to various design problems.
ASIC vendor sessions provide specific techniques for building
successful chips.  EDA tool vendor presentations explore other EDA
products which leverage Synopsys High-Level Design tools.

What's new this year?
SNUG 1995 is the site of the First Annual Design Competition.  This
competition gives you an opportunity to match your design skills
against other Synopsys users.  Winners will share their design tricks
with you.

You will also get a sneak preview of upcoming Synopsys Solutions, and a
chance to examine some third party products as well.

Feel free to pass this program on to any of your colleagues who are
familiar with Synopsys.  This year's program promises to be extremely
exciting.  Don't miss it!

Jeff Flieder
SNUG Technical Program Chair
(719)528-7718, fax (719)528-7635
fmicos!splinter!flieder@uunet.uu.net

Ken Nelsen
Synopsys Applications
(415)694-1771, fax (415)694-1864
knelsen@synopsys.com

Schedule

Wednesday, March 22
Tutorial registration                   12:00 - 2:00
Tutorial sessions                        2:00 - 5:00
Welcoming cocktail party/
Synopsys new product fair                5:00 - 7:00

Thursday, March 23
General session registration/breakfast   7:30 - 9:00
Welcome/agenda                           9:00 - 9:15
Synopsys Direction
(Aart de Geuss, President)               9:15 - 9:45
Breakout sessions                       10:00 - 11:30
  Topics include: User sessions,  Design competition

Lunch                                   11:45 - 1:00
Breakout sessions                        1:15 - 2:45
  Topics include: User sessions,  Design competition

Breakout sessions                        3:00 - 4:30
  Topics include: User sessions,  Design competition

Services Round Tables                    4:40 - 5:15
  Topics include: Surfing the Internet, Talk Back to Training
         Support Center Summit, Conversations with Consulting

Keynote Speaker (John Gage)              5:30 - 6:15
Wrap-up                                  6:15 - 6:30
Cocktail party/EDA tool vendor fair      6:30 - 8:30

Friday, March 24
Tutorial registration / breakfast        7:00 - 8:00
Tutorial sessions                        8:00 - 11:30

General Session
Thursday, March 23

User Breakout Sessions
These sessions are always the hit of the conference.  Hear Synopsys
users' experiences on specific topics.  Each user breakout session will
consist of two presentations, thirty minutes each, with another thirty
minutes for questions and answers.

Topics include:

Design Compiler Breakout
Moderater: John Cooley
Jerry McGoveran, Synthesis of a 200K Gate DSP ASIC
Steve Golson, My Favorite dc_shell Tricks

Design Reuse Breakout
Moderator: Kurt Baty
Kurt Baty, DesignWare for Fun and Profit
Jeff Freeman, Design Reuse

Design Compiler Breakout
Randy Bolling, Register Balancing : When and Where?
Ron Crevier, Rapid Prototyping Using Behavioral Compiler

Test Synthesis Breakout
Moderator: John Vogel
Rob Maffit, Test Compiler Methodology

Submicron Design Breakout
Moderator: Volker Kiefer
Stefan Rusu, Advanced Timing and Wire Models in Synopsys

Simulation and Verification Breakout
Moderator: Erik Magdanz
Brian Balthazor, General Instrument Case Study
Erik Magdanz, Logic Modeling Overview
Chris Beggy, Synopsys in a Mixed Tool-Suite Design Methodology

Semiconductor Vendor Sessions
Back by popular demand!  Feedback from last year's sessions was very
positive.  This year we will expand to two sessions.  This gives you an
opportunity to hear about the latest technologies available from the
semiconductor vendors and their recommended customer design flow using
Synopsys tools.  Participants include: Altera, Actel, IBM, LSI Logic,
VLSI and Xilinx.

EDA Tool Vendor Sessions
New this year!  These sessions have a format similar to the
semiconductor sessions.  They are an opportunity to see other EDA
vendors show how they can help you leverage your high level design
tools from Synopsys.  Participa= nts include: Compass Design
Automation, Summit Design, Inc., Intergraph, Mentor Graphics,
Chronologic Simulation, Veda Desgin Automation Ltd., Viewlogic, High
Level Design Systems, ArcSys, Inc., Speed Electronics, Vista
Technologies and Knowledge Based Silicon.

Design Competition Sessions
Coordinator: John Cooley
New this year!  These sessions provide you with an opportunity to work
with other high level designers and compete to see who can build the
best design.  Due to hardware limitations, the competition
participation will be limited.  Teams will be formed on a first come,
first serve basis.  A $1000 prize will be awarded to the winning team.
Sign up for the competition when you register.  Participants will be
notified of final team composition and details as soon as they become
available.

Services Roundtables

   Surfing the Internet
     Find out what tools are available to help you explore the
     Internet, and get a glimpse into the future of automated customer
     services.

   A Coversation with Consulting
     Talk to our consulting team about how they can help you complete
     projects on time and within budget.

   The Support Center Summit
     Meet with members of Support Center, and discuss ways for you to
     work together more effectively.

   Talk Back to Training
     We are always working to improve our training workshops. Here's
     your chance to talk to our courseware developers and hear what
     they have planned for the future.

Half-Day Tutorials
Wednesday, March 22

New for SNUG '95: Speed Optimization Symposium
This session is intended for experienced synthesis users who are
interested in a comprehensive methodology for speed based optimization
using Design Compiler.  A "Baseline" methodology for speed optimization
will be presented and then a panel of various experts from Synopsys
will discuss their favorite tricks for optimizing high performance
designs.  This session is repeated on Friday.

New for SNUG '95: Behavioral Synthesis Using VHDL
This session is intended for any synthesis user interested in
behavioral synthesis.  Hardware designers are frustrated with lengthy
IC design cycles for increasingly complex, data-intensive, algorithmic
applications. This tutorial will show you how to enter your design
specifications at the behavioral level and use Behavioral Compiler to
explore implementation alternatives and determine the optimal
architecture.  Content is the same as the tutorial on Friday, but
examples are presented in VHDL.

VHDL Synthesis Techniques and Recommendations
This tutorial will present a wide range of VHDL synthesis coding styles
and issues. Caveats based on real-world VHDL synthesis models will be
explored in full detail. Topics will be presented in the following
areas: VHDL synthesis fundamentals,  importance of VHDL coding styles,
relying on hardware design experiences,  disparities between efficient
simulation models and optimum synthesized hardware,  potential
simulation and synthesis mismatches,  and VHDL coding style differences
between targeted CMOS and FPGA technologies.

Pins-Out Verification
This tutorial was first offered at EuroSNUG in August.  "Pins-out"
verification offers a solution to the problem of ensuring ASICs are
right the first time.  As the complexity of ASICs increases, validation
of functionality and the trading off of design parameters becomes more
difficult.

First time right design depends on correct interactions between the
ASIC and surrounding subsystems. Thus, it is important to simulate the
IC in its system context; in other words, pins-out.  This tutorial
introduces the pins-out methodology and shows its benefits.

Friday, March 24

New for SNUG '95: Speed Optimization Symposium
This session is intended for experienced synthesis users who are
interested in a comprehensive methodology for speed-based optimization
using Design Compiler.  A "Baseline" methodology for speed optimization
will be presented and then a panel of various experts from Synopsys
will discuss their favorite tricks for optimizing high performance
designs.  This session is a repeat of the Wednesday session.

New for SNUG '95: Behavioral Synthesis Using Verilog
This session is intended for any synthesis user interested in
behavioral synthesis.  Hardware designers are frustrated with lengthy
IC design cycles for increasingly complex, data-intensive algorithmic
applications. This tutorial will show you how to enter your design
specifications at the behavioral level and use Behavioral Compiler to
explore implementation alternatives and determine the optimal
architecture.  Content is the same as the tutorial on Wednesday, but
examples are presented in Verilog.

New for SNUG '95: DSP Design Techniques  using COSSAP
This session reviews DSP basics and applications.  It provides a good
overview of DSP issues and particularly focuses on the COSSAP design
methodology to solve these issues.  This session is intended for the
designer who is new to using EDA tools for solving DSP applications.
It is not intended for the designer who is proficient in the use of
COSSAP tools.

Advance Registration

Please complete a separate registration form for each attendee.
Specify breakout sessions for Thursday, and your choice(s) of
tutorials.

General Session Registration
Registration includes all materials for the general and breakout
sessions.  Due to limited space, breakout session sign-up will be done
on a first-come-first-serve basis.  Both cocktail parties , breakfasts
on Thursday and Friday, and the Thursday lunch are included.

Tutorial Session Registration
Registration for each tutorial includes the session and all related
course material.  Tutorials are available only to general session
registrants.  Space is limited - register early!

General session:                        Late registration - $150.00

Tutorials (per session):                Late registration - $75.00 each

Full payment in U.S. dollars must accompany registration.  Company and
personal check, VISA, MasterCard, and American Express cards are
accepted.  All checks must be made payable to: Synopsys Users Group.

For Credit Card Registration:
* call 1-800-388-9125
* e-mail the information to designinfo@synopsys.com
* fax your completed form to SNUG at 503-690-6906

To Register By Mail:
Detach the form and mail it with your check to:
Synopsys
P.O. Box 310
Beaverton, OR 97075-9962

Cancellations/Refunds
A letter of cancellation must be received 7 days prior to the beginning
of the conference to qualify for a refund.

Travel/Housing

Hotel
Due to the heavy response, the Red Lion Hotel is full.  You can try
these alternative locations: San Jose Biltmore 408-988-8411, Santa
Clara Marriot 408-988-1500

Air Travel
Synopsys has negotiated an American Airlines discount for SNUG
attendees.  You'll receive 5% off the lowest applicable fare or 10% off
if the ticket is purchased 7 days in advance.  A Saturday night
stay-over will increase your savings.  When you or your travel agent
makes reservations be sure and give the American Airlines agent the
code STAR NBR 02 35 TA to receive the discount.

Car Rental
Hertz has been appointed the official car rental company for SNUG'95.
Special discount rates, with unlimited mileage, start from $35.99 per
day to a weekly rate of $131.99 for a sub-compact to a $43.99 per day
to a weekly rate of $181.99 for a full-size, 4 door sedan.  These rates
are guaranteed from March 15th through March 31st.  When making
reservations use the SNUG ID number, CV#14168, and Hertz will
automatically compare the SNUG guaranteed rate to other Hertz published
rates to give you the best comparable rate available.  For reservations
call Hertz at (800) 654-2240.

SNUG'95 Registration Form

Name:________________________________________________________
Title:_________________________________________________________
Company:_____________________________________________________
Mailing Address:______________________________________________
_____________________________________________________________
Phone:_____________________FAX:______________________________
e-mail Address:_______________________________________________
Credit Card Name:______________Credit Card Number:_____________
Exp. Date:__________Name Printed on Card:_______________________
Signature:____________________________________________________

____ I prefer vegetarian meals

General Registration - $100
Breakout Session Choices (Select one per session plus alternate):

1st Session: first choice #A___, alternate #A____
A1. Design Compiler
A2. Design Reuse
A3. Design Competition

2nd Session: first choice #B___, alternate #B____
B1. Synthesis
B2. Test Synthesis
B3. Semiconductor Vendor Sessions
B4. EDA Tool Vendor Sessions
B5. Design Competition

3rd Session: first choice #C___, alternate #C____
C1. Sub-micron Design
C2. Simulation and Verification
C3. Semiconductor Vendor Sessions
C4. EDA Tool Vendor Sessions
C5. Design Competition

Wednesday VHDL Based Tutorial Registration - $50
Tutorial Session Choice (Select one): #W____
W1. Speed Optimization Symposium
W2. Behavioral Synthesis Using VHDL
W3. VHDL Synthesis Techniques and Recommendations
W4. Pins-Out Verification

Friday Verilog Based Tutorial Registration - $50
Tutorial Session Choice (Select one): #F____
F1. Speed Optimization Symposium
F2. Behavioral Synthesis Using Verilog
F3. DSP Design Techniques Using COSSAP

Registration Total: $__________

All technical sessions and presentations are subject to change prior to
conference dates.

More Information:  
If you have questions or need more information on SNUG'95, please call
1-800-388-9125.



Article: 845
Subject: Re: FPGA multi-chip modules ?
From: gnuge@aol.com (Gnuge)
Date: 11 Mar 1995 20:39:45 -0500
Links: << >>  << T >>  << A >>
Check out Altera's 50,000 gate Multi-Chip Module.


Article: 846
Subject: Re: FPGA multi-chip modules ?
From: lemieux@eecg.toronto.edu (Guy Gerard Lemieux)
Date: 12 Mar 95 02:51:12 GMT
Links: << >>  << T >>  << A >>
In article <3jqfis$a4o@vanbc.wimsey.com>,
Rob Semenoff <rob@vanbc.wimsey.com> wrote:
>Are any trying to get more logic into a package for
>less money by interconnecting dies in a package
>in some programmable, or customer-specified way ? 

Altera has a device called the 8050M.  it is a multichip module
containing 4 FLEX 81188 FPGAs (1188 flip flops, 1008 4-input LUTs)
and an Aptix FPIC (FP interconnect chip).  i think they claim
50,000 gate capacity.  it costs $5k US.

i think other vendors are pursuing similar directions.
the goal is to get ultra-high-capacity devices that are
easy to partition/program.

guy


Article: 847
Subject: Re: FPGA multi-chip modules ?
From: attmes@slip.technet.sg (Koh Kim Huat)
Date: 12 Mar 1995 09:58:11 GMT
Links: << >>  << T >>  << A >>
In article <3jqfis$a4o@vanbc.wimsey.com>, rob@vanbc.wimsey.com (Rob Semenoff) says:
>
>I presume vendors are increasing FPGA density by going
>for bigger dies and smaller feature size.
>
>Are any trying to get more logic into a package for
>less money by interconnecting dies in a package
>in some programmable, or customer-specified way ? 
>
>-rob

I understand that Altera has such kind of Multi-chip module (MCM)
for its FLEX8000 series FPGA. But it doesn't seem cheap. In fact,
such MCMs are very expensive as fabrication process is not as easy 
as we think.

Futhermore, the logic utilization of MCM is not proportion to the
number of chips integrated. Actually the more chips you put in the
MCM, the lower the utilization. Since there will not be enough
routing resources among the chips, the MCM becomes unroutable as it
grows too big. Therefore, MCM is not really practical for high gate
count FPGAs.

However, if you want to get more logic into a package, it is not
necessary to go for MCM. Reduce process technology to 0.5um or less,
definitely, the number of logic gates on the same die will be more.
Not only you can get more logic, the performance (speed) will also
be increased. Also, add more metal layers for routing resources to
improve the routing so as the logic utilization. This is very
important for FPGA greater than 10K gates, otherwise, the FPGA will
become not routable.

Simon.


Article: 848
Subject: Re: FPGA multi-chip modules ?
From: pss1@hopper.unh.edu (Paul S Secinaro)
Date: 13 Mar 1995 00:09:56 GMT
Links: << >>  << T >>  << A >>
lemieux@eecg.toronto.edu (Guy Gerard Lemieux) writes:
>Altera has a device called the 8050M.  it is a multichip module
>containing 4 FLEX 81188 FPGAs (1188 flip flops, 1008 4-input LUTs)
>and an Aptix FPIC (FP interconnect chip).  i think they claim
>50,000 gate capacity.  it costs $5k US.

Is this really a multichip module?  Last time I glanced at the
brochure, it looked more like a small motherboard with four
normally-packaged '1188's and the Aptix chip soldered on, with some
pins on the bottom, probably with all the I/O pad and pin-to-pin
delays that implies (especially when passing through the Aptix).  I
was under the impression than an MCM was built in such a way that
interconnect speeds between chips were nearly as fast as intra-chip
connects (take the Intel P6 for example).

Also, I was at an Altera workshop a few months ago and the spin that
they put on this device was that it was mainly intended for fast
gate-array prototyping, not production use.

-Paul
-- 
Paul Secinaro (Paul.Secinaro@UNH.edu OR pss1@christa.unh.edu)
Synthetic Vision and Pattern Analysis Laboratory
UNH Dept. of Electrical and Computer Engineering


Article: 849
Subject: Simulation with VIEWLogic's PROSim
From: Roland Welte <100070.3321@CompuServe.COM>
Date: 13 Mar 1995 07:38:17 GMT
Links: << >>  << T >>  << A >>
I am using VIEWLogic's PROSeries as a front end tool for my
FPGA designs.

A question came up with regards to command files for silulation
with PROsim. I know that command files can also call other
command files, but is there a possibility to transfer arguments
from one command file to the other? I would like to write
'macros' which simulate micro processor write and read cycles
and then call these with the address and data values as aruments
from within a 'main' command file.

Any help and hints are greatly appreciated.

Thanks.

Roland




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