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Messages from 1100

Article: 1100
Subject: Viewlogic VHDL for Xilinx
From: Saied Benyamin <saied>
Date: 27 Apr 1995 21:37:07 GMT
Links: << >>  << T >>  << A >>
I am desparately trying to force the viewlogic VHDL synthesizer use
the CE (clock Enable) on the Xilinx CLB's with no luck.  The viewlogic
technical help people could not give me a solution either.  Does any
one know how to do this?  The synthesizer is right now working the
clock enable into the equations and wasting gates.  My code is as
follows...

nx_st <= idle	WHEN (match AND p_eom) ELSE
         met	WHEN .......


set_st_reg:PROCESS
	BEGIN
		WAIT UNTIL (PRISING(clk) or reset='1');
		IF (clkenable='1') THEN
			cur_st <= nx_st;
		ELSE
			cur_st <= cur_st;
		END IF;
	END PROCESS;

I have also tried putting clock in the sensitivity list and
use clk'event AND clk='1' and that did not work either.

I appreciate any help.....  saied@tekelec.com



Article: 1101
Subject: Call for Participaton at UK Fifth Annual Advanced PLD & FPGA Day
From: pclarke@lfields.demon.co.uk (Peter Clarke)
Date: Fri, 28 Apr 1995 13:17:11 +0000
Links: << >>  << T >>  << A >>
                     CALL for PARTICIPATION

                             at the 

              FIFTH ANNUAL ADVANCED PLD & FPGA DAY

              - - - - - - - - - - - - - - - - - - -

The Fifth Annual Advanced PLD & FPGA DAY takes place at the Sheraton Skyline 
Hotel, Heathrow, on Wednesday 10th May. It is organised by UK newspaper 
Electronics Times in association with Data I/O.

Delegates are invited to register for the event which will include two 
streams of technical presentations and a table-top 
demonstration/exhibition area.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 
                              
                            PROGRAMME 

9:30	Keynote, Ian Page, Oxford University's Computing Laboratory 

will speak on hardware compilation and reconfigurable FPGAs with reference 
to his group's CAM architecture of device  

10:00	Invited paper, David Kohlmeier, Data I/O

"Transferring high pin-count designs to manufacturing"


STREAM A
--------

10:50 	Kevin Marlow, Mentor Graphics
	"Simplifying FPGA design flow for better design"

11:20	Shubba Shukla, Exemplar Logic
	"VITAL-based design flow for Xilinx FPGAs"

12:00	Dr Hans Klein, IMP
	"Capabilities of an analogue FPGA"

12:30	Doug Amos, Altera
	"PLDs with embedded mega-function capability"

2:15	Bruce Kleinman, Quicklogic
	"Tackling algorithms with FPGAs"

2:45	Simon Fielding, Viewlogic Systems
	"Techniques for writing VHDL for efficient FPGA synthesis"

3:45	Bill Chown, Summit Design
	"Using graphical techniques with HDLs for FPGA design"

4:15	Tom Salsbury, Synopsys
	"Enhanced analysis and debugging in FPGA designs"


STREAM B
--------

10:50	Bradly Fawcett, Xilinx
	"FPGAs and reconfigurable computing"

11:20	Joel Rosenberg, Atmel
	"Implementing DSP functions using cache logic FPGAs"

12:00	Freddy Engineer, Minc
	"Implementing a general-purpose VHDL/Verilog HDL logic emulator 
	using FPGAs"

12:30	Yousef Khalilollahi, Actel
	"Designing ATM switching fabrics using Actel FPGAs"

2:15	Daniel Brasen, IST
	"Automatic ASIC prototyping with FPGAs and programmable 	
interconnects between FPGAs"

2:45	Kent Dahlgren, I-Cube
	"Bus switching with field-programmable switches

3:45	Peter Trott, AMD
	"Designing a PCI interface using AMD PLDs"

4:15	Ken Chapman, Xilinx
	"On-chip memory: the key to multiplication in an FPGA"

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 

REGISTRATION FORM

I wish to attend the Fifth Annual Advanced PLD & FPG Day on Wednesday, 
10th May, at the Sheraton Skyline Hotel, Heathrow.

Name ..........................

Position.......................

Company .......................

Address .......................

..............................

Postcode ......................

Tel: ..........................

Fax: ..........................

E-mail: .......................

Please reserve .... tickets for the Advanced PLD & FPGA Day at 95 
(plus VAT, 111.62) each

Tick .... My purchase order is attached

Tick .... I enclose a cheque payable to Morgan-Grampan plc (111.62 
including VAT) per seat.

Registration fee includes: entry to conference and exhibition areas, 
lunch and one copy of the proceedings

Please return to 
Barbara Green, 
Electronics Times, 
Morgan-Grampian plc, 
30 Calderwood Street,
London SE18 6QH

or contact on Tel: +44 181 316 3288
or Fax: +44 181 854 8980
or Fax: +44 181 855 1793  

---------------------------------------------------------------------------
Peter Clarke
Programme Co-ordinator


Article: 1102
Subject: Re: How to use XBLOX librariers in VHDL in Synopsys?
From: mike@vlsivie.tuwien.ac.at (Michael Gschwind)
Date: 28 Apr 1995 13:30:48 GMT
Links: << >>  << T >>  << A >>
In article <3novvv$2oa@paris.usc.edu> oner@paris.usc.edu () writes:
>Hi Netters,
>
>My subject says it all. I have been using Viewsynthesis to analyze
>my VHDL programs and I can use XBLOX libraries in Viewsynthesis
>by making special procedure calls. Is there a similar way to do
>this in Synopsys tools? If there is, could you explain how I can do it?
>
>
>An example of my VHDL code written for Viewsynthesis:
>
>-------------------------------------------------------------------------------
>--  Data Register & Counter
>-------------------------------------------------------------------------------
>  data_clk_en <= load_data OR inc_data;
>  xb_counter(D_IN => d_in, ASYNC_CTRL => reset, CLOCK => clk,
>             LOAD => load_data, CLK_EN => data_clk_en,
>             Q_OUT => dout, ATTR => "STYLE=BINARY");
> 

If you use the xblox design ware library, some elements (counters,
adders/subtractors, comparators) will be generated by XBLOX
automatically, for other XBLOX components I have no idea.  You could
hand-generate them and include the relevant macros with xmake (in VHDL
you would just do a COMPONENT declaration), but that is not nice...

One problem you have to solve if you use XBLOX components (via merging
macros...) other than those supported by xblox DW is *SIMULATION*...

If you get any other suggestions/find any other solutions, please let
me know...

m.


--

Michael Gschwind, Institut f. Technische Informatik, TU Wien
snail: Treitlstrasse 3-182-2 || A-1040 Wien || Austria
email: mike@vlsivie.tuwien.ac.at   PGP key available via www (or email)
www  : URL:http://www.vlsivie.tuwien.ac.at/mike/mike.html
phone: +(43)(1)58801 8156	   fax: +(43)(1)586 9697
Boycott Whaling!!! Boycott Norway!!! Boycott Norwegian Products!!!


Article: 1103
Subject: FPGA Downloading Circuit Tutorial
From: devb@elvis.vnet.net (David Van den Bout)
Date: 28 Apr 1995 08:33:45 -0500
Links: << >>  << T >>  << A >>
XESS Corp. has just released two chapters of
"FPGA Workout II".  "comm.exe" covers a FIFO design
and shows how to implement it on the EPX780 FPGA.
(This will eventually be expanded to cover a full
buffered UART.)  "autoload.exe" discusses the design
of a simple circuit to load the EPX780 FPGA from an
EPROM so you don't have to download from a PC each time.
Each chapter is a hypertext document that will execute
on a DOS machine with a VGA display.

If interested, you can retrieve these chapters via
anonymous FTP from ftp.vnet.net in directory
pub/xess/hyperdoc.  Get the ZIPPED and executable
file comm.exe and autoload.exe.

Other hypertext files which are still available:
   epxdata.exe: EPX780 datasheet
   pldasm.exe : PLDasm HDL manual
   jtag.exe   : JTAG tutorial
-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 1104
Subject: Re: Sunrise ???
From: stephen@srbailey.com (Stephen A. Bailey)
Date: 28 Apr 1995 14:57:29 GMT
Links: << >>  << T >>  << A >>
In article <D7pKL4.EuA@stortek.com>, peetj@hp7101.stortek.com says...
>
>Terry E. Koontz (tkoontz@uncc.edu) wrote:
>
>: Viewlogic recently add ViewTest to their Powerview product line.
>
>: ViewTest is based on Sunrise 2.0 software (their words)
>
>: Does anyone have an address and telephone number for Sunrise.
>
>: Terry Koontz
>: UNCC
>
>: tkoontz@uncc.edu
>
>Sunrise
>Corp Headquarters
>2730 San Tomas Exp.
>Suite 200
>Santa Clara, CA. 95051
>408-980-7600
>408-980-7630 fax
>Info_request@srtest.com

The above information is INCORRECT!  Sunrise moved to Viewlogic's
Fremont offices in early January.  An earlier post accurately
gave the new address and phone number which I reiterate here:

Sunrise Test
47211 Lakeview Blvd.
Fremont, CA 94538

Viewlogic has at least two phone numbers into these facilities,
however, all numbers go through the same receptionist, etc.  I'm
familiar with the "Vantage" numbers:

510-659-0901  (voice)
510-659-0129  (fax)
-- 
=========================================================
Stephen A. Bailey             voice: 408.377.8326
SRBailey                      fax:   408.377.1206
911-C Apricot Avenue          data:  408.377.1206
Campbell, CA 95008
http:  TBA                    email: stephen@srbailey.com
=========================================================



Article: 1105
Subject: Looking for XNF format definition
From: benedett@caliban.dsi.unimo.it (Arrigo Benedetti)
Date: 28 Apr 1995 16:59:47 GMT
Links: << >>  << T >>  << A >>
I'm looking for a detailed description of various Xilinx formats, especially XNF.
I've just received the Xilinx development system, but I've not not found any XNF
specific information in the books. Is there a separate document that has to be
ordered from Xilinx?

Thanks in advance,
-- 
Arrigo Benedetti                          e-mail: benedett@dsi.unimo.it
University of Modena graduate student          abenedetti@deis.unibo.it
address: Via S. Agata 11 41100 MODENA - ITALY
phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727
--
Arrigo Benedetti                          e-mail: benedett@dsi.unimo.it
University of Modena graduate student          abenedetti@deis.unibo.it
address: Via S. Agata 11 41100 MODENA - ITALY
phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727


Article: 1106
Subject: Re: VMEbus interface using fpgas
From: NDCX09A@prodigy.com (James Dickson)
Date: 29 Apr 1995 02:07:05 GMT
Links: << >>  << T >>  << A >>

I have been successful in implementing VME interfaces with Altera FPGAs 
and EPLDs many times.  I have found that state machine design of the 
interface is the best approach and works quite well with VHDL or Alteras 
HDL, especially for the Block Mode Transfers (DMA).

Let me know if you have any specific questions... and good luck!





Article: 1107
Subject: ASIC group ?
From: ast@actcom.co.il (Gideon Amir)
Date: Sun, 30 Apr 1995 17:03:04 GMT
Links: << >>  << T >>  << A >>
Its nice to have this very useful fpga group, but what about ASIC's?
Shouldn't we have a separate group to discuss LSI vs. Tosh etc.?
Or, does it exist and I simply cannot find it among the 2000 game and 
joke groups out there?



Article: 1108
Subject: Re: Free Hardware
From: rhperez@aol.com (RHPerez)
Date: 30 Apr 1995 15:44:51 -0400
Links: << >>  << T >>  << A >>
My understanding is that Xilinx doesn't want to divulge their info,
because they feel they got burned with ATT: first ATT second-sources
Xilinx silicon, then ATT designs its own silicon to compete with
Xilinx.  I've heard lots of people want to use ORCA over Xilinx;
in fact, buying NeoCAD may have been the only card left to play
in Xilinx' pocket, to slow down ORCA and Motorola.

The actual programming format is published by Xilinx, I believe.
(could be wrong, though).


Article: 1109
Subject: Microcontrollers
From: rhperez@aol.com (RHPerez)
Date: 30 Apr 1995 15:47:59 -0400
Links: << >>  << T >>  << A >>
How about writing the HDL code (VHDL or Verilog) that emulates
the 6502 family?  I know it's been done commercially, because it
is such a simple design.  And, there are lots of free compilers
for it.

synthesizing the code would take a synthesizer (obviously) but
I have read that there are public-domain ones available.  


Article: 1110
Subject: Re: Is anybody using FPGA's to do PCI interfaces?
From: rhperez@aol.com (RHPerez)
Date: 30 Apr 1995 15:52:47 -0400
Links: << >>  << T >>  << A >>
Both Xilinx and ORCA claim to do it; ATT has a complete App note
including the VHDL code for the job.  The tricky part in PCI design
is meeting the timing and electrical requirements.  I would expect
that both companies have slightly tweaked their latest hardware
so that if you place things *just* right, it will work.

For prototyping, you can skip the electrical requirements and just
meet timing, but that will only work for a lightly loaded PCI bus.


Article: 1111
Subject: Re: Need help about conference chip
From: david.evans.cnv666@nt.com (David Evans)
Date: 1 May 1995 00:53:01 GMT
Links: << >>  << T >>  << A >>

In article <3nj61e$bgc@mis.cpc.ku.ac.th>, fengwct@ku.ac.th (Wichai Tang) writes:
|> Hi,
|> 	I must design a digital conference chip. But I have no idea about 
|> this chip.  This chip use to mix several PCM signals together. I know that,
|> the PCM code is nonlinear. So the first step to do a conference is to 
|> convert this nonlinear PCM code into linear digital signal system and sum the
|> whole time slot that need to join a conference together. Then convert 
|> this signal back to PCM code and put it back to the specific time slot. I 
|> will use FPGA as my target to implement this design. Could anyone suggest me 
|> in the following questions ?
|> 	1. I know that PCM is nonlinear digital system so we must convert 
|> it back to linear digital signal before we can do anything on it. From 8 
|> bits of PCM code must be convert to 14 bits of linear digital signal. The 
|> easy solution is to use ROM to convert this signal, but I would like to 
|> know that is there any other way to do this job ? And dose it appropriate 
|> for targetting at FPGA ?
|> 	2. When we have many time slot want to join a conference, we must 
|> attenuate all signal before summing it up. so the question is how can I 
|> attenuate this linear digital signal ? I think this should not as easy as 
|> just divide it with number of conferece time slot. Am I correct ?
|> 	Any comment or pointer is very appreciate. Thank you for your concern.
|> 
|> Best Regards,
|> Wichai Tang

One little hint...Don't just add all the talkers together and then divide--
It will sound bad.  Add only the two loudest.  I'll leave the details as
an exercise for the student.    

Have fun.



-- 
David Evans                          email: david.evans.cnv666@nt.com
Multimedia Communications Systems    
Northern Telcom Canada Limited      


Article: 1112
Subject: AT&T ORCA data book
From: klindwor@tech12.informatik.uni-hamburg.de (Andre Klindworth)
Date: 1 May 1995 11:12:45 GMT
Links: << >>  << T >>  << A >>

Hello, everybody

I would like to know where I may obtain a databook on AT&Ts ORCA FPGAs? 
There should be a sales representative in Germany, I suppose, 
but I couldn't make out who it is.

Thanks for your help.
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
                                    Phone: +49 40 54715-501,  Fax: -397
-----------------------------------------------------------------------
-- 
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
                                    Phone: +49 40 54715-501,  Fax: -397


Article: 1113
Subject: Re: Viewlogic VHDL for Xilinx
From: dlanza@wizard.ess.harris.com (David Lanza)
Date: 1 May 1995 12:48:20 GMT
Links: << >>  << T >>  << A >>
In <3np2q3$ak4@getty.tekelec.com> Saied Benyamin <saied> writes:

>I am desparately trying to force the viewlogic VHDL synthesizer use
>the CE (clock Enable) on the Xilinx CLB's with no luck.  The viewlogic
>technical help people could not give me a solution either.  Does any
>one know how to do this?  The synthesizer is right now working the
>clock enable into the equations and wasting gates.  My code is as
>follows...

>nx_st <= idle	WHEN (match AND p_eom) ELSE
>         met	WHEN .......


>set_st_reg:PROCESS
>	BEGIN
>		WAIT UNTIL (PRISING(clk) or reset='1');
>		IF (clkenable='1') THEN
>			cur_st <= nx_st;
>		ELSE
>			cur_st <= cur_st;
>		END IF;
>	END PROCESS;

Try it like this...

	BEGIN
		WAIT UNTIL (PRISING(clk) or reset='1');
		IF (reset = '1') THEN
			cur_st <= cur_st;
		ELSIF (clkenable='1') THEN
			cur_st <= nx_st;
			cur_st <= cur_st;
		END IF;
	END PROCESS;

... Should give you the clock enable connection.  Viewlogic's Synth tool
can be picky about VHDL style.  The tech support poeple should have been able
to help, though.

Dave Lanza

--

  David Lanza
  dlanza@harris.com


Article: 1114
Subject: Re: Viewlogic VHDL for Xilinx
From: djg@tas.com (David Gesswein)
Date: 1 May 1995 09:18:53 -0400
Links: << >>  << T >>  << A >>
In article <3np2q3$ak4@getty.tekelec.com> you write:
>I am desparately trying to force the viewlogic VHDL synthesizer use
>the CE (clock Enable) on the Xilinx CLB's with no luck.  The viewlogic
>technical help people could not give me a solution either.

Start with this exact syntax and see if it works.  Since their tool does
pattern matching to use these special features statements which are 
equivalent in VHDL may not generate the same logic.  If this works then
try modifying it to do what you want.

>From their training class information (not personally tested):

Clock enable with async reset:

...
PROCESS
BEGIN
WAIT UNTIL(prising(clk) OR reset = '1');
   IF reset = '1' THEN
      dout <= '1'
   ELSE
      IF clock_enable = '1' THEN
         dout <= din;
      ENDIF
   ENDIF
END PROCESS;
...

Sync reset
...
PROCESS
BEGIN
WAIT UNTIL(prising(clk));
   IF clock_enable = '1' THEN
      -- if reset = '1' then dout goes low, style restriction below
      dout <= din AND NOT(reset);
   ENDIF
END PROCESS;
...

David Gesswein
djg@tas.com


Article: 1115
Subject: Web/FTP site for FPGA based research
From: obiliset@ascinc.com (Sashi Obilisetty)
Date: Mon, 1 May 1995 14:12:14 GMT
Links: << >>  << T >>  << A >>
Hi,

I was wondering if there is a Web site I can look into for
papers in FPGA based research. 

(I could'nt find a FAQ for this group at rtfm.mit.edu. Is there
a FAQ at all? If so, where?) 

thanks,

 

--
*	Sashi Obilisetty							*
*	Alternative System Concepts, Inc.					*
*	PO Box 128 Windham NH 03087						*
*	tel (603) 437-2234 fax (603) 437-ASC2	URL http://www.ascinc.com	*


Article: 1116
Subject: Any experiences with Altera MAX9000 ?
From: klindwor@tech12.informatik.uni-hamburg.de (Andre Klindworth)
Date: 1 May 1995 14:27:35 GMT
Links: << >>  << T >>  << A >>

Hi, there.

I am thinking about using the new Altera MAX9000 device(s) for an
industrial design project. As usual, the schedule is very tight
and running into problems with the MAX+plusII development tool
or device availability would be a catastrophe. 
So I would like to hear from anybody who has allready carried
out a MAX9000 design if he/she would advice me to take the risk.

Thanks in advance.
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
Germany                             Phone: +49 40 54715-501,  Fax: -397
-----------------------------------------------------------------------


-- 
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
                                    Phone: +49 40 54715-501,  Fax: -397


Article: 1117
Subject: Crosspoint FPGA Users?
From: Mike Reynolds <reynolds@ozemail.com.au>
Date: 1 May 1995 22:57:46 GMT
Links: << >>  << T >>  << A >>
Hi,

Is anyone out there using Crosspoint CP20K FPGAs?

Any comments on their strengths/weaknesses wrt other 
FPGAs, best design tools/methodology, support etc?

If anyone is developing Crosspoint FPGAs using PC 
front-end tools - which tools?

Cheers,
Mike.


Article: 1118
Subject: Lattice EPLDs
From: chibane@alpha.fdu.edu (Cherif Chibane)
Date: Tue, 2 May 1995 00:39:04 GMT
Links: << >>  << T >>  << A >>
Hello There,

I have been using XILINX's FPGA as well EPLD for quite sometimes now. 
Lately I have been using EPLDs and I am guetting tired of XILINX and I 
would like to change to another vendor. My willingness to 
chnage was prompted by the high cost of the erasable XILINX' EPLDs. In 
addition, they still use 1980 technology (UV) which requires them 20 min to 
erase.

I have been looking to LATTICE EPLD. They seem to be good. From my 
research, they seem to have extra resources for pin routing. Since my 
designs are never frozen, this feature should help me keep the pins the same 
even if I change the design.

So can anybody, who has used Lattice, share with me his thrills of victories 
and agony of defeats. Having suffered many griefs with XILINX, I 
can take anything.


Thank you,
Cherif

----
<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>
<>    Cherif Chibane                                              <>
<>    ALGAM Laboratories	  	         		  <>
<>    Tel: 201-262-9797		                                  <>
<>    Fax: 201-262-9810		                                  <>
<>    Email: Chibane@sun490.fdu.edu             	          <>
<>----------------------------------------------------------------<>
<> Fairleigh Dickinson University                                 <>
<> Electrical Engineering Dept.                                   <>
<><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><><>


 


Article: 1119
Subject: Re: Looking for XNF format definition
From: Not configured (change c:/user/winvn/winvn.ini) (Not configured (change c:/user/winvn/winvn.ini))
Date: 2 May 1995 08:48:28 GMT
Links: << >>  << T >>  << A >>
In article <BENEDETT.95Apr28185947@caliban.dsi.unimo.it>, benedett@caliban.dsi.unimo.it (Arrigo Benedetti) says:

I am looking for this XNF format too. I thought it was public and
asked for it at Xilinx. They told me that it is not public and if you
want it, you have to sign some papers... I still don't have it.
If you get it, please tell me...

P.S. www.xilinx.com is their address, but you knew this, of course.

Peter Sels


Article: 1120
Subject: Re: ASIC group ?
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 2 May 1995 13:23:17 GMT
Links: << >>  << T >>  << A >>
Try comp.lsi, although last time I participated it seemed to be mostly 
full custom discussion as opposed to ASICs.  Post there and ask.

---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1121
Subject: Re: Web/FTP site for FPGA based research
From: jma@descartes.super.org (Jeffrey M. Arnold)
Date: Tue, 2 May 1995 15:55:44 GMT
Links: << >>  << T >>  << A >>
In article <D7wKsF.IMv@mv.mv.com> obiliset@ascinc.com (Sashi Obilisetty) writes:
   I was wondering if there is a Web site I can look into for
   papers in FPGA based research. 

We (IDA/SRC) maintain a web site with pointers to various research
groups and other links of interest.  You can get to it via:

	http://www.super.org:8000/FPGA/caf.html

There you will also find an archive of this news group, a calendar of
related events, and a detailed bibliography (courtesy of BYU).  Other
links are always welcome!

   (I could'nt find a FAQ for this group at rtfm.mit.edu. Is there
   a FAQ at all? If so, where?) 

There is not a FAQ, but volunteers would be welcomed!

-jeff

------
Jeffrey Arnold
IDA Supercomputing Research Center
17100 Science Dr.
Bowie, MD 20715
email: jma@super.org



Article: 1122
Subject: Re: AT&T ORCA data book
From: dh@fncrd7.fnal.gov (don husby)
Date: 2 May 1995 16:13:53 GMT
Links: << >>  << T >>  << A >>
klindwor@tech12.informatik.uni-hamburg.de (Andre Klindworth) writes:
> I would like to know where I may obtain a databook on AT&Ts ORCA FPGAs? 
> There should be a sales representative in Germany, I suppose, 
> but I couldn't make out who it is.

Phone numbers found on the back of an AT&T ORCA data sheet:

USA:         800-327-9374  /  610-712-4331
Europe:      (44) 734 324 299   fax: (44) 734 328 148
Germany:     (49) 89 95086 0
Japan:       (81) 3-5421-1600   fax: (81) 3-5421-1700
Pacific/Asia (65) 778-8833      fax: (65) 777-7495


Article: 1123
Subject: Re: Is anybody using FPGA's to do PCI interfaces?
From: timsc@bmw.hwcae.az.Honeywell.COM (Tim Schneider)
Date: 2 May 95 12:07:23
Links: << >>  << T >>  << A >>

we're using Altera here to do a PCI bus interface.
I believe there is an app note out that explains the details.

from the altera express service it looks like its document #'s

5830 and 5831

1-800-5-ALTERA

 -tim



Article: 1124
Subject: Re: Viewlogic VHDL for Xilinx
From: jay@bisbee.viewlogic.com (Jay Southard)
Date: 2 May 1995 15:10:55 -0700
Links: << >>  << T >>  << A >>

With just a minor change to your VHDL, your code will fit the ViewSyn clock
enable templates, assuming:
	1) Your technology is "xc4000", or "xc3000"
	2) You have ViewSynth 2.4 or later
	3) You really do have a reset clause
You just have to remove the redundant else clause with clock enable.

Try:
	set_st_reg:PROCESS
 	BEGIN
 		WAIT UNTIL (PRISING(clk) or reset='1');
		if (reset = '1') then
			cur_st <= idle; -- Or whatever
		else
	 		IF (clkenable='1') THEN
	 			cur_st <= nx_st;
	 		END IF;
		end if;
 	END PROCESS;


In article <3np2q3$ak4@getty.tekelec.com>, Saied Benyamin <saied> writes:
|> I am desparately trying to force the viewlogic VHDL synthesizer use
|> the CE (clock Enable) on the Xilinx CLB's with no luck.  The viewlogic
|> technical help people could not give me a solution either.  Does any
|> one know how to do this?  The synthesizer is right now working the
|> clock enable into the equations and wasting gates.  My code is as
|> follows...
|> 
|> nx_st <= idle	WHEN (match AND p_eom) ELSE
|>          met	WHEN .......
|> 
|> 
|> set_st_reg:PROCESS
|> 	BEGIN
|> 		WAIT UNTIL (PRISING(clk) or reset='1');
|> 		IF (clkenable='1') THEN
|> 			cur_st <= nx_st;
|> 		ELSE
|> 			cur_st <= cur_st;
|> 		END IF;
|> 	END PROCESS;
|> 
|> I have also tried putting clock in the sensitivity list and
|> use clk'event AND clk='1' and that did not work either.
|> 
|> I appreciate any help.....  saied@tekelec.com
|> 
-- 
_______________________________________________________________________
   -- Jay                       If you don't know where you're going,
                                any road will take you there.




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