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Messages from 1350

Article: 1350
Subject: Re: FPGAs for PCI Interfaces
From: tw38966@vub.ac.be (SH.RYU KIM HOFMANS)
Date: 5 Jun 1995 15:00:10 GMT
Links: << >>  << T >>  << A >>
Roman & Tracey Iwanczuk (iwanczuk@scruznet.com) wrote:

: Xilinx has several PCI compatible FPGAs and EPLDs.  Rather than
: list all of the info here and make this a too blatant advert 
: (since I am a Xilinx employee) I'll just say that you can find 
: out more about them by e-mailing pci@xilinx.com

: regards
: roman iwanczuk

well, I e-mailed pci@xilinx.com a few weeks ago, but I didn't get any
response :(
(But maybe it's because they're getting too much mails)

By the way, does ALTERA also have a pci-mail adress ? (e.g pci@altera.com ?)



Article: 1351
Subject: Participate in Biennale Symposium via the Internet
From: davis@unive.it (Enrica Abbate)
Date: 5 Jun 1995 16:26:40 GMT
Links: << >>  << T >>  << A >>
art and technology. creativity and its methods

INTERSECTING SYMPOSIA
June 8, 1995
_______________________________________________________


THE STRUCTURE

As part of the Centennial Celebration of the Biennale Visual Arts
Exhibition, the TEATRO FONDAMENTA NUOVE in Venice, Italy, is organizing
simultaneous, interacting symposia entitled "art and technology. creativity
and its methods".  One symposium, consisting primarily of panelists present
in Venice at the invitation of the Biennale, will take place live at the
TEATRO FONDAMENTA NUOVE.  The other symposium will be held simultaneously
among members of the Internet community from around the world via internet
conferencing.  The contents of the internet conference will be projected on
the screen in Venice where it will be used to stimulate panelist
discussion.  In turn, delegates will be responsible for representing to the
internet conference the central elements of the dialogue taking place in
Venice, making meaningful connections between the two forums.  In this
manner, two independent, yet intersecting and mutually reinforcing symposia
will be taking place, thus blurring barriers of physical distance.


THE FOCUS

The symposia will focus on the influence of advanced technology-- such as
virtual reality, interactive television, and other high-tech forms-- on the
creative process, and will represent the perspective of artists, critics,
philosophers, and scientific and business leaders from technological
fields.  In particular, participants in the symposia will be asked to draw
on personal experience to stimulate discussion on the following questions:

Is technological development bringing us to self-destruction or to a new
Renaissance?
Are we experiencing the last phase of Western civilization, or the dawn of
the digital era?
Does the computer revolution favor alienation or communication?
Does computer simulated closeness increase actual solitude?
How do advanced technologies affect the relationship between artist, art,
and viewer?


PARTICIPATE VIA INTERNET

As a member of the Internet community, you are invited to participate in
the internet conference.  On June 8, 1995, the Internet conference will be
open and projected onto the screen at the TEATRO FONDAMENTA NUOVE from
15:00 to 19:00 Central European Time (9:00AM-1:00PM Eastern Standard Time).
The conference is accessible with a Telnet program.  To Connect TELNET to:


chat.fondamenta.interbusiness.it

You will then see the heading "Welcome to the Chat Room" and you will be
asked to Enter your name.  Please type in your first and last name as well
as the city and country where you are physically located at the time of the
connection.   The following format is recommended for readability:

JaneDoe--ParisFrance

Note the lack of spaces as well as the capital letters separating the first
name from the last name, and city from country.

Given sufficient space, anyone will be allowed to enter the conference at
the time of the symposium.  If you are planning to participate, however, it
would be greatly appreciated if you could please send an e-mail in advance
indicating your intention to participate and a brief description of your
background and interests.  The address to use for this purpose is:

davis@unive.it

If you are unable to participate at the time of the symposium or you do not
have a telnet capacity, you can also e-mail questions or comments to the
above address in advance.  These contributions will be incorporated into
the proceedings and the nature of responses and reactions on the part of
the panelists or conference participants will be returned via e-mail at a
later date.  (See the WWW page listed below for panelist biographies.)



THE SYMPOSIUM WORLD WIDE WEB PAGE

To find out more information on the symposium, connect to its World Wide
Web page:

http://www.fondamenta.interbusiness.it

The page (which should be completed by June 5) contains the schedule of
events and installations, detailed conceptual outline of the symposia,
biographies of panelists and presenting artists, and sponsor listings. In
addition, on June 8 by 14:30 Central European Time (8:30 Eastern Standard
Time), the web page will contain a summary of the panelist discussion that
took place during the morning's session.  Finally, after the completion of
the symposium, the transcript of both the live proceedings and the internet
conference can be obtained at this web address.

If you want to obtain any of the above information via e-mail, please send
requests to davis@unive.it

THE PROCEEDING OF THE SYMPOSIA WILL BE VIDEOTAPED AND SELECTIVELY BROADCAST
BY VIDEOMUSIC.


Article: 1352
Subject: Re: FPGAs for PCI Interfaces
From: husby@fnal.gov (Don Husby)
Date: 5 Jun 1995 20:36:09 GMT
Links: << >>  << T >>  << A >>
tak@core.rose.hp.com wrote:
> what kind of effect will routing have on "wide fanout" input signals?
> for example, both TRDY# and IRDY# can have significant loading, especially
> when sustaining zero wait state burst transfers is required.

Using (neocad) epic, I tested a simple route:

  PAD-longline-PFU(s).

For a single PFU, the route was 2.6ns
With two PFU at opposite ends of the chip, the route was 2.9ns
Presumably, each additional PFU will add ~0.3 ns.

Remember, each PFU has 4 function outputs, so, 2 PFUs can
be a fanout of 8.

The routing time of 2.9ns puts the total setup time at 3.0ns
plus or minus ~ 1ns.

Faster routing is acheivable by routing via shorter lines.



Article: 1353
Subject: HELP AT6000
From: "John E. Chausse" <chauss1@server.uwindsor.ca>
Date: Mon, 5 Jun 1995 21:14:50 GMT
Links: << >>  << T >>  << A >>


I am in electrical engineering and am taking a course on FPGA's.  I have 
no backround in FPGA's.  If anyone has any technical documentaion on the 
AT6000 or knows where i could get it, i would appreciate any response.

Thanx.
 
****************************************************************************
*                                    *                                     *
*         John E. Chausse            *                                     *
*  Email: chauss1@server.uwindsor.ca *                                     *
*       University of Windsor        *                                     *
*       Windsor Ontario Canada       *                                     *
*                                    *                                     *
****************************************************************************


Article: 1354
Subject: AT17C128 and AT17C65 E2PROM PARTS
From: Martin Mason <martin@atmel.com>
Date: Tue, 6 Jun 1995 01:28:38 GMT
Links: << >>  << T >>  << A >>
Atmel Corp. - has a family of pin compatable 17CXXX serial E-squared 
devices for anyone interested in second sourcing OTP EPROM or E2PROM 
17CXXX series FPGA configuration memories.

The parts can also emulate 24CXXX 2 wire interface industry standard 
serial devices for storing system set-up info. in the same part as the 
FPGA configuration data.  The Atmel parts use the 'spare' pin  
(Vpp on OTP EPROM Serials) to select betwen 17CXXX ans 24CXXX modes.  The 
parts are 5V in-system (re)programmable, have programmable reset/~oe polarity
and are available NOW upto 128K bit densities.

If you would like more information on these parts please send an e-mail 
with your snail mail address to fpga@atmel.com for a data sheet, or e-mail 
martin@atmel.com if you have any technical questions.

Please put datasheet in the subject for datasheet requests.


Martin Mason.

-------------------------------------------------------------------------
|	"Always Net Surfing...........Never working"			|
-------------------------------------------------------------------------
|	Martin Mason		| Applications Architect - FPGAs	|
|	Atmel Corp.		| (Work)	 martin@atmel.com	|
|	2125 O'Nel Drive 	| (Work2)	   fpga@atmel.com	|
|	San Jose		| 					|
|	CA 95131		| (Work): + 408 436 4178		|
-------------------------------------------------------------------------	


Article: 1355
Subject: LowCost CPLD/FPGA tools ???
From: kugel@mp-sun6.informatik.uni-mannheim.de (Andreas Kugel)
Date: 6 Jun 1995 07:55:02 GMT
Links: << >>  << T >>  << A >>
Are there any lowcost tools (approx < $500) for CPLD/FPGA
designs available ? Of special interest are Lattice isp chips
(complete ispLSI1000,2000 familiy) and XIlinx XC3000 series

Design entry may be text-based, logic simulation capabilties
must be present, timing simulation would be nice.


---


--------------------------------------------------------
Andreas Kugel                
Chair of Computer Science V       Phone:(49)621-292-5755
University of Mannheim            Fax:(49)621-292-5756
A5
D-68131 Mannheim
Germany
e-mail:kugel@mp-sun1.informatik.uni-mannheim.de
--------------------------------------------------------



Article: 1356
Subject: Re: HELP AT6000
From: ludwig@inf.ethz.ch (Stefan Ludwig)
Date: 6 Jun 1995 10:06:18 +0200
Links: << >>  << T >>  << A >>
In article <Pine.SGI.3.91.950605171258.20844A-100000@server.uwindsor.ca>,
John E. Chausse <chauss1@server.uwindsor.ca> wrote:
>
>
>I am in electrical engineering and am taking a course on FPGA's.  I have 
>no backround in FPGA's.  If anyone has any technical documentaion on the 
>AT6000 or knows where i could get it, i would appreciate any response.
>
>Thanx.

You can take a look at the hard- and software we have implemented for a
2nd year EE course for computer science students using the AT6000 family
of FPGAs.

ftp://ftp.inf.ethz.ch/doc/tech-reports/1993/198.abstract
ftp://ftp.inf.ethz.ch/doc/tech-reports/1993/198.ps.Z
ftp://ftp.inf.ethz.ch/doc/tech-reports/1994/215.abstract
ftp://ftp.inf.ethz.ch/doc/tech-reports/1994/215.ps.Z

The software described in those reports is available for free. Contact
me for more information.

Good luck!

	Stefan H-M Ludwig                        ludwig@inf.ethz.ch

	Institute for Computer Systems
	Swiss Federal Institute of Technology (ETH)
	CH-8092 Zurich, Switzerland
	
	Phone: 41-1-632 7301
	Fax  : 41-1-632 1075


Article: 1357
Subject: Re: LowCost CPLD/FPGA tools ???
From: trev@ss11.wg.icl.co.uk (Trevor Hall)
Date: Tue, 6 Jun 1995 11:23:42 GMT
Links: << >>  << T >>  << A >>

kugel@mp-sun6.informatik.uni-mannheim.de (Andreas Kugel)

>Are there any lowcost tools (approx < $500) for CPLD/FPGA
>designs available ? Of special interest are Lattice isp chips
>(complete ispLSI1000,2000 familiy) and XIlinx XC3000 series
>
>Design entry may be text-based, logic simulation capabilties
>must be present, timing simulation would be nice.

If you were writing from a .co site -> Xilinx, no chance.
                                       Lattice, perhaps, we paid 600 pounds sterling
                                       for ispLSI1k,2k and 3k fitters.

As you are a .uni, Xilinx or Lattice may be nice to you.

Have you thought about AMD MACH devices ? PALASM is cheap (don't know how much, we get
it free, even though we don't use it).


If you do not have contact names you may wish to try :-
steve.scard@xilinx.com     (Steve Scard, XILINX)
mark@lscuk.demon.co.uk    (Mark Ogden Lattice Logic)

And for good measure ;-
simonr@altera.com          (Simon Redmile Altera)
paul.ridgway@amd.com       (Paul Ridgway AMD)

These are UK apps. engineers but I am sure they can point you in the right direction.

Cheers,
T.H.









Article: 1358
Subject: FPGA conversion options
From: ljoo@enternet.com.au (Laszlo Joo)
Date: Tue, 6 Jun 1995 04:37:55
Links: << >>  << T >>  << A >>
I have to convert two XILINX FPGA designs to ASIC. Both of them is a XC3030 
design and needed in the quantity of 5K this year.
I wonder someone who has previous experience in this field could give me 
information regarding to manufacturers, time schedules and quotes.

Regards,

Laszlo Joo

Commtek Pty Ltd



Article: 1359
Subject: Asynch. Periph. Prog. of FPGAs
From: bachman@clipper.robadome.com (Thomas Bachman)
Date: 6 Jun 1995 17:43:05 GMT
Links: << >>  << T >>  << A >>
HELP!!!!!

We're trying to program a 4013 FPGA using asynchronous peripheral mode, 
and cannot get the programming sequence to work!

Our algorithm for programming goes something like this:

	hold PROGRAM pin low
	wait
	release PROGRAM pin 

Wait:
	If INIT not high
	  Goto Wait

	While all bytes have not been written to the FPGA
	  {
	    write a byte

Still_Busy:
	    if the RDY/BSY pin is still low
	      goto Still_Busy

	    if the INIT pin is low
	      goto Failed

	  }

We're able to write the header bytes (FF, 20, etc.), and can write all
of the bytes of the frame to the FPGA without errors.  However, when we
write the last byte of the frame (actually, because the frame size of 
this FPGA is 266 bits -- i.e. not evenly divisible by 8 -- the last byte
contains the last 2 bits of the first frame and the first 6 bits of the
next frame), the INIT pin goes low, indicating a framing error.  We've
tried using both the checksum mode (i.e. the last 4 bits of the frame
are checksum bits) and the non-checksum mode (i.e. the last 4 bits of
the frame are 0110) but neither one works.

Please send email to bachman@clipper.robadome.com if you have ideas 
for help!  Thanks in advance!


	-- Thomas Bachman	

-- 
!!!!! This .sig space for sale !!!!! 




Article: 1360
Subject: HELP AT6000
From: Scott Evans <scott@atmel.com>
Date: Tue, 6 Jun 1995 18:04:25 GMT
Links: << >>  << T >>  << A >>
You can get technical information about the Atmel FPGA by sending an 
e-mail to:
	fpga@atmel.com

or calling the FPGA Hotline at

	408 436 4119

Please let us know what information you are requesting, data book, app. 
notes, etc.  Also let us know your snail mail address.

Sorry we don't have WWW or ftp access for this information.

 ____________________________________________________________________
|\___________________________________________________________________\
| |Scott Evans                      |Atmel Corporation                |
| |scott@atmel.com                  |2125 O'Nel Drive                 |
| |(408)436-4117 (408)436-4200 (fax)|San Jose, CA  95131              |
 \|___________________________________________________________________|



Article: 1361
Subject: http://www.xilinx.com/Tech_support.html
From: Bill Mengelson <mengel@IntNet.net>
Date: 6 Jun 1995 19:58:50 GMT
Links: << >>  << T >>  << A >>
Are there PAL/PLA devices such as 22V10 in SMT packaging with a seated 
height of less than o.1" ? Thanks Bill



Article: 1362
Subject: Re: http://www.xilinx.com/Tech_support.html
From: roger@coelacanth.com (Roger Williams)
Date: 07 Jun 1995 02:05:28 GMT
Links: << >>  << T >>  << A >>
   Are there PAL/PLA devices such as 22V10 in SMT packaging with a seated 
   height of less than o.1" ?

22V10s are available in SO-24s from Philips and other companies.  The
SO-24, though, has a max height of 0.104", so I assume that you're
looking for a PQFP-28 (at 0.05").   I haven't seen 22V10s in this
package (presumably because they're hard to socket to program), but
devices like Lattice's small ISP devices may work for you.

-- 
Roger Williams
Coelacanth Engineering  |  Numeric stability is probably not all
Middleborough, Mass     |  that important when you're guessing...


Article: 1363
Subject: Xblox oo !!!!
From: xilinx@xaloc.upc.es
Date: Wed, 7 Jun 1995 09:18:46 GMT
Links: << >>  << T >>  << A >>
Hello,

	     The last night I turned on my PC and began with a new
	     design. (I use XILINX 5.1 Software) This morning (14 hours
	     later) XBLOX hadn't finished. Is this possible ?

	     No error messages were shown on the screen.


					 Thanks,

						 Fernando Alonso. 
						 TSC Dpt. UPC.
						 Barcelone.
						 SPAIN


Article: 1364
Subject: Some benchmark circuits in XNF
From: hismail@cs.bilkent.edu.tr (Ismail Haritaoglu)
Date: Wed, 7 Jun 1995 14:11:41 GMT
Links: << >>  << T >>  << A >>

I used some benchmark circuits from Partitioning93 Benchmarks.
Also I would like to use some othre well-known benchmark circuits. 
(9symml, toolg, apex7, exp2, vda, alu2, alu4,term1,
count, bw,f51m,duke2,vg2 ). However, I couldn't  find them in XNF 
in MCNC directory.

if  anyone knows  where I can get  these circuits in XNF, please send
an e-mail to hismail@cs.bilkent.edu.tr.

Thanks in advance 


Ismail Haritaoglu

Bilkent University
Computer Eng. Dept. 
Ankara, Turkey


Article: 1365
Subject: Fitter Quality
From: alexk@dspis.co.il (Alex Koegel)
Date: 7 Jun 1995 15:12:46 GMT
Links: << >>  << T >>  << A >>

We have used Altera Flex8000 very sucessfully. A FLEX81500 based design at 94% utilization was fitted, & re-fitted many times again

We have used MaxPlusII Rev 5.11 & 5.2.

One just cann't generalize and say  "the fitter was appaling". Yes, there are some architectural limitations with the Flex8000 (not

Alex Koegel
DSP Communications



Article: 1366
Subject: Re: Xblox oo !!!!
From: tom@dilleng.wa.com (Tom Dillon)
Date: Wed, 7 Jun 1995 16:46:58 GMT
Links: << >>  << T >>  << A >>
On 7 June at 11:21, you wrote:
> Hello,
>
> 	     The last night I turned on my PC and began with a new
> 	     design. (I use XILINX 5.1 Software) This morning (14 hours
> 	     later) XBLOX hadn't finished. Is this possible ?
>
> 	     No error messages were shown on the screen.
>
No, I have never seen XLBOX take more than 30 minutes.

Make sure you run XNFPREP on the design first. It will show you many errors that 
should be corrected prior to running XBLOX.

Other than that, you may need to have Xilinx look at the design.

Good luck,


--
Tom Dillon
DILLON ENGINEERING
e-mail: tom@dilleng.wa.com



Article: 1367
Subject: About your Xblox problem
From: xilinx@xaloc.upc.es
Date: Wed, 7 Jun 1995 17:21:04 GMT
Links: << >>  << T >>  << A >>


Fernando,

Regarding what you described, the way Xblox seems to wait for more
than 14 hours, I believe there's something happening in background, 
such like asking you a question and waiting for your answer. But as it
is in background, of course you CANNOT see the software is prompting 
you.
If possible, I would recommend to run your programs in 'verbose
mode'. Then you'll see the questions, which usually do not have to 
happen. But sometimes, very often seeing the question brings you on the
right way to correct the problem, as questions may only occur if
there's a problem.

This is what I've found in Xdocs, one of my more favourite e-mail based 
tool.
Send an e-mail To: xdocs@xilinx.com and simply write HELP in the subject
line. By an automatic reply, you'll get the way and the commandes for using
it. This is an access to a big database of articles concerning known bugs
and workarounds, advises, technical tips and so on. The INDEX keyword
in the Subject line will make you get a listing of references numbers 
associated to the title of articles and subjects.
The SEND commande followed by the reference(s) number(s) will make you 
get the complete article / application note and so on, but once again the
HELP command will explain you clearfully how to use this powerfull tool.

Hope all this helps...

Regards, 
             /|
            / |
           | /|
           |/ |
           |  |
           | O
vince...  O
 ____________________________________________________________
|                                                            |
|  __   Vincent Tabourier          Application Engineer      |
| / /\/ Xilinx S.a.r.l                                       |
| \ \   Espace Jouy Technology                               |
| / /   21 rue A. Calmette, Bat C  Phone: (33)-1-34 63 01 00 |
| \_\/\ 78 353 Jouy En Josas Cedex Fax:   (33)-1-34 63 01 09 |
|       FRANCE                                               |
|  -->  E-Mail: vincent.tabourier@xilinx.com                 |
|                                                            |
| Jingle: J.S.Bach, " The Well Tempered Keyboard "           |
|                     Book I ( Prelude )                     | 
|____________________________________________________________|




Article: 1368
Subject: Re: Fitter Quality
From: ventti@fincitec.fi (Veli-Matti Karppinen)
Date: Thu, 8 Jun 1995 05:30:37 GMT
Links: << >>  << T >>  << A >>
In article <3r4fle$2jf@dns.netvision.net.il> alexk@dspis.co.il (Alex Koegel) writes:

>We have used Altera Flex8000 very sucessfully. A FLEX81500 based design at 
94% utilization was fitted, & re-fitted many times again

>We have used MaxPlusII Rev 5.11 & 5.2.

>One just cann't generalize and say  "the fitter was appaling". Yes, there are some architectural limitations with the Flex8000 (not

>Alex Koegel
>DSP Communications

I agree completely with this. We have had both good and bad experiences with 
the compiler, but it certainly has been improving during the 5+ years we've
used it.

 I think the key point is to find out which compiler/fitter settings should be 
used in each case and that can take a while.

Regards,

Veli-Matti Karppinen
Fincitec Oy

---------------------------------------------------------------
Veli-Matti Karppinen                Fincitec Oy
P.B. 11, FIN-94601 Kemi             Tel. +358 698 221 490
Finland                             Fax. +358 698 221 561
        
" Once you have flown, you will walk your eyes turned towards
  the sky, for there you've been and there you long to return "
                                     -- da Vinci


Article: 1369
Subject: Reconfigurable hardware architectures for image processing
From: benedett@caliban.dsi.unimo.it (Arrigo Benedetti)
Date: 08 Jun 1995 07:52:07 GMT
Links: << >>  << T >>  << A >>
I'm looking for references to recent works on reconfigurable hardware systems
targeted to image processing and visualization.

I will post a summary if there is enough interest.

Regards,
-Arrigo Benedetti
--
Arrigo Benedetti                          e-mail: benedett@dsi.unimo.it
University of Modena graduate student          abenedetti@deis.unibo.it
address: Via S. Agata 11 41100 MODENA - ITALY
phone: (home) + 39 59 224929 (office) +39 59 216688 (fax) +39 59 220727


Article: 1370
Subject: (no subject)
From: "Charles F. Shelor" <cfshelor@acm.org>
Date: 8 Jun 1995 12:29:15 GMT
Links: << >>  << T >>  << A >>


Charles F. Shelor                      cfshelor@acm.org
SHELOR ENGINEERING                     VHDL Training, Consulting, Models
3308 Hollow Creek Rd                   (817) 467-9367
Arlington,  TX  76017-5346




Article: 1371
Subject: Virtually FREE VHDL/ASIC seminars
From: "Charles F. Shelor" <cfshelor@acm.org>
Date: 8 Jun 1995 12:33:20 GMT
Links: << >>  << T >>  << A >>
Two seminars to be held in Hunstville, AL.
Wednesday, June 21
Huntsville Marriott
8:30 - 12:00:  Introduction to VHDL by Example
1:00 -  4:30:  Object Based Top Down ASIC/FPGA Development

$25 each seminar

Introduction to VHDL by Example

This introductory seminar addresses the use of VHDL in the
development of ASICs, FPGAs, and CPLDs.  A short history of
the language provides the background for why it is the best
language, from a life cycle and full system perspective, for
the development of hardware devices.  The features of VHDL are
explained by the use of a =D2real world=D3 example.  The course is
intended to provide program managers, engineering managers, and
practicing engineers sufficient information to determine if VHDL
would be appropriate for their application.  It will show some
of the power of VHDL and will remove the mystique surrounding
VHDL.  It will not create VHDL programmers nor will it be able
to discuss every minute detail of the language.  The use of VHDL
in system modeling, design verification, and logic synthesis will
be emphasized.  The benefits and pitfalls of synthesis will be
discussed.  Sources for more information on VHDL will be provided.


Object Based Top Down ASIC/FPGA Development

This tutorial describes a top down development methodology where
the partitioning process is guided by object based considerations.
The methodology emphasizes designing for reuse as the greatest
engineering productivity enhancement in current technology.  The
methodology also stresses routing considerations since routing is
very important to sub-micron ASICs and to many FPGAs.  VHDL
beginners can benefit from the tutorial by seeing a non-trivial
VHDL implementation.  VHDL experts can benefit from the tutorial
by learning the OBTD methodology from requirements through
implementation.  The tutorial uses the VIUF 1994 Design Contest
problem, an airport baggage handling system, as the design example.


Outline:

Introduction to Object Terminology
Application of Object Based Techniques to ASIC and FPGA Development
Problem Requirements
Top Level Design Considerations
Intermediate Design Constraints
Example Implementation
Planning and Scheduling with OBTD methodology


About the author:

Charles Shelor is an independent VHDL methodology consultant and
trainer.  He has twenty years experience in the design of high
performance embedded systems.  He was the winner in the user
category of the VIUF 1994 Design  Contest.  He has presented over
a dozen papers at various conferences, a design feature in
Electronic Design News, and is the author of the VHDL Designer
column in the =D2VHDL Times=D3.  He has a BSEE, MSEE, and is pursuing
a PhD in Computer Engineering.  He has a patent in multiple
processor computer architectures.

Contact SHELOR ENGINEERING for more information



Charles F. Shelor                      cfshelor@acm.org
SHELOR ENGINEERING                     VHDL Training, Consulting, Models
3308 Hollow Creek Rd                   (817) 467-9367
Arlington,  TX  76017-5346


ps:  Sorry about the previous blank post!  I dropped my pad on the
keyboard sending the post before I finished  :-}





Article: 1372
Subject: ** Last Year: "DAC & The Grateful Dead" **
From: jcooley@world.std.com (John Cooley)
Date: Thu, 8 Jun 1995 16:52:43 GMT
Links: << >>  << T >>  << A >>

  For the past three years I've found it futile to publish a technically
  oriented ESNUG the week before DAC because of all the pre-DAC hysteria.
  (People just aren't in the mindset to solve bugs, etc. at this time.)
  Technical ESNUG will resume the week after DAC.

                                       - John Cooley
                                         part-time EDA Consumer Activist
                                         full-time ASIC/FPGA consultant

  P.S.  Enclosed is last year's (1994) review DAC in San Diego.  (If you bump
        into me at this year's DAC in San Francisco, tell me what you think
        is hot and what's not -- I'll need it for this year's review!)   :^)

  --------------------

      !!!     "It's not a BUG,                       jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                             (508) 429-4357
    (  >  )
     \ - /  
     _] [_           The Second Annual ESNUG/DAC Awards

                        "DAC '94 & The Grateful Dead"


      The parallels between going to a Grateful Dead concert and attending
 the Design Automation Convention (DAC) are so many it's uncanny.  They're
 both typically four or five day long festivals with a main floor show
 and lots of more interesting things happening off the floor.  At night,
 you can partake in all sorts of fun in the parking lot if you're at the
 Dead show; or at an EDA vendor sponsored dinner party if you're at DAC.
 Sign that unwritten, unverbalised social contract to not tell anyone what
 you're about to see & do and they'll let you into that tent/bus/van for
 an extra special "fun" time only hinted at on the Dead concert floor.  Sign
 that lawyer written, carefully worded Non-Disclosure Agreement contract from
 the EDA vendor and they'll let you into their demo suit to see their extra
 special upcoming software only hinted at on the DAC showroom floor.

     And just like there are sets of songs that get the Dead audience all
 rocking and sets that put everyone to sleep; there are DAC panels that
 have everyone talking and others that people walk out on.  Just like
 there are light weight occasional recreationial drug users next to hard
 core addicted junkies in the Dead concert; there are occasional PC-based
 schematic capture FPGA designers next to hard core UNIX Workstation pumping
 Verilog/Synthesis/ATPG 200 Mhz 350K GaAs ASIC designers at DAC.  And both
 worlds employ "pushers" (salesmen) to provide the controlled substances (or
 controlled software) to the users for a hefty cut of the money.  
  
     Both subcultures wear special attire (tie-dye or suits), trade bootleg
 material (concert tapes or EDA benchmarks) and converse in special words
 that have meaning only to members of that particular subculture ( "electric
 cool aid", "ghanga", "tripping" vs. "ESDA", "PLI" & "regressions.")  Just
 as there are unique personalities known in the Dead world ( Timothy Leary,
 Bill Graham, Jack Kerouac, Tom Wolfe, Ken Kesey, Hunter S. Thompson)
 there are also unique personalities known in the DAC world ( Aart De Geus,
 Ron Collett, Bill Fuchs, Richard Goering, John Sanguinetti, Joe Costello...)

     But enough cultural anthropology!  On with the awards!


 WORST OVERALL SURPRIZE AT DAC: An awful lot of attendees at DAC were caught
 off guard when they closed the DAC exhibit hall a day early.  Yes, it was
 technically buried in the schedule -- but who reads schedules until the day
 of the event?  (As a consequence, on Thursday, I found myself in a 2 1/2 hour
 lunch/interrogation about industry trends with Ron Collett, a market
 researcher.)  Also, DACnet had technical problems the first day that made it
 very difficult to login and use.  This meant many people were hard to contact
 because they blew off retrying the then healthy DACnet on subsequent days.  
 (A good DACnet note: they added telnet & ftp capabilty this year - great!)

 MOST ANXIOUS EDA VENDOR(S): Virtually all of the non-Cadence & non-ViewLogic
 affiliated Verilog vendors were acting like debutants at their first ball.
 Because Synopsys tipped its hand in the Verilog/VHDL wars in its failed bid
 for Chronologics and because Mentor is openly stating it needs a Verilog
 solution, the remaining independent Verilog vendors are terrified at the
 prospect of not being asked to dance.

 WHAT EDA USERS THOUGH WAS HOT: Because sub-micron & low power design seems
 to be of interest to quite a few people these days, one of the hottest
 talked about companies at DAC this year was EPIC Design Technology.  Their
 PathMill is an advanced static analysis tool, PowerMill is the leading
 dynamic power analysis tool and TimeMill is the a SPICE-like accelerated
 analysis tool -- all for submicron design.

 The second hot topic was Chrysalis' Design INSIGHT and Design VERIFYer, two
 of the very first commercial tools to take the formal verification approach 
 to checking if one's design has flaws.  Because they take a mathematical
 approach, they claim that formal verification beats dynamic simulations by
 orders of magnitude in overnight regressions.

 The third topic people were discussing was Synopsys' Behavioral Compiler,
 a tool can take algorithmically written Verilog or VHDL and convert it
 to gates.  Unlike regular synthesis that pretty much translates from the
 original structure in the source HDL; Behavioral Compiler literally juggles
 things like registers, MUXes and Adders around to best fit the designer's
 scheduling goals.

 The Redwood/Comdisco demo and the recent purchase of Redwood by Cadence were
 on people's minds.  (The big question is how many original Redwood R & D
 engineers going to stick around?)  Cadence's Verilog & VHDL co-simulation
 products were also hot.  (Mix & match Verilog/VHDL source/libraries at will!)
 ArcSys is targeting Cadence in the place & route business and Integrated
 Silicon Systems (ISS) also seems to be attacking Cadence on the mask 
 verification front (Dracula.)  Everyone goes after the big company.


 BEST DAC PANEL: Tie between the EE Times/DEC/ViewLogic sponsored DAC
 Forum and the DAC sponsored Four CEO panel.  What people liked about
 the DAC Forum was the fact that they could "vote" electronically for
 what a particular panelist was saying at the moment -- making it very
 audence interactive in a grand way.  (No vendors, only users were given
 the hand held voting machines.)  What they liked about the Four CEO Panel
 was a rare access to how these industry bigwigs saw the world.

 WORST DAC PANEL: The EE Times Benchmarking Summit.  Lots of people on
 the panel and in the audence came prepared to discuss issues like the Actel
 Proposal, how PREP works, benchmarking clauses in NDA contracts and
 benchmarkers who blackmail EDA vendors.  Instead, the moderator (a non-EDA
 knowlegable person) had everyone spend 2 hours partaking in a UN conflict
 resolution exersize where we had to argue the opposing side's point of view.
 (Someone would say something and the moderator would then have everyone
 determine "What should I write in the 'ASSUMPTION' column and in the 'WANTS'
 column on that statement?")  Every time an interesting exchange started,
 the moderator would actively step in and stop it.  As a result, all we could
 do was lightly touch some of the politics of benchmarking.


 BEST AFTER HOURS PARTY: Quickturn Emulation's Tuesday Night Bash.  They had
 a sit down dinner after which the Temptations gave a performance.  Although
 it had appeared that ViewLogic was going to win this with their ferry ride
 to a sit down dinner on Harbor Island and comedian (everyone was smoozing
 like crazy to get tickets before this event), the comedian turned out to
 be a flop in many a person's opinion.  (He was more caustic than funny;
 meaning that attendees were stuck doing nervous laughter to be polite.)
 It was rumored that LSI gave 100 of its "most favored customers" a sailing
 regatta in San Diego bay with six people per sailboat which sounded fun but
 was too limited a party to qualify for an award.

 BEST USE OF DAC TERRAIN FOR A PARTY: Synopsys' Wild Night At The Zoo.  The
 moment one got off the bus you had a table full of beers with helpers saying
 "Take two!  The tour's 45 minutes!"  As they shooed you onto the double
 decker open air tour bus to go around the zoo.  (Harvey Jones even commented
 how excited I was -- he was two seats behind me -- when we saw the sheep
 exhibits.)  Stumbling off the bus, we got more beer and great pre-dinner
 munchies in a party with six different animals we could touch & pet.  Then
 we had a classy swordfish or chicken dinner in an open air Gilligan's Island
 setting.  Afterwards, all 300 of us were given Irish coffee as we walked to
 the firedrummer's performance.  (In contrast, Collett reports that Cadence
 also had a dinner at the San Diego Zoo for about 65 people with no tour and
 three petting animals brought in after dinner.  Mentor did something of
 similar ilk & size at the San Diego Aquarium.)

 BEST RARE DAC FREEBIE: Summit Design's Denim Jackets.  They were well made
 with a small tasteful "Summit" patch on the left shoulder.  Total number
 given away: 175  (120 went to their Pacific Rim distributor, 25 on the 
 showroom floor and 30 for smoozing American gringos.)

 BEST COMMON DAC FREEBIE: The Official DAC Gym Bag.  It's sturdy, useful and
 has a tasteful royal purple, teal & black color scheme.  (One user openly
 wondered if IBM was "in" on the bag's color scheme because all the IBM
 shirts matched it *exactly*.)  Runner Up: a tie between the ViewLogic Soccer
 Ball and the EPIC Design Technology sports radio.  (ViewLogic conscientiously
 chooses a high quality freebie that's a pain to carry back on the plane so
 everyone can see you carrying it in the airport.  They did it last year with
 the baseball bat and this year with the soccer ball.  I can't award them
 Best Freebie when their message is "We're awkward to work with!")  The EPIC
 Design Technology sports radio's great (batteries included!) but *nowhere* 
 near the quality of a Sony.

 MOST UNEXPECTED DAC FREEBIE: Quad Design's Hammers.  (Racal-Redac and Analogy
 gave out tape measures, too!  Are their marketing managers a little confused
 about hardware design industry?)  Runner Up: Aptyx's Coconuts.  Huh?


 MOST CONTENT FREE VENDOR PRESENTATION: Synopsys' Talk On Sub-micron Design.
 I'm told it was 40 minutes where only two things were said: design's is
 headed towards the sub-micron level and there's going to be more transistors
 on chips in the future.  A close second was Cadence's re-engineering talk
 where they spent 20 minutes vaguely discussing customer successes and that
 "Cadence was here to help with your re-engineering needs."

 BIGGEST VENDOR LIE: Quite a few people told me about going through the
 ViewLogic Soccer Ball Quest they had to sit through a "VHDL is better than
 Verilog" talk by a ViewLogic salesman.  The salesman confidently said that
 "VITAL is just around the corner!  VHDL handles concurrent processes better!"
 This surprized the experienced simulation users because they've always
 described Verilog as "just like C but with wires, registers and constructs
 to handle concurrent processes" plus it took five years to get fully debugged
 Verilog libraries from ASIC vendors -- why should VITAL be different?  Ready
 for a discussion on these topics, they asked the salesman to explain his
 reasoning.  The salesman replied: "Well...   That's what I've been told..."

 WHAT DO YOU MEAN:"WHAT'S NEW?":  When people in the Mentor booth were asked
 by a long time customer: "What do you have new this year?"  After thinking
 a bit they found they couldn't answer with anything other than a simple
 design manager tool.

 MOST PERSONALLY GRATIFYING DAC PANEL: The HDL Summit.  Ron Collett moderated
 six panelists ranging from Verilog bigots to people using both to VHDL bigots.
 As usual, Collett tried to conclude the panel with his usual spin that
 VHDL was where everyone was going, etc.  Just to yank his chain, I took great
 joy in pointing out how, years ago, how a researcher at Dataquest had made
 a now embarrassing prediction that VHDL users would outnumber Verilog in
 early '92 -- which later turned out to be greatly exaggerated.  That
 Dataquest researcher was Ron Collett.

 See you next year at DAC in San Francisco!

                                               - John Cooley
                                                 the ESNUG guy

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3046 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1373
Subject: Pricing Info anyone?
From: venkat@news-local.cs.columbia.edu (Venkata N. Peri)
Date: 8 Jun 1995 17:44:02 GMT
Links: << >>  << T >>  << A >>
Does anyone have pricing info. for Xilinx and other FPGAs. My application
requires quantities in lots of ones...


Venkat

-- 
--------------------------------------------
Venkata N. Peri
Addr:  1222, 16th Street, Fort Lee, NJ 07024
Tel:   (201)-886-8537
Email: venkat@cs.columbia.edu, 
       vnp1@columbia.edu
       v.peri@ieee.org
--------------------------------------------


Article: 1374
Subject: Low cost ISA board
From: sc@vcc.com (Steve Casselman)
Date: Fri, 9 Jun 1995 03:40:24 GMT
Links: << >>  << T >>  << A >>
We are designing a low cost ISA board for reconfigurable
computing/prototype development and would like to have  
everyones thoughts on the subject like:

Cost, functionality, programmablity, prototype area,
mezzanine busses, external connectors, development software,
driver software and type of projects you might want to do
with such a card.

This will help us design a product more in tune with what
you all might need.

Steve Casselman 
Virtual Computer




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