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Messages from 1375

Article: 1375
Subject: Need access to Actel ALS tool
From: klindwor@tech12.informatik.uni-hamburg.de (Andre Klindworth)
Date: 9 Jun 1995 12:39:14 GMT
Links: << >>  << T >>  << A >>

I would like to map a couple of circuits onto Actel ACT-3 FPGAs
using the vendor's ALS tool. Since we currently have no access
to the ALS tool, I would greatly appreciate if a frequent
ALS user is willing to help me.
The circuits to be mapped are quite simple
(less than 1000 gates and a few registers) and a logic level
VHDL description exists. Synthesis and mapping thus probably won't
give any problems. If necessary, I can provide other (textual) 
design descriptions like EDIF or Verilog. 
Besides getting to know the amount of LMs needed for design
implementation, I am especially interested in getting the exact
delays INCLUDING actual routing delays. Thus any tools
which provide logic synthesis only (like SIS) 
won't be any help.
Anybody out there who can help? 
Thanks in advance.
-- 
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
                                    Phone: +49 40 54715-501,  Fax: -397


Article: 1376
Subject: 256k Serial Configuration PROM for Xilinx???
From: cjwhite@minimax.wustl.edu (Christopher J. White)
Date: 9 Jun 1995 15:48:11 GMT
Links: << >>  << T >>  << A >>

I've heard rumors that there is a single 256k part that can replace
the XC17128 + XC1765 combonitation for programming XC4010.  Anyone
else hear this?  Any details?

cj white

-- 
/**************************************************************************/
/* Life plan:                                                             */
/*   Christopher J. White                                                 */
/*   cjwhite@rgit.wustl.edu                                               */
/*   Washington University in St. Louis                                   */
/**************************************************************************/
#include <Gods_help.h>



Article: 1377
Subject: Forbidden DAC Panels, Free Lunch, Chrono & Exemplar
From: jcooley@world.std.com (John Cooley)
Date: Fri, 9 Jun 1995 17:56:34 GMT
Links: << >>  << T >>  << A >>

Here's some last minute pre-DAC notes & hot EDA gossip:

 - As a continuation of a we'll-keep-you-independent stock swap gone bad saga,
   the ex-Chronologic staff put out a press release *directly* naming 4 key
   R&D types, 2 key customer support dudes, 3 key marketing/sales people,
   their only HR person and their ex-CEO, John Sanguinetti in the formation
   of a Verilog/VCS based consulting group.  This means is that Chrono has
   lost roughly 50% of its core people -- what this translates to in true
   percentage brain drain is anybody's guess.


 - Mentor Graphics just bought the FPGA & small ASIC synthesis company
   Exemplar Logic with a $25 million stock swap.  (I guess the Exemplar guys
   haven't been following Chrono too closely....)   Exemplar's to remain
   an autonomous division within Mentor with Ewald Detjens, Exemplar's
   current CEO, to become chief scientist for synthesis at Mentor Graphics.
   Bob Garnder, the current president of Exemplar, will remain with the
   Exemplar subsidiary as chief operating officer.  The plan is that Mentor
   will keep on selling its Unix-based FGPA Station product, while Exemplar
   continues with its Galileo products on both PCs and UNIX.


 - The User's Society for Design Automation (USE/DA) is having a Birds of a
   Feather meeting Wednesday, in the SF Marriot (across the street from the
   Moscone Center) from 6:00 to 7:30 PM in the Golden Gate Ballroom.  There
   will be a change in officers and an open discussion on what issues, as
   users, we want to pursue.  Come to be heard, lend a hand in a project or
   just to be nosey!


 - "Integrated System Design" and EDN tried to sponsor a USE/DA oriented panel
   discussion on EDA Business Practices w/ issues such as revenue sharing for
   reduced tool pricing, alternative software licensing, etc.  (Steve Schulz,
   as a USE/DA board member, spearheaded a user survey on these issues and
   wanted to present the findings & open it to discussion with a panel of
   users and CEO's from the big EDA companies.)  The EDA bigwigs agreed, but
   I'm told that the DAC Organizing Committee nixed the idea in a big way
   for fear of stealing the thunder from Ron Collett's panel (where he has
   the CEO's talking in his panel the next day.)  Special rules have been
   put on the "forbidden" USE/DA panel such as there can be no signs directing
   people to the it and it's not listed in any program schedule.  Instead of 
   inviting any USE/DA people who have been working on these issues, I'm
   told that Collett has, at the last minute, put two completely unknown
   users (one from multi-billion dollar IBM and another from multi-billion
   dollar Siemens) to represent users views on his panel.

   If you want to have a free lunch plus see DAC's "Forbidden Panel on EDA
   Business Practices -- Where the Users Wanted To Talk With The CEO's.",
   drop by on Monday, June 12, from 12:30 to 1:30 pm, in room 102 of the
   Moscone Convention Center.  To secure a free lunch, ya gotta get a ticket
   by e-mailing "jonah@asic.com" or by phone at 415 903 0145 or fax at 415
   903 0151.  You can also contact EDAC at 408 287 8371.  Tickets will also
   be available at the EDN booth (1319) and Integrated System Design booth
   (418) as well as Room 102 before the panel begins -- but it's first come,
   first serve!  Reserve them NOW!


 - If you want to get involved in next year's Synopsys User's Group (SNUG)
   meeting, the SNUG Technical Committee will be meeting at 4:00 to 6:30 on
   Tuesday in the SF Marriot in the room "Sierra 5H."

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3443 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1378
Subject: Re: Pricing Info anyone?
From: husby@fnal.gov (Don Husby)
Date: 9 Jun 1995 20:01:56 GMT
Links: << >>  << T >>  << A >>
venkat@news-local.cs.columbia.edu wrote:
>
>Does anyone have pricing info. for Xilinx and other FPGAs. My application
>requires quantities in lots of ones...

This is kind of annoying isn't it?  It's hard to get even ballpark prices 
without calling a sales person and having to extract each price one at a 
time.  The AT&T guy said that they couldn't give me a price list, but he 
could come by and show it to me.

Call your local sales offices.  Prices seem to be very flexible lately.
I recently got a price from Xilinx that was nearly double the price of a 
comparable ORCA part.  When I told this to the sales guy, he came back later 
with prices that were lower by about 25%.

For ballpark on AT&T ORCA parts, you can use the figure of about $1.00
per PFU for medium-sized parts (2C12), cheaper for smaller parts.  One ORCA 
PFU is equal to ~1.5-2.5 Xilinx 4000 CLBs.

Prices seem to be dropping by about 15-20% per year, and about 15-20% for 
large quantities.




Article: 1379
Subject: Re: 256k Serial Configuration PROM for Xilinx???
From: gt5876b@prism.gatech.edu (Richard John Farmer)
Date: 9 Jun 1995 21:46:32 -0400
Links: << >>  << T >>  << A >>
cjwhite@minimax.wustl.edu (Christopher J. White) writes:

>I've heard rumors that there is a single 256k part that can replace
>the XC17128 + XC1765 combonitation for programming XC4010.  Anyone
>else hear this?  Any details?
 Yeah it's called the xc17256 as one might guess. I don't know if it has 
been released yet though. I built a programmer that can handle the entire
line. Now all I have to do is get a good doc on the file format so a can
bit bang it out the parallel port. BTW once I'm finished I'm going to release
it onto the net. It's not quite as simple as the pic programmer David Tate
whipped up, but mine meets all voltage and current specs to the letter.
 
----------------------------------------------------------------------------
Rick Farmer           gt5876b@prism.gatech.edu  `85 CB700SC  AMA# 482666
3510 Buford Hwy K-6   85k miles and 10 years of merciless abuse and it still 
Atlanta, Ga. 30329    lives, but then again a spare engine (or two) helps.
-- 
----------------------------------------------------------------------------
Rick Farmer           gt5876b@prism.gatech.edu  `85 CB700SC  AMA# 482666
3510 Buford Hwy K-6   85k miles and 10 years of merciless abuse and it still 
Atlanta, Ga. 30329    lives, but then again a spare engine (or two) helps.


Article: 1380
Subject: Re: 256k Serial Configuration PROM for Xilinx???
From: fliptron@netcom.com (Philip Freidin)
Date: Sat, 10 Jun 1995 08:04:53 GMT
Links: << >>  << T >>  << A >>
In article <3r9qfr$mch@ecl.wustl.edu> cjwhite@minimax.wustl.edu (Christopher J. White) writes:
>
>I've heard rumors that there is a single 256k part that can replace
>the XC17128 + XC1765 combonitation for programming XC4010.  Anyone
>else hear this?  Any details?
>
>cj white
>
>-- 
>/**************************************************************************/
>/* Life plan:                                                             */
>/*   Christopher J. White                                                 */
>/*   cjwhite@rgit.wustl.edu                                               */
>/*   Washington University in St. Louis                                   */
>/**************************************************************************/
>#include <Gods_help.h>
>

Acording to my 1994 data book, the largest part they make is the XC17128.

Acording to my October 3, 1994 Price list, there is an XC17256.

Call your local Xilinx office to find out which one is right :-)

Philip Freidin.



Article: 1381
Subject: Re: Low cost ISA board
From: pdgray@undergrad.math.uwaterloo.ca (Peter D. Gray)
Date: Sat, 10 Jun 1995 23:15:52 GMT
Links: << >>  << T >>  << A >>
In article <1995Jun9.034024.4769@super.org>,
Steve Casselman <sc@vcc.com> wrote:
>We are designing a low cost ISA board for reconfigurable
>computing/prototype development and would like to have  
>everyones thoughts on the subject like:
>
>Cost, functionality, programmablity, prototype area,
>mezzanine busses, external connectors, development software,
>driver software and type of projects you might want to do
>with such a card.
>
>This will help us design a product more in tune with what
>you all might need.

Step one, please don't use the ISA bus. What is the point of having
processing power at the end of tiny straw? Nowadays, PCI seems to be
the bus of choice. It is common and fast enough for many useful
applications. You needn't support the max throughput or all
hardware/software platforms (ie. you could provide software libraries
only for PC's and not explicitly support workstations and Unix).

Personally, I would like to be able to vary the amount of memory on the
card. For many applications, very little distributed memory is required
where other applications can use as much as they can get. Often it is
possible to trade memory (space) for computational complexity (time).
Perhaps standard SIMM memory could be used (the user would have control
over access time as well as the size).

For prototype area, I'd say omit it. Those things are always too small
anyway: just put a nice wide connector for expansion on it.

As for software, I don't want any. I can write my own code... But to
make it easy for me, you should give some thought to the memory map of
the device.  Every register bit in every FPGA should be visible, along
with every byte of memory on the board. I like memory mapped devices
because they are easy to support under Unix (just mmap them into your
address space). Also, you can write demo programs that are "more"
portable if the device is memory mapped since accessing memory in `C'
is standardized, but accessing I/O space is different for every
complier/operating system combination. Naturally, you've got to have
single-stepping and variable clock rates.

Just my opinions.

PG
pdgray@math.uwaterloo.ca


Article: 1382
Subject: Re: Xblox oo !!!!
From: "Bond, James" <bond@rahul.net>
Date: 10 Jun 1995 23:58:59 GMT
Links: << >>  << T >>  << A >>
xilinx@xaloc.upc.es wrote:
>
> Hello,
> 
> 	     The last night I turned on my PC and began with a new
> 	     design. (I use XILINX 5.1 Software) This morning (14 hours
> 	     later) XBLOX hadn't finished. Is this possible ?
> 
> 	     No error messages were shown on the screen.
> 
> 
> 					 Thanks,
> 
> 						 Fernando Alonso. 
> 						 TSC Dpt. UPC.
> 						 Barcelone.
> 						 SPAIN

This is quite unlikely. Usually some hard Place and Route jobs
are notorious for its long run times even upto 10 or 12 hours ,but
XBLOX ? There could be a lot of factors behind this. 

Is your PC on a network ?
What module you use in XBLOX ?
You meant XBLOX hadn't finished and not PPR ?
What is the speed of your PC ?

-JB


Article: 1383
Subject: Re: LowCost CPLD/FPGA tools ???
From: bsmith@wci.com
Date: 11 Jun 1995 05:16:43 GMT
Links: << >>  << T >>  << A >>
Trevor Hall (trev@ss11.wg.icl.co.uk) wrote:

: kugel@mp-sun6.informatik.uni-mannheim.de (Andreas Kugel)

: >Are there any lowcost tools (approx < $500) for CPLD/FPGA
: >designs available ? Of special interest are Lattice isp chips
: >(complete ispLSI1000,2000 familiy) and XIlinx XC3000 series
: >
: >Design entry may be text-based, logic simulation capabilties
: >must be present, timing simulation would be nice.

I recently bought a 'epXboard' from XESS (800.549.XESS, devb@vnet.net)
for about $150.  It has an Intel nlx780_84 on a circuit board with
a 7-segment LED for output and a PC printer interface for programming
and input.  

This kit is the lab course for a college digital circuits
class and has a very step-by-step tutorial on FPGA.  It includes a
FPGA design, compiler, and simulator (called PLDSHELL) which is
distributed by Intel.  The text is called "FPGA Workout" and is 230
pages long (but easy to read).

I learned alot from the kit and recommend it without reservation.

-- 
Bob Smith
Wireless Connect, Inc
2177 Augusta Place,  Santa Clara, CA  95051-1714
Voice: (408) 296-1550    FAX: (408) 296-1547


Article: 1384
Subject: "Free" - E-Z Computer Assembly Guide
From: QuikShot Computer Products <quikshot@iadfw.net>
Date: 11 Jun 1995 15:28:41 GMT
Links: << >>  << T >>  << A >>


-- 
Need to upgrade your computer or build your own from scratch?  
Download a copy of the E-Z Computer Assembly Guide from 
QuikShot Computer Products On-line, it's free. 
The E-Z Computer Assembly Guide was written by John Millsap the 
founder of QuikShot Computer Products On-line.  John spent many 
years repairing and configuring computers prior to starting 
QuikShot. The E-Z Computer Assembly Guide is very straight 
forward and simple to follow. The guide is in a zip file named 
quikshot.zip. Unzip the guide and print it out.  The unzipped 
file will be - quikshot.doc. 
As a bonus QuikShot offers free tech support to all PC owners 
via their E-mail tech support address - quikshot@iadfw.net.  
Due to overwhelming demand it may take a little while to get 
the free help but it is offered. 
The home page address for QuikShot Computer Products On-line is 
- http://www.tab.com/jmc/quikshot .

Best of luck




Article: 1385
Subject: Re: Need access to Actel ALS tool
From: coronill@ucssun1.sdsu.edu (Rich)
Date: 12 Jun 1995 08:58:10 GMT
Links: << >>  << T >>  << A >>
Andre Klindworth (klindwor@tech12.informatik.uni-hamburg.de) wrote:
: Besides getting to know the amount of LMs needed for design
: implementation, I am especially interested in getting the exact
: delays INCLUDING actual routing delays. Thus any tools
: which provide logic synthesis only (like SIS) 
: won't be any help.

Actually, you can get the exact delay from within the
ALS tool itself. Go under 'Timer' and have your ALS
manual ready to set up the types of delay you want to
see. This includes logic module and routing delays.
In the last version I used you could not specify
external delays, however.

Hope this helps a little,
Rich
coronill@rohan.sdsu.edu



Article: 1386
Subject: Re: Low cost ISA board
From: walton@emc.com (John Walton)
Date: 12 Jun 1995 12:40:21 GMT
Links: << >>  << T >>  << A >>
>We are designing a low cost ISA board for reconfigurable
>computing/prototype development and would like to have  
>everyones thoughts on the subject like:

>Cost, functionality, programmablity, prototype area,
>mezzanine busses, external connectors, development software,
>driver software and type of projects you might want to do
>with such a card.

If you're going to use Xilinx as the "Reconfigurable" part,
check out the package compatibility application note. Some
package/die combinations have the same pinout, others may
differ by only a few pins. The 84 pin PLCC is a good choice.

John Walton





 


Article: 1387
Subject: Re: Pricing Info anyone?
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 12 Jun 1995 12:51:53 GMT
Links: << >>  << T >>  << A >>
In article 23e@lol.cs.columbia.edu, venkat@news-local.cs.columbia.edu (Venkata N. Peri) writes:
>Does anyone have pricing info. for Xilinx and other FPGAs. My application
>requires quantities in lots of ones...
          ^^^^^^^^^^^^^^^^^^^^^^^^^^^

For small quantities, just use mail order.  Look in the archive for old 
discussion, phone #s, etc.

http://www.super.org:8000/FPGA/caf.html 
COMP.ARCH.FPGA Archive



---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1388
Subject: Re: 80x51 in FPGA anyone ?
From: F Tooned <ftooned@delphi.com>
Date: Tue, 13 Jun 95 06:21:25 -0500
Links: << >>  << T >>  << A >>
<granville@decus.org.nz> writes:
 
>I saw a 6502 example, but that is rather dated, and are very interested to know
 
Hi Jim,
 
 
I was just wondering if the 6502 example you saw was done in an Altera
FPGA??  Any references to the article you are referring to would be
appreciated.
 
Mike


Article: 1389
Subject: Re: 80x51 in FPGA anyone ?
From: Jonathan AH Hogg <jonathan@dcs.gla.ac.uk>
Date: Tue, 13 Jun 1995 11:32:55 GMT
Links: << >>  << T >>  << A >>
On Tue, 13 Jun 1995, F Tooned wrote:

> I was just wondering if the 6502 example you saw was done in an Altera
> FPGA??  Any references to the article you are referring to would be
> appreciated.

it was done on an xc4010 i believe, it's a Model Technology app note.

:-jonathan

-- 
Jonathan AH Hogg, Computing Science, The University, Glasgow G12 8QQ, Scotland.
jonathan@dcs.gla.ac.uk http://www.dcs.gla.ac.uk/~jonathan (+44)141 3398855x2069



Article: 1390
Subject: Low cost FPGA system
From: Ivan Jeukens <ivan@icmsc.sc.usp.br>
Date: 13 Jun 1995 13:27:03 GMT
Links: << >>  << T >>  << A >>
I need a low cost FPGA development system(under US$2000). The devices
	must be PCI compliant. Actually, I'm trying to develop a PCI interface
for a network adapter.

						Ivan



Article: 1391
Subject: HELP on programming XC3090A
From: esteves@di.uminho.pt (Antonio Esteves)
Date: 13 Jun 1995 15:50:53 GMT
Links: << >>  << T >>  << A >>

Hullo again,
---------------------------------------------------------------------------
(This is an article I send some days ago to this group)

We have some problems to program FPGA XC3090A in PERIPHERAL MODE and
using XACT 4.3.

The schematic used during configuration is the following:

    i)  /CS1=GND, CS2=Vcc, /CS0 is activated on each byte we send to the FPGA;
    ii) /WR (from uP) is connected to /WS (FPGA) and is activated on each 
       byte we send to the FPGA;
    iii) /INIT (with 4.7K pullup) - is not used (but we wait a while before
	programming);
    iv) RDY/notBUSY is read by uP, via bit 0 of Data Bus, using a Tri-state
	buffer;
    v) DONE/notPROGRAM (with 4.7K pullup) is activated by the uP via an Open
	collector buffer.

- The writing cycle seems to obey the timings for the peripheral mode.

-The uP sends each byte of the configuration file to the FPGA and
 inspects the LcaReady signal until it becomes HIGH.

- At the end of the configuration file, the FPGA should deactivate the
  DONE/notPROGRAM signal, which stays at LOW level.

- The conditions used in XACT to generate the file ".BIT" for a simple
  system, were:
	TLL inputs, Pullup resistor in DONE/notPROGRAM, no Readback,
	XtalOsc disabled, DONE/notPROGRAM and /RESET signals activated
	1 cycle after the end of the configuration. We didn't use Tie
	of unused logic, and the logic outside the FPGA is TTL.

----------------------------------------------------------------------------

After some info from this news group and Xilinx WWW pages, I found that
some problems can arise from noise in several signals and
the missing of pull-up resistors. We put the pull-up resistors on
Done/notProgram  and /INIT.
The FPGA seems to accept the bytes of configuration (LcaReady = -|____|-),
but after sending all the bytes the Done/notProgram signal stays at LOW
and the I/O pins not active.
The file I was using lately was obtained brom the RAWBIT file, using
only the bits between the preamble and postamble.

SOME QUESTIONS:

* Q: How to generate a right configuration to send to the FPGA
  (since I saw several ideas) ?

* Q: Do I need to generate PROM file? In this case, is it possible
  someone to send me one of the files refered in Xilinx www page
  (STRIPHEX or MAKESRV)?

* Q: Is it necessary to TIE the design used for test ?

* Q: The "1992 Data Book" from Xilinx is out of date for XC3090A ?

------------------------------------------------------------------------

Xilinx suggested us that we could have a problem of bit alignment.
But we have more problems than the alignment of bits.

We are monitoring the /INIT signal, while loading a configuration
to the FPGA, and before the end of the file /INIT changes to LOW.

Q: Does this mean error on the configuration file ?

The signals CCLK, /INIT, /WS, LcaReady, /RESET seem to behave correctly
during each byte writing cycle.

In relation to DOUT we have some doubts. To ilustrate, next it is explained
what happen when sending two bytes of header (B0=LSBit, B7=MSBit):

BYTE N:
     ___   _   _        _   ______________   
CCLK    |_| |_| |_ .. _| |_|

     ------- 
DOUT         B0  B1 ..  B5  B6 (B7) _______

B0-B6: are correct
POSSIBLE PROBLEM: B7=LOW, but should be HIGH 


BYTE N+1:
     ___   _   _        _   ______________   
CCLK    |_| |_| |_ .. _| |_|

         ___                   ___________     
DOUT ___|'1' B0  B1 ..  B5  B6 (B7) 

B0-B7: are correct
POSSIBLE PROBLEM: the early '1' 

In all the header bytes seen in DOUT, the bit B7 comes 1.5 T after the last
transition of CCLK. In the Xilinx 1992 Data Book says that bits in DOUT should
be delayed only 1/2 T of CCLK.

-------------------------------------------------------------------------

I think that our problem is similar of the one reported by Thomas Bachman
in article send to this news group. Also the configuration algorythm seems
to be equal, but he uses XC40XX and we use XC3090A.

I am sorry for a very long article.
Thanks in advance for the possible help.
It is very much wellcome !!!

+-----------------------+-----------------------------------------------------+
| Antonio J. A. Esteves |                                                     |
| Dep. Informatica      | esteves@di.uminho.pt                                |
| Universidade do Minho | Tel: +351 53 604479                                 |
| Largo do Pac,o        | Fax: +351 53 612954                                 | 
| 4719 Braga Codex      | PGP: finger -l esteves@shiva.di.uminho.pt           | 
| Portugal              | WWW: http://www.di.uminho.pt/~esteves/index.html    |
+-----------------------+-----------------------------------------------------+




Article: 1392
Subject: RE: Low cost CPLD/FPGA tools
From: Darren@pmel.com
Date: Tue, 13 Jun 1995 16:49:24 GMT
Links: << >>  << T >>  << A >>
Andreas Kugel wrote :

> Are ther any lowcost tools (approx < $500) for CPLD/FPGA
> designs available ?


How about FREE tools ?

Pilkington Micro-electronics Ltd. (PMeL) supply a FREEWARE version 
of their FPGA tools. The PMeL architecture is licensed as the 
Motorola MPA1000 series of FPGAs and the tools support an ever
increasing number of front-ends.

The on-line documentation includes a full architecture description
which can be very useful to new users or for educational purposes.

For further details see our web page - http://www.demon.co.uk/pmel
or email to info@pmel.com


Darren Wedgwood.


Article: 1393
Subject: Help! R.J. Francis' Ph.D thesis
From: c94nz@PROBLEM_WITH_INEWS_DOMAIN_FILE (Michael Zhu Ning)
Date: 13 Jun 1995 20:11:36 GMT
Links: << >>  << T >>  << A >>
Hi! FPGA folks,

Who can kindly tell me how to get R.J. Francis' Ph.D thesis, Univ. of
Toronto, Dept. of EEG?

Cheers!

Michael.Zhu.Ning@comlab.ox.ac.uk 


Article: 1394
Subject: Re: 17C256 EEPROMs from Atmel.
From: Martin Mason <martin@atmel.com>
Date: Tue, 13 Jun 1995 21:38:58 GMT
Links: << >>  << T >>  << A >>

Atmel Corp.  will be producing an AT17C256 EEPROM part in Q3 this year as 
part of it's family of eeprom 17XXX series parts.  The AT17C128 and 
AT17C65 are currently available in volume.  The pin compatable parts are 
EEPROM based and are 5V in system (re)programmable.  For more information 
contact your local Atmel sales office (details below) or e-mail 
martin@atmel.com including your snail-mail address.

-------------------------------------------------------------------------
|	Martin Mason		| FPGA Applications Eng.		|
|	Atmel Corp.		| (Work)	 martin@atmel.com	|
|	2125 O'Nel Drive 	| (Work2)	   fpga@atmel.com	|
|	San Jose		| (Fax) 	+ (408) 436 4300	|
|	CA 95131		| (Work) 	+ (408) 436 4178	|
-------------------------------------------------------------------------
| Atmel Offices Worldwide (* - Denotes FPGA Tech. Support Center)	|
-------------------------------------------------------------------------
|*North West    (408) 441 4270	 *South West    (714) 282 8080		|
|*North Central (708) 310 1200	 *South Central (214) 733 3366		|
|*North East    (617) 849 0220	 *South East    (919) 850 9889		|
|*Mid Atlantic  (609) 520 0606    Fax Back 	1-800-29-ATMEL		|
-------------------------------------------------------------------------
|*France 	(33) 1-48855522  *U.K. 		(44) 1-276 686677	|
|*Germany	(49) 69-7075910	  Scandanavia 	(358) 0-5023026		|
-------------------------------------------------------------------------
|*Hong Kong	(852) 721 1369	 *Japan 	(81) 3-5641-0211	|
| Korea		(82) 2-839 6341	  Singapore 	(65) 299 2891		|
-------------------------------------------------------------------------


Article: 1395
Subject: Any one working on Cypress PLD's ?
From: kirani@cinenet.net (kayvon irani)
Date: 14 Jun 1995 02:36:37 GMT
Links: << >>  << T >>  << A >>
	Hi every one!

	I am wondering if any one out there has tried out the Cypress's

	FLASH series ? They're supposed to perform same as or better than

	Altera parts but supposedly, they are much easier to re-route once

	the pins are fixed. BTW, any comment on AMD suit against them ?


From:	Kayvon Irani
	Lear Astronics Corp.
	3400 Airport Ave.
	Santa Monica, Ca 90405
	(310)915-6000 Ext. 3696
	(310)915-8369 Fax



Article: 1396
Subject: Re: Any one working on Cypress PLD's ?
From: mdv@cts.com (Mark Vorenkamp)
Date: Wed, 14 Jun 1995 13:03:52 GMT
Links: << >>  << T >>  << A >>
kirani@cinenet.net (kayvon irani) wrote:
>	Hi every one!
>
>	I am wondering if any one out there has tried out the Cypress's
>
>	FLASH series ? They're supposed to perform same as or better than
>
>	Altera parts but supposedly, they are much easier to re-route once
>
>	the pins are fixed. BTW, any comment on AMD suit against them ?
>
>
>From:	Kayvon Irani
>	Lear Astronics Corp.
>	3400 Airport Ave.
>	Santa Monica, Ca 90405
>	(310)915-6000 Ext. 3696
>	(310)915-8369 Fax
>

I used the Cypress Warp 3 software (regrettably) for thier 375 part; what a mess!  This software was loaded with bugs.  One severe
bug I found was that it kept trying to use input registers that didn't exist.  I understand this bug has not been fixed yet.  The fitter is
terrible.  Usually after hand assigning things to get a fit (necessary for me), if I removed some logic I would no longer get a fit.  The
PC based software gives very little info about errors and/or fitting problems.

Also, notice that when using preset and clear for the 370 family, you can't preset or clear just one register, you have to preset or clear
a whole block; not good for tweaking timing.

The Cypress software is a lot cheapter than Altera's, and it shows.

Reroutability depends on your application, as with all CPLDs

Mark



Article: 1397
Subject: Re: HELP on programming XC3090A
From: bachman@clipper.robadome.com (Thomas Bachman)
Date: 14 Jun 1995 15:18:36 GMT
Links: << >>  << T >>  << A >>
In article <3rkc4t$fea@icaro.uminho.pt>, esteves@di.uminho.pt (Antonio Esteves) writes:
>I think that our problem is similar of the one reported by Thomas Bachman
>in article send to this news group. Also the configuration algorythm seems
>to be equal, but he uses XC40XX and we use XC3090A.

Hi Antonio,

	We finally solved our problem, but I'm not sure if it's the same
	one as yours.  I'll describe what happened.

	A .rbt file was generated using the "rawbits" tool.  This file contains
	a few lines of header information (i.e. text containing date that the
	file was created, the version of the xact tools, etc.), and then ASCII
	ones and zeros -- the data needed to program the device.  For asynch.
	peripheral mode, we needed to convert this bit-stream into bytes so
	they could be loaded into the FPGA by the microprocessor.  I created
	a utility that would do this.

	The problem that we were having was mis-understanding what bit the
	most significant bit was.  In other words, if the .rbt file contained the
	following text (header part the the .rbt file):

		1111111100100000001111001000100110011111

	I would parse it into the following bytes:
	
		0xFF
		0x20
		0x3C
		0x89
		0x9F

	When we programmed the FPGA using this data, the INIT pin would
	go low after we programmed it with the first frame [we were using the
	4013, which has 266 bits/frame.  This means that 5 header bytes +
	(266 bits per frame)/(8 bits per byte) = 5 + 34 (2 bits from end of 
	the frame are combined with first 6 bits from next frame to make the
	last byte) = 39 bytes written to the device before we saw the INIT
	pin go low].  

	This assumes that the most significant bit is the first one, which
	it is not.  The most significant bit is the eigth one.  Therefore, the
	bit stream should be translated as:

		0xFF
		0x04
		0x3C
		0x91
		0xF9


	Other problems that we came across included:

	  o  Device not going active after programming.  

	     This problem has to do with the length count.  If you
	     are creating the .rbt file using what is referred to 
	     as the "DONE alignment" method, then the device may/may not
	     become active after writing the last byte.  The source of this
	     problem is that the FPGA is expecting a CCLK count corresponding
	     to the 24-bit length count given in the header.  We would program
	     the entire FPGA device, see the DONE pin go high, and yet the 
	     FPGA pins would not become active.  The problem is solved by
	     writing another byte to the device, triggering the extra CCLK
	     signals that it needs to activate the outputs.  Another solution
	     to this is to use the "Length Count Alignment" method.  Look in
	     the XACT User Guide (pgs. 6-41 to 6-45 ??) for more info.

	  o  Data on DOUT didn't seem to match the data written.

	     This was our mistake in interpreting the data.  We received an
	     application note from XILINX which noted:

	       "Each device passes the incoming header, including the length-
	        count value, on the DOUT pin, delayed by half a CCLK period,
		i.e. the bits are clocked out on a falling CCLK egde."

	     and also:

	       ".... and adusting for the fact that byte-wide interfaces 
		always leave the last bit sitting in the Parallel to Serial
		converter, shifting it out at the *beginning* of the next
		byte."

	     Thus, you should see the last bit on a byte on the first CCLK
	     of the next byte.

	Unfortunately, none of this is readily apparent from the data books 
	that XILINX provides.  Their technical support people mentioned that
	they were working on a app-note that describes this whole process.
	Let's hope that it comes out soon.

	Hope this helps,

		Thomas Bachman

-- 
!!!!! This .sig space for sale !!!!! 




Article: 1398
Subject: Re: HELP on programming XC3090A
From: seeker@indirect.com (Stan Eker)
Date: Thu, 15 Jun 1995 05:59:11 GMT
Links: << >>  << T >>  << A >>
Antonio Esteves (esteves@di.uminho.pt) reported:

<lengthy description of conditions removed - see original if you wanna
  jump in with some help, here.  Problem is peripheral-mode 3090a config.>

: We are monitoring the /INIT signal, while loading a configuration
: to the FPGA, and before the end of the file /INIT changes to LOW.

: Q: Does this mean error on the configuration file ?
                    ^^^^^ YES       ^^^^^^^     ^^^ NOT NECESSARILY

Yes - it's gone back and started the cycle all over again.  Dropping /RESET
low during the configuration process might do this.  You need to stop and
start all over again when it does this, but it's signaling a big PROBLEM
with your configuration logic/code if it happens at all.  Noise on VCC or
/POWERDOWN might cause it, and there was something else I've forgotten...

We only used the parallel/peripheral modes in one design; all the others
use the serial mode, so I'm more familiar with *those* problems.

: The signals CCLK, /INIT, /WS, LcaReady, /RESET seem to behave correctly
: during each byte writing cycle.


: I am sorry for a very long article.
: Thanks in advance for the possible help.
: It is very much wellcome !!!

The full description is the *only* way to give us enough info to deduce a
possible problem - it's very much needed, not flamebait.  There are SO many
ways to make it go wrong, and only a few to make it work correctly...


Article: 1399
Subject: AT&T serial eproms
From: max@softhard.sk ("Max Larine")
Date: Thu, 15 Jun 1995 06:08:30 GMT
Links: << >>  << T >>  << A >>
Does anyone know something regarding AT&T serial eprom programming
diagrams? There are two parts I'm interested in:
ATT1736
ATT17128
I have AT&T data sheets for these, but the only information related to the
programming procedure is the name of company which produces programmer.
Any information on these subject will be greatly appreciated.

All the best            Max Larine.

--- 
All the best			Max Larine.




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