Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 1450

Article: 1450
Subject: Re: Low cost ISA board
From: wware@world.std.com (Will Ware)
Date: Fri, 23 Jun 1995 17:41:16 GMT
Links: << >>  << T >>  << A >>
Michael J. Wirthlin (wirthlim@fpga.ee.byu.edu) wrote:
: This newsgroup has already
: discussed the reasons why FPGA/PLD vendors do not make the
: back-end programming information available.

I missed this discussion. Is there an archive somewhere, or could somebody
summarize it via email? (wware@world.std.com) Thanks.

: Perhaps some of the hardware vendors will be willing to
: sell the back end tools at a significantly reduced price (i.e. sell the
: bitstream generation program at a nominal cost) in order to maintain
: control of the proprietary information, yet allow hobbiests to use the
: tools.

If they did so (or published enough info to write freeware back-end tools),
wouldn't they gain a lot in hardware sales? Would this be offset by their
loss in software sales? Would it hurt them by facilitating their
competitors' efforts to reverse-engineer their parts?
-- 
-------------------------------------------------------------
Will Ware <wware@world.std.com> web - http://world.std.com/~wware/
PGP fingerprint   45A8 722C D149 10CC   F0CF 48FB 93BF 7289


Article: 1451
Subject: Re: Low cost ISA board
From: Andreas Kugel <kugel@mp-sun6>
Date: Fri, 23 Jun 1995 22:07:09 +0200
Links: << >>  << T >>  << A >>
I just got a statement from xilinx that at end of this year 
they will sell the new series 6200, which is a followup of the
algotronix chips, some of you might remember.
a sram based fpga with fine granularity, not like the 3000 or 4000
series.
with this family they will provide the programming information,
this means how to generate the bitstream, because the chips
are also partial reconfigurable while running.
maybe it would be a good idea, to check this and if it holds
true, the use this chips on the low cost board. maybe we could
get the alliance vhdl run with this chips, from vhdl down to
the bitstream. 
no more money for inefficent tools !!



--------------------------------------------------------
Andreas Kugel                
Chair of Computer Science V       Phone:(49)621-292-5755
University of Mannheim            Fax:(49)621-292-5756
A5
D-68131 Mannheim
Germany
e-mail:kugel@mp-sun1.informatik.uni-mannheim.de
--------------------------------------------------------



Article: 1452
Subject: Re: Xilinx PLDMAP usage. Pro's and Cons?
From: dstarr@world.std.com (David J Starr)
Date: Fri, 23 Jun 1995 23:15:03 GMT
Links: << >>  << T >>  << A >>
  Thanks for you input.  What do you mean by "redundant gates"?  Could
you elaborate?
David J. Starr



Article: 1453
Subject: create NLM FAST using ManageWare
From: Robin Cyrus <74774.257@CompuServe.COM>
Date: 24 Jun 1995 01:23:19 GMT
Links: << >>  << T >>  << A >>
	M   A   N    A    G    E   W   A   R    E 

 Create NetWare Loadable Modules and NetWare  utilities 
 with an easy, Visual Basic-like language, then compile 
 to generate stand-alone, royalty-free NLM and EXE files 
 that run on clients (DOS EXE) and servers (NLM). 	 					
                     
  call Robin Cyrus @ 602 970 1025 HiTecSoft at your service!                                                        
-- 

M A N A G E W A R E    THE BEST NLM maker 


Article: 1454
Subject: Re: Low cost ISA board
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 24 Jun 1995 13:39:00 GMT
Links: << >>  << T >>  << A >>
In article f4b@senator-bedfellow.MIT.EDU, jsmith@red-branch.MIT.EDU () writes:
>How many people out there would be willing to put some time and effort into
>a project to develop good solid tools, perhaps something akin the the FSF (
>gnu stuff).  I personally would LOVE to see a suite of good solid front end
>tools that interfaced to various backends depending on what FPGA/CPLD/etc
>that one choose to use.
>
>I realise getting the programming information for the backends might take
>some doing, however.. the front end we can get started on now.

I suggest someone summarize this thread, repost it as Low Cost FPGA/CPLD Tools 
and crosspost on comp.lang.verilog.

There are several CAE vendors who have free and/or cheap versions of verilog.

Both CAE vendors and FPGA/CPLD vendors presumably would be interested in 
decent low cost tools.  Starting a shareware toolkit, library, utilities etc.
somewhere is interesting.  Perhaps the kind folks who support the archive could 
help?  

Seems like a great university project.  

>I am more than willing to put some effort into programming and organizing
>such a project, if I can get a few other people (at least) willing to spend
>some time at it.

Sorry, I have good tools in my job and a life outside my job.

In order to pull working people into this, you might try coordinating with 
user groups for CAE tools and FPGA/CPLDs.  This might help in general.

---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1455
Subject: Re: Low cost ISA board
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 24 Jun 1995 14:15:12 GMT
Links: << >>  << T >>  << A >>
In article 2Gu@world.std.com, wware@world.std.com (Will Ware) writes:
>Is there an archive somewhere

http://www.super.org:8000/FPGA/caf.html
COMP.ARCH.FPGA Archive

---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1456
Subject: EDA Sales Person Wanted
From: dcui@aol.com (DCUI)
Date: 24 Jun 1995 10:51:46 -0400
Links: << >>  << T >>  << A >>
Intergraph seeks EDA sales person for the Research Triangle Park, NC. 
Must have 3-5 years experience in EDA, solid communications and
presentation skills a must.  Phone or fax resume to 603-664-5523 or
respond via email to dcui@ingr.com
Dan Cui


Article: 1457
Subject: Re: Low cost ISA board
From: Bill Cox <102113.2207@CompuServe.COM>
Date: 25 Jun 1995 06:55:16 GMT
Links: << >>  << T >>  << A >>
Hi.

I sympathize with the low cost tool idea.  I write FPGA place and 
route software for QuickLogic for a living.  It is possible for 
one person to write good quality tools including placement, 
routing, and generating programming information.  However, I 
believe you will find resistance from many of the vendors (not 
QuickLogic).  Altera, Actel, and Xilinx jelously guard details 
required to implement a netlist in their parts.  In truth, there 
are few vendors other than Altera who really want interoperable 
tools.  Xilinx bought NeoCAD partly to eliminate generic tools.  
Also, almost half of the work (but only 15% of the code) in FPGA 
automatic tools are in handling wacky special cases specific to 
an architecture, so significant work must be done to support each 
new one.

I would be willing to contribute to front-end tool developement.  
A simple schematic capture, and a simple synthesis language and 
simulator shouldn't be too hard with a good group of programmers.

As for backend tools, what if someone offered a service over the 
internet to place and route designs for you using vendor supplied 
tools at a minimal charge?

-- Bill

-- 

Bill Cox
cox@qlogic.com


Article: 1458
Subject: Wanted. orcad Library for PALASM.
From: Vincent.Himpe@ping.be (Vincent Himpe)
Date: Sun, 25 Jun 1995 16:03:36 GMT
Links: << >>  << T >>  << A >>
Hi.

I'm looking for the Orcad library that comes with AMD's Palasm toolchain.
I have an orcad schematic that has been built with this library and i can't
display it because i don't have this library.Only the wires show up.Not the
symbols since the library is missing.

regards
Vincent
--------------------------------------------------------------
Vincent Himpe
                                                 /////
Internet :                                       O  *)
   vincent.himpe@ping.be                          /
   vi_himpe@mietec.be                            \__/
Fido :
  2:291/1912.8

http://www.ping.be/~ping0751
--------------------------------------------------------------



Article: 1459
Subject: What about Veribest?
From: ast@actcom.co.il (Gideon Amir)
Date: Sun, 25 Jun 1995 16:10:18 GMT
Links: << >>  << T >>  << A >>
	I'm willing to design a small ASIC (5k) using a PC package. I'm 
considering either Viewlogic or Integraph's Veribest for schematic & 
simulation and perhaps some synthesis jobs. 
 	I know quite well the Viewlogic tools. 
	Veribest look good, but...
	Have anyone used Veribest for a REAL ASIC design? What are the 
pitfalls and advantages? What about sign-off certification?
	
	I appreciate any feedback. 

	M. Zalcberg 



Article: 1460
Subject: Place-n-Route service
From: fliptron@netcom.com (Philip Freidin)
Date: Mon, 26 Jun 1995 02:08:18 GMT
Links: << >>  << T >>  << A >>
I really hope I am not going to regret this........


This message is only posted to comp.arch.fpga. When (if) the
issues are resolved, I will post announcements into other
appropriate groups.


What follows is a request for suggestions for the creation of
a cheap (but not free) system for non-corporate users to get
access to place and route tools for FPGAs. I have been thinking
about providing such a service for about a year and a half, but
have finally realized that if I don't tell anyone that I am
thinking about this, I will be stuck with just my own ideas on
the subject, and clearly, after a year and a half I have not
managed to resolve all the issues that I need to resolve to 
offer such a service.

Philosophy:
	The current situation for hobbyists and students who
don't have access to the current state of the art technology
is tragic. When I can go to FRY's (an electronics store in
the Silicon valley) and buy a floppy disc controller board
including cables and brackets for less that I need to pay to
buy the floppy disk controller chip on the board, I have no
trouble understanding why the home hardware hacker of
computer and digital design is a dying breed. Go look in
alt.comp.hardware.homebuilt to see what I mean. As an
ex-lecturer of comp.sci and elec.eng I know that the students
that do 'stuff on the side' as opposed to only course work
tend to do far better in the practical work and actually have
an understanding of what they are learning, and are much
better at applying it. They also tend to be the only ones who
can handle the cross discipline work required in integrating
hardware with software.
	Todays state of the art digital technology that is an
ideal platform for digital systems design for proffesionals,
hobbyists, and students, are the FPGAs. I do not believe that
they are too expensive to use, especially the reprogrammable
RAM base products from Xilinx. You can order them in one-off
quantities from companies like Digi-Key and JDR, for as little
as $16.74 (current Digikey catalog, page 83, XC3020-70PC68C).
There are two barriers for the above mentioned target audience
that I want to serve: The cost of the place and route tools,
and the learning curve to use them.


The service I would like to offer:
	I would like to offer a service to the students and
hobbyists who want to use these products, but can't afford the
place and route tools. As a hobbyist myself, I paid for a set
of these tools some time ago and have used them for many
projects. I am now a consultant, and still use these tools,
and am about to double the number of machines I will be
running with these place and route tools. Since they are not
running 24 hours a day (sometimes) there are unused place-and-
route hours available.

	Here's what I have in mind:

	1) People email me either XNF files or SCH/SYM files
	2) I run the appropriate tools to convert and compile
	   the design to a bitstream  (.BIT/.RBT)
	3) I email the results and reports back to you.
	4) You pay me.

What help do I need:

	I need opinions and ideas on all of the following:

	1)  How do I set this up so that it requires almost
	    zero effort for me to run. I.E. if I have to
	    baby sit each run, then I don't have the time
	    for this. 

	2)  How do the users of the service create XNF files.
	    I don't know of any public domain schematic
	    capture system that runs on PCs that includes
	    Xilinx compatible libraries and netlist generators.

	3)  How do the users of the service debug their designs
	    when they don't work.

	4)  How much should I charge for the service $5 ?? $50 ??
	    or what...???  Should it be per run? Should it be
	    per CPU hour, should it be by device type ....
	    How do I collect.

	5)  How do I respond to people who complain about the
	    above question ??

	6)  When this all falls flat on its face (no interest or
	    no easy way for people to get XNF to me or this all
	    degenerates into a flame war about proprietory
	    software, and how the vendors should just give it
	    away, and couldn't a few of us net critters just get
	    together like the GNU folks and write a better place
	    and route software anyway, and .....) how do I save
	    face.

	7)  When this becomes wildly successful, and it is too
	    much for me to look after, how do I hand over the
	    service to someone else, or shut it down.

	8)  How do I set myself up as a clearing house for the
	    PD software that will be needed to generate the XNF.

	9)  How do I find people who want to help in creating and
	    running this service.

	10) Are there any legal things I should be worrying about.

	11) Should I ever consider bulk buying of these chips and
	    selling them to users of the service.

	12) If things are successful, should there also be an
	    archive of design modules: PCI, UART, VME, PC-AT, SCSI
	    and other things that people want to share.

	13) What would be needed to make this TOTALLY automatic,
	    so that I didn't need to do anything to run someone's
	    design.

	14) I DO NOT WANT TO DEBUG PEOPLES DESIGNS FOR THEM. After
	    making this clear to all users of the service, how
	    should I deal with people who flame me publically for
	    not helping them with their designs, and charging them
	    for place and route runs that didn't work.

	15) Which products should I support: XC3000, XC4000, XC5200,
	    XC6200, XC7000, XC8000, MAX5000, MAX7000, MAX9000,
	    FLEX8000, AT6000, MACH100/200/300/400, QLxxXyy, ACT10xx,
	    ACT12xx, ACT14xx, 22V10

	16) Please enter your own question here that you feel
	    others need to think about and answer, and which I
	    should have thought about too.

	17) Am I nuts?


Why can't someone else compete with me at a cheaper price:

	Sounds like a great idea to me. All I want is for hobbyists
	and students to have access to the current state of the art
	just as I did when I was a lad (oh so many years ago). Once
	(when...if) I have the service set up, I can't see why I
	wouldn't want others to also offer the same or better
	service. I expect that the only proprietory/licensed
	software that will be involved will be the place and route
	software. The rest must all be PD, so that the cost of
	entry into all this for someone is having access to a
	reasonable PC, buying a chip, downloading the appropriate
	PD software, and paying me for the 'run'. Others who have
	also purchased licenses for the place and route tools could
	offer similar services.


Why don't the vendors themselves offer such a service:

	I'll probably find out the hard way.


Why the service is not free:

	Because I had to buy the computers, the software, the net
	access, and it's going to require my time.


Who is this Philip Freidin anyway:

	I am an independent consultant, with a little business
	called Fliptronics. I do not currently work for any FPGA
	company, although I have in the past. I	make my living
	doing digital systems design, and Windows programming.

	I am quite knowledgeable about these products.

	I am still a hw/sw hobbyist.



Thankyou for your interest in reading all of this 


Awaiting your input.
praying to avoid a flame-fest


Philip Freidin		fliptron@netcom.com







Article: 1461
Subject: InOut Port in the Synopsys FPGA Compiler
From: jean@cis.nctu.edu.tw (Feng-Chen Chang)
Date: 26 Jun 1995 09:48:08 GMT
Links: << >>  << T >>  << A >>
Hi ! Everybody we are now using 
the Synopsys FPGA compiler and 
Xilinx XACT 5.1, there is a 
probelm that we counter.
We use the VHDL to describe 
our design and we use a bidirection 
port(InOut).
The problem is how to insert a 
bidirection I/O with Synopsys FPGA 
Compiler. 
 
 
 
 
We will appreciate your replay in the tin or mail jean@pds.cis.nctu.edu.tw 
 
-- 
            Feng-Chen Chang - (035) 712712-56668 - jean@pds.cis.nctu.edu.tw
National Chiao Tung University - Computer and Infomatiom Science. Dept. 
                Hsinchu, Taiwan 30050, Republic of China  
                       Parallel and Distribute Laboratory




Article: 1462
Subject: Re: The "InOut" Port mode in the Xilinx FPGA
From: Yuce Beser <yuce@sh.bel.alcatel.be>
Date: 26 Jun 1995 12:09:53 GMT
Links: << >>  << T >>  << A >>
Dave,
I am using the XSI interface (Xilinx Synopsys Interface), and for bidirectional
ports, I am instantiating the IOBUF (bidirectional buffer) component.

Definition:
	component IOBUF 	
	port (	O	:out std_logic;
		I	:in std_logic;
		T	:in std_logic;
		IO	:inout std_logic	-- signal type INOUT !
    	     );
	end component;


Instantiation: (If I apply it to your illustration)
	I1:IOBUF port map (sig_in, sig_out, out_en, data);


>
>
>  	sig_out        |-------|
>      --------------->| obuft |----->
>                      |-------|     |
>                 out_en   |         |      |-------|
>                 -------->|         |<---->| Bipad | "data"
>                                    |      |-------|
>        sig_in        |-------|     |
>      <---------------| ibuf  |<----
>                      |-------|
>


Yuce Beser



Article: 1463
Subject: Save Your Computer!
From: Britestar (Britestar, Inc.)
Date: Mon, 26 Jun 1995 18:35:43 GMT
Links: << >>  << T >>  << A >>
				"Save Your Computer"

Surge sentry computer grade with fax/modem.

four outlet surge/noise cube with two RJ-11 jacks for fax/modem line
and power protection.  3 stage/line circuitry.  1 picosecond clamp
response time.  Emi/rfi noise rejection to 35db.  UL 1449 rating at
330v.  347 joules.  Max surge 11,505 amps.  Lifetime warranty and
power protection.  Putty.  2"h x 4"w x 6.5"d.
MFG# ds41psg1.  Shipping weight 1.721 lbs.

Price:  $69.95, shipping and handling included.

---------------------------------------------------------

			"Repair your Computer"

Computer tool kit.  By Curtis.

Can be used to repair maintain and upgrade virtually any microcomputer
system.  All tools are demagnetized.  Lifetime warranty.  Zipper vinyl
case.  Black 6"h x 9"w x 1.37"d.

MFG# tk3ctf  20 piece set (l lb).
Price  $29.95.  Shipping and handling included.

MFG#	tk4ctf 55 piece set (3 lbs).
Price $52.99.  Shipping and handling included.

-----------------------------------------------------

			"Super discount"

Voice activated telephone recorder.  By TT Systems.

One button record, pause, fast forward/rewind, volume control, tape
counter, cue and review, LED record light, built-in condenser mic for
non-phone recording.  AC or battery powered.

Uses standard cassettes.  Black.  1.5"h x 7"w x 4"d.

MFG# vtr500tts.  Shipping weight 2.28 lbs.
Special price $199.95.  Shipping and handling included.  Save $100
dollars!

Send your check or money order to:
Britestar Enterprises
3701 Inglewood Ave
Suite #304
Redondo Beach, CA  90278

Please list MFG# with your order.  Please allow 7 - 10 days for
delivery.

-------------------------------------------------------

			Money Manager Software

"MoneyManager," from Times Publishing does virtually everything
Quicken does, and even surpasses it in some respects due to a more
powerful language it uses.  (IBM compatible only).

"MoneyManager" for Windows is the software that allows a person to
take control of their personal finances by organizing, tracking and
reporting income, expenses, assets, liabilities and investments on a
daily basis on his PC.

"MoneyManager" prints checks, pays bills and reconciles even the most
complex bank statement in seconds.  "MoneyManager" tracks your
checking, savings, credit card and money management.

You can record and categorize your expenses, compare them to budgets
and know exactly where your money goes.

Keep your investment of stocks, bonds and mutual funds portfolio
up-to-date with "MoneyManager."

Calculate and analyze your gains, losses and returns on investments
and tax consequences in an instant.

Thinking of buying a home?  "MoneyManager" will create a home
affordability analysis for you.  Lease-or-buy decisions were never
easier.

Want to pay off that mortgage faster?  It will produce amortization
schedules and show you the whopping savings in interest you can
realize by making small prepayments of principal.

How about income statement, balance sheet, cash flow forecasts, and
net worth projections?  All of these are available at your fingertips
with "MoneyManager."

Sale price: $24.99 - Shipping and handling included.  7 - 10 days for
delivery.  Comes in 3 1/2 or 5 1/4 diskettes, (choose one).

Send your check or money order to:
Britestar Enterprises
3701 Inglewood Ave
Suite #304
Redondo Beach, CA  90278

--------------------------------------------------------
				Geographics

GEO4000 Moving Message Color Sign, from "Geographics"

Multi-color: 16 vibrant colors/hues.  Displays maximum 27 characters,
minimum 14 characters.  3 fonts, 4 text styles, 10 preprogrammed
graphics, 46 European characters.  "Magic" interface.  Network up to
254 signs.  90-day memory backup.  Display area:  3"H x 37.6"W.
Indoor use only.  Includes wireless remote, mounting brackets and
adapter.  5.5"H x 39.6"W x 1.4"D.
Shipping weight 11 lbs.  
MFG# 08386EZL.

Sale price $370.50, shipping and handling included.

---------------------------------------------------

				"Fresh Air"

"Bionaire" 2 speed personal air purifier/ionizer.

Cleans air in a room 10' x 10' x 8' in 12 minutes.  2-speed, low
noise, turbo system.  4 stage filtration system.  Effective on tobacco
smoke, pollen, dust, bacteria.  Ion on/off switch.  Flame retarded,
injection-molded plastic casing.  One year limited warranty.  Black.
12.5" x 7.5" x 8"d. 

MFG# f7obio.

Price $94.95, shipping and handling included.

--------------------------------------------------------

				18 Karat Gold

"Cross" 18 Karat Gold Fountain Pen.

18 Karat Gold Fountain Pen available in four 18 Karat nib widths.
Piston converter included.  Gift boxed.  Comes with Lifetime
Mechanical Guarantee.  Shipping weight 1 lb.

MFG# 8036bcro  Broad	nib
MFG# 8036mcro Med.	nib
MFG# 8036fcro   Fine  	nib
MFG# 8036xcro  X-fine 	nib

Price $990.64, Shipping and handling included.  Save $279.36.

Send your check or money order to :

Britestar Enterprises
3701 Inglewood Ave
Suite #304
Redondo Beach, CA  90278

Please list MFG# with your order.  Please allow 7 - 10 days for
delivery.

---------------------------------------------------------

			Snail Mail Order Form

Send your check or money order to:
Britestar Enterprises
3701 Inglewood Ave
Suite #304
Redondo Beach, CA  90278


Name: ________________________________________________________

Address: ______________________________________________________

City/State/Zip:_______________________________________________

Phone:  _______________________________________________________

I've enclosed my check or money order for:

"MoneyManager" software for Windows.

Diskette Size:  3 1/2  ____     5 1/4  ____

Surge sentry computer grade with fax/modem
MFG# ds41psg1
Price 69.95, shipping and handling included.		[  ]

Computer took kit.  By Curtis.

MFG# tk3ctf  20 piece set (l lb)
Price $29.95, shipping and handling included.		[  ]
MFG# tk4ctff  55 piece set (3 lbs).
Price $199.95, shipping and handling included.		[  ]

Voice activated telephone recorder.  By TT Systems.
MFG# vtr500tts  shipping weight 2.28 lbs.
Special price $199.95. Shipping and handling included.	[  ]

GEO 4000 Moving Message Color Sign, from :Geographics"
MFG# 08386EZL
Sale price $370.50, shipping and handling included	[  ]

"Bionaire" 2 speed personal air purifier/ionizer
MFG# f7obio.
Price $94.95, shipping and handling included.		[  ]

"Cross" 18 Karat Gold Fountain Pen
MFG# 8036bcro  Broad	nib				[  ]
MFG#  8036mcro Med.	nib				[  ]
MFG#  8036fcro Fine	nib				[  ]
MFG# 8036xcro  X-fine	nib				[  ]
Price $990.64.  Shipping and handling included.

			"Never leave home to shop"

A 544 page catalog, with over 12,356 name brand
items, filled with office/electronic products.
Names like Sony, Sharp, Magnavox, Panasonic,
JVC, Packard Bell, Brother, Cobra, Toshiba,
Pioneer, Casio, and over 216 others.
Price $8.00, shipping and handling included.		[  ]


................................
.  BriteStar, Inc.               
.  3701 Inglewood Ave            
.  Suite 304                     
.  Redeondo Beach, CA            
.  90278                         
..................................



Article: 1464
Subject: PREP benchmark data access
From: sbaker@best.com
Date: 26 Jun 1995 21:07:11 GMT
Links: << >>  << T >>  << A >>
A little apology.

When questions about PREP benchmark winners went up on this newsgroup some days ago I responded with the URL for the 
PREP homepage.  And we got lots of action at prep.org.  But not everyone got through to the data.

Unfortunately, at the same time the PREP page was being moved to a new site and not all of the pages were available.

By Tuesday morning they should all be working fine.

I'm sorry for inconveniencing anyone searching for the PREP certified programmable logic benchmark data.  By tomorrow you will be 
able to access the data at "http://www.prep.org".

If you have any more troubles getting rhrough or if you have any further comments about the page, please let me know.

Stan Baker
President,
PREP Corp.
sbaker@prep.org



Article: 1465
Subject: Re: low cost ISA board
From: sc@vcc.com (Steve Casselman)
Date: Mon, 26 Jun 1995 21:53:59 GMT
Links: << >>  << T >>  << A >>
Our low cost ISA board is comming along. Thanks
to everyone who E-mailed me their comments:)

So far the design looks like:
ISA plug&paly (Fujistu part windows 95 ready)
Xilinx 5210 160pqfp
EEPROM
32Kx8 Sram Socket
Sockets for old Drams
Programmable Oscillator (opt)
Analog prototype area near backplate
Large Digital protoptye area
All Xilinx pins broken out

To include:
Schematic Capture
Logic simulation and timing
Xilinx place and route tools

Target Price $995

Steve Casselman
Virtual Computer


Article: 1466
Subject: Re: Place-n-Route service
From: mbutts@netcom.com (Mike Butts)
Date: Mon, 26 Jun 1995 22:24:06 GMT
Links: << >>  << T >>  << A >>
Great idea.  I hope the compilcations don't spoil it.

Lack of tools is a terrible problem, one that I'm
convinced is blocking what would be a real return
of independent amateur hardware design.  Would Woz
have built the Apple if he'd had to buy $$ tools
just to use the chips at all?  Unfortunately
FPGA vendors do have defensable reasons for keeping
their codes proprietary, besides optimization of
short-term shareholder value from sales of tools.  Many
commercial FPGA users would object to the ability to
reverse-engineer hardware designs that published
configuration codes could enable, for one example.
Remote execution of FPGA tools on a pay-per-use
server could solve this deadlock.

A paper at this year's DAC may be worth a look in
this context.  A system called "Henry" is proposed,
for doing EDA across the Web, with remote execution
of tools.  Design files in the form of "active
documents" traverse the Web between user and tool
server, and the tool runs at the remote Web 
site, paid for per-use.  The tool server could be
at the tool vendor and/or some third party.

There are many more details, issues, and such raised
by the paper.  *Please* let's not start debating
all that here.  Just go read the paper.  Maybe it's
even readable on DAC's Web site, I know a few papers
were (http://www.dac.com).  I'd check but have no
browser handy here.

I think what Philip proposes will work fine with
ordinary email or ftp or telnet, and should start
that way for now.  Keep it simple.  But I think
it's interesting that the Web is prompting some
to propose just such a model for all EDA tool 
usage.  Maybe the FPGA tool server will be an early
example of Web-based design.

The paper is:
Mario J. Silva, Randy H. Katz, "The Case for Design
Using the World Wide Web", Proc. 32nd ACM Design Automation
Conference, June 1995, p. 579-585.
(The authors are at UC-Berkeley.)

   --Mike

-- 
Mike Butts, Portland, Oregon   mbutts@netcom.com



Article: 1467
Subject: Re: InOut Port in the Synopsys FPGA Compiler
From: yjhou@Qualcomm.com (Jason Hou)
Date: Mon, 26 Jun 1995 16:38:03 -0700
Links: << >>  << T >>  << A >>
In article <3slvoo$i9l@debbie.cc.nctu.edu.tw>, jean@cis.nctu.edu.tw
(Feng-Chen Chang) wrote:

> Hi ! Everybody we are now using 
> the Synopsys FPGA compiler and 
> Xilinx XACT 5.1, there is a 
> probelm that we counter.
> We use the VHDL to describe 
> our design and we use a bidirection 
> port(InOut).
> The problem is how to insert a 
> bidirection I/O with Synopsys FPGA 
> Compiler. 
>  

Did you remember to place the InOut pad into 'Z' when OE = 0?
That will do it every time.  I have no trouble declaring it
as port INOUT with Synopsys.


Jason Hou,
Qualcomm Inc.,
yjhou@qualcomm.com


Article: 1468
Subject: Re: Place-n-Route service
From: daveb@perth.DIALix.oz.au (David Brooks)
Date: 27 Jun 1995 09:10:23 +0800
Links: << >>  << T >>  << A >>
fliptron@netcom.com (Philip Freidin) writes:

[Long article, heavily snipped to save bandwidth]


>What follows is a request for suggestions for the creation of
>a cheap (but not free) system for non-corporate users to get
>access to place and route tools for FPGAs.

>Philosophy:
>	The current situation for hobbyists and students who
>don't have access to the current state of the art technology
>is tragic.

>There are two barriers for the above mentioned target audience
>that I want to serve: The cost of the place and route tools,
>and the learning curve to use them.


>	Here's what I have in mind:

>	1) People email me either XNF files or SCH/SYM files
>	2) I run the appropriate tools to convert and compile
>	   the design to a bitstream  (.BIT/.RBT)
>	3) I email the results and reports back to you.
>	4) You pay me.

>What help do I need:

>	I need opinions and ideas on all of the following:

>	1)  How do I set this up so that it requires almost
>	    zero effort for me to run. I.E. if I have to
>	    baby sit each run, then I don't have the time
>	    for this. 

    With expert users supplying the XNFs, probably little problem. Could 
be bad with newbies (no fault of theirs), whose runs may do unexpected 
things. We all took some time to learn how to drive these things properly.

>	2)  How do the users of the service create XNF files.
>	    I don't know of any public domain schematic
>	    capture system that runs on PCs that includes
>	    Xilinx compatible libraries and netlist generators.
 
    One answer would be to build such a library, that does work on a PD 
schematic capture. Not a trivial task, to be sure.

>	3)  How do the users of the service debug their designs
>	    when they don't work.

    This (IMHO) is the big one. I spend plenty of time running ViewSim on 
my design, before it ever gets near the hardware. You (as a service 
bureau) cannot do this: it needs the circuit designer hands-on. No, I 
don't know of a PD version of ViewSim.

>	4)  How much should I charge for the service $5 ?? $50 ??
>	    or what...???  Should it be per run? Should it be
>	    per CPU hour, should it be by device type ....
>	    How do I collect.

    I would suggest per CPU hour - it's all the same to you what devoce 
library they are reading from (IMHO). The payments issue could open that 
famous worm-bucket called "payments via Internet". 

>	5)  How do I respond to people who complain about the
>	    above question ??

    If they don't like it/you, they don't have to use same.

>	6)  When this all falls flat on its face (no interest or
>	    no easy way for people to get XNF to me or this all
>	    degenerates into a flame war about proprietory
>	    software, and how the vendors should just give it
>	    away, and couldn't a few of us net critters just get
>	    together like the GNU folks and write a better place
>	    and route software anyway, and .....) how do I save
>	    face.

    Hmm, is that really an issue? You have done your best to help people 
(thereby doubtless creating much good karma :-), if they refuse to 
use your service, not your problem.
    I am here assuming that you will get some _positive enjoyment_ out of 
setting this thing up - if you are doing it as a money-making venture 
(nothing wrong in that, just different priorities) then "face" is not 
involved, just dollars.

>	7)  When this becomes wildly successful, and it is too
>	    much for me to look after, how do I hand over the
>	    service to someone else, or shut it down.

    You might publish it as shareware - so you still get "royalties", and 
the workload is spread.

>	8)  How do I set myself up as a clearing house for the
>	    PD software that will be needed to generate the XNF.

    You'll need to input plenty if time, I suspect. As to the mechanics, 
the GNU project people could probably give you some tips.

>	9)  How do I find people who want to help in creating and
>	    running this service.

    Ditto. (Your post here is a good start).

>	10) Are there any legal things I should be worrying about.

    I don't know: just read your software license carefully.

>	11) Should I ever consider bulk buying of these chips and
>	    selling them to users of the service.

    Do you really want to compete with the Fry's of this world? I don't 
see how you would make anything out of this side of it.

>	12) If things are successful, should there also be an
>	    archive of design modules: PCI, UART, VME, PC-AT, SCSI
>	    and other things that people want to share.

    Hopefully, this will evolve naturally. (An excellent idea).

>	13) What would be needed to make this TOTALLY automatic,
>	    so that I didn't need to do anything to run someone's
>	    design.

    You would need to limit your service (in the Xilinx paradigm) to just 
running XMAKE and XDELAY in a hands-off mode. And make it clear that is all 
you do.

>	14) I DO NOT WANT TO DEBUG PEOPLES DESIGNS FOR THEM. 

    Assuredly. And this is the nub of it: I pity anyone trying to debug a 
design "blind" in the hardware. For the scheme to work, we do need a PD 
logic simulator.

>	15) Which products should I support: XC3000, XC4000, XC5200,
>	    XC6200, XC7000, XC8000, MAX5000, MAX7000, MAX9000,
>	    FLEX8000, AT6000, MACH100/200/300/400, QLxxXyy, ACT10xx,
>	    ACT12xx, ACT14xx, 22V10

     I use XC3100 and XC4000, but that's just my one vote.

>	16) Please enter your own question here that you feel
>	    others need to think about and answer, and which I
>	    should have thought about too.

>	17) Am I nuts?

    Not at all: I have often wished a similar thing existed somewhere.

>Philip Freidin		fliptron@netcom.com





-- 
David R. Brooks <daveb@perth.DIALix.oz.au>    Tel/fax. +61 9 434 4280
"Government is not reason. It is not eloquence. It is a force. 
Like fire, a dangerous servant and a fearful master." - G. Washington 



Article: 1469
Subject: Re: Place-n-Route service
From: wware@world.std.com (Will Ware)
Date: Tue, 27 Jun 1995 03:11:37 GMT
Links: << >>  << T >>  << A >>
Mike Butts (mbutts@netcom.com) wrote:
: A paper at this year's DAC may be worth a look in
: this context.  A system called "Henry" is proposed,
: for doing EDA across the Web, with remote execution
: of tools.  Design files in the form of "active
: documents" traverse the Web between user and tool
: server, and the tool runs at the remote Web 
: site, paid for per-use.  The tool server could be
: at the tool vendor and/or some third party.

The question of how to charge fairly for this service over the net is
a perplexing one, but this looks like a great place to start. Here's
a related thought: Hand out passwords that act as debit cards. It would
work like this. I want to use your service, so before I do, I send you
a check and in response you create an account for me, and send me the
username and password. I use the name and password to telnet to your
tool server, and my account has been assigned some number of CPU hours. 
When my design has been satisfactorily placed and routed, I can redeem
the remaining hours on my account, sell or donate my account to somebody
else, or leave the account open if I'm planning more designs in the
future. People on limited budgets might pool their resources and share
an account, provided they can find some suitable arrangement among
themselves to insure an equitable division of CPU hours. If I sell,
donate, or share my account, it doesn't add any bookkeeping for the
service provider.
-- 
-------------------------------------------------------------
Will Ware <wware@world.std.com> web <http://world.std.com/~wware/>
PGP fingerprint   45A8 722C D149 10CC   F0CF 48FB 93BF 7289


Article: 1470
Subject: Re: Place-n-Route service
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 27 Jun 1995 07:21:08 GMT
Links: << >>  << T >>  << A >>


Here are some more thoughts on my subject (following up my own article  :-)

1) My thinking is that I want this to be a service that a hobbyist
   can use without feeling it is too expensive. My intent is NOT to make
   money on this, Not to pay for my computer and software, and not to pay
   for my time. My hope is that it would cost a hobbyist $5 to get a 3020
   routed.

2) given the problems that others have highlighted for me, and given that
   the target audience is probably not highly familiar with FPGAs, I dont
   think I want to support large-complex designs. How do the following
   constraints strike you (as examples)
	A) only 3020, 3030, 3042, 4002/3/4/5/6
	B) no more than 70% full
	C) Only 1 clock net, all FFs must use this net, via a global buf
	D) No async reset/presets
	E) No locked pinouts
	F) Clock rates no faster than (pick a number: 1MHz, 5MHz, 10MHz..)

3) It seems that the PD tools MUST include simulation, and that it should
   be a pre-requisite before a design is submitted. I certainly thoroughly
   simulate all my designs before I get near the place-n-route tools.

Thanks for your interest.
	Philip Freidin		fliptron@netcom.com



Article: 1471
Subject: Re: Place-n-Route service
From: acher@informatik.tu-muenchen.de (Georg Acher)
Date: 27 Jun 1995 09:38:56 GMT
Links: << >>  << T >>  << A >>

In article <fliptronDAtLr9.BHw@netcom.com>, fliptron@netcom.com (Philip Freidin) writes:
...
|> 2) given the problems that others have highlighted for me, and given that
|>    the target audience is probably not highly familiar with FPGAs, I dont
|>    think I want to support large-complex designs. How do the following
|>    constraints strike you (as examples)

I can route for myself, but if I have to use your service, here are my 0.01$:

|> 	A) only 3020, 3030, 3042, 4002/3/4/5/6

That's OK, someone who needs an 4025 is certainly no hobbyist :-)


|> 	B) no more than 70% full

The number of used CLBs has no great meaning for routing time. PPR has a very
funny behavior if you run several routings on the same(!) design, sometimes it
takes twice as long (the resulting .lca file works as fine as the others, but not
better...)

|> 	C) Only 1 clock net, all FFs must use this net, via a global buf

I can't imagine that FPGAs for hobbyists are just fully synchronuos state
machines with no asynchronous tricks. If you started with TLLs and GALs it's
difficult to get away from these behaviors, and sometimes you simply need this
tricks to get the design running.

|> 	D) No async reset/presets

Ditto, if you design an PCI interface, you won't need this, but if you design
some 'integrated' glue logic you can't avoid it (sometimes...).

|> 	E) No locked pinouts

If you just accept designs without locked pinouts, forget it... If one detects an
error in the design running in 'real world' and has to reroute, he is forced to
change his PCB again... That's not much fun :-(

|> 	F) Clock rates no faster than (pick a number: 1MHz, 5MHz, 10MHz..)

10-15MHz are low enough to avoid trouble (setup/hold etc.), if you are using the 
3000A-series.

3) It seems that the PD tools MUST include simulation, and that it should
   be a pre-requisite before a design is submitted. I certainly thoroughly
   simulate all my designs before I get near the place-n-route tools.

I don't know, wether an hobbyist can simulate the design without forgeting an
important bug. Especially if timing simulation (after the routing) shows that the
design won't run properly :-( or if it even works in timing simulation but then you
have trouble with the evils of high frequency, clock jitter, signal ringing and
anything else that cause so much fun in designing ;-)

PS: Use the fastest PC you can get. I've worked til last week with a 486SX/33MHz
and PPR needs about 60min to get it routed. Now I have an Pentium/90MHz and it's
done in 5-6min!
-- 
	Bye
	Georg Acher
+--------------------------------------------------------------+
|         Georg Acher, acher@informatik.tu-muenchen.de         |
|           "Oh no, not again !" The bowl of petunias          |
+--------------------------------------------------------------+


Article: 1472
Subject: Lattice Semiconductor WWW ??
From: g-o-berg@dircon.co.uk (Geir Olav Berg)
Date: 27 Jun 1995 10:58:38 GMT
Links: << >>  << T >>  << A >>
Does anybody know if Lattice Semiconductors has got a WWW page somewhere ?

Geir Olav Berg   g-o-berg@dicron.co.uk



Article: 1473
Subject: Re: The "InOut" Port mode in the Xilinx FPGA
From: jean@cis.nctu.edu.tw (Lin Feng Ming)
Date: 27 Jun 1995 11:30:22 GMT
Links: << >>  << T >>  << A >>
Beser,
We are wondering where the IOBUF is and how to use it ?

Should we instantiate it each time we need or it can be auto instantiated
(inserted) by the Synopsys FPGA Compiler ?

By the way, Since we use the Synopsys SGE as our interface editor,
and if we must instantiate it each time we need, is there any  
IOBUF.sym that we can use ?

Thanks your answer ! 

Have a nice day. 
-- 
            Feng-Chen Chang - (035) 712712-56668 - jean@pds.cis.nctu.edu.tw
National Chiao Tung University - Computer and Infomatiom Science. Dept.
                Hsinchu, Taiwan 30050, Republic of China   
                       Parallel and Distribute Laboratory




Article: 1474
Subject: Re: Xilinx PLDMAP usage. Pro's and Cons?
From: rtr@rd.bbc.co.uk (Richard Russell)
Date: Tue, 27 Jun 1995 13:10:47 GMT
Links: << >>  << T >>  << A >>
Don Husby (husby@fnal.gov) wrote:

: Here we see the difference between the way things are really done, and the 
: imaginary world that marketing would like to see.  I have never done a
: Xilinx design that didn't require a lot of hand mapping, placing, and
: routing.  It's nice that they have all these automatic tools that work well
: with slow, simple designs...

Rather a sweeping generalisation, this.  I have never done a Xilinx design
which *did* require any hand mapping, placing or routing.  This includes
3195As with over 94% of CLBs used and clock speeds of 27 MHz.  With the
advent of the 'Neocad' place-and-route software the need for hand tweaking
should be reduced even further.

Richard.





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search