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Messages from 1525

Article: 1525
Subject: Re: aynchronous ripple counter
From: paul@xanadu.physics.indiana.edu (Paul Smith)
Date: 7 Jul 1995 21:23:20 GMT
Links: << >>  << T >>  << A >>
In article <3tgt37$9eh@dub-news-svc-2.compuserve.com>,
 <100611.1036@compuserve.com> wrote:
>Geoff Rubner <gbr@sn2.ee.umist.ac.uk> wrote:
>
>>Hi All,
>
>>can anyone suggest some elegant RTL-code for an 8-bit
>>ripple counter? Or know of a good VHDL repository where
>>I could get one?
>
>>I want to synthesise it onto Actel/Xilinx with Autologic (Mentor 8.2_5).
>
>>Thanks in advance,
>
>>Geoff Rubner.
>>gbr@sn2.ee.umist.ac.uk
>
>If you want to use Actel chips, you could probably do much worse than
>use ActGen to generate the module for you. The results will probably
>be much better than whatever you can get with a VHDL description. Of
>course, I might be wrong...
>
>Nacho de los Rios
>100611.1036@compuserve.com
>

ActGen only does synchronous counters.

paul@xanadu.physics.indiana.edu



Article: 1526
Subject: Please recommend good EDA program
From: kendal@interlog.com (Rolande Kendal)
Date: Sat, 08 Jul 95 07:08:54 GMT
Links: << >>  << T >>  << A >>
I would like a Windows based EDA package for under $1000.00.
I have no experience with them thus far.  My needs a board design,
FPGA, and simulation.

A Data-IO salesman was telling me their Senario package is 'the best'.

I would appreciate anyones recommendations of what I should concider.

Rolande					>Still look'n for God<



Article: 1527
Subject: Re: Q: Need help with MAX+plus reading EDIF
From: alexk@dspis.co.il (Alex Koegel)
Date: 9 Jul 1995 06:05:46 GMT
Links: << >>  << T >>  << A >>
In article 7o5@ibch10.inf.tu-dresden.de,  Joerg Wittenberger <joerg.wittenberger@inf.tu-dresden.de> writes:
>Hello out there,
>
>as the subject states I have trouble reading EDIF files with the
>Altera MAX+plus II software.
>
>The final error is
>
>Error: I/O error can't open file 'c:\....\proj.cnf'
>


Yes, I have encountered this before. In my case, the main EDIF Cell name wasn't
compatible with the project name. Easy fix: edit your EDIF design and change main
cell name (appears both at the first & end paragraphs of the file) to a name equals
your desin name.

Let me know if that helps...
Alex




Article: 1528
Subject: QLogic FAS246 info?
From: fugue@cicero.spc.uchicago.edu (The Right Reverend <name withheld by request>)
Date: Sun, 9 Jul 1995 16:59:59 GMT
Links: << >>  << T >>  << A >>
  Does anyone know where I can obtain programming/tech info on this
chip (the QLogic FAS246)?  

Thanks!

P.S. E-mail replies greatly appreciated.


-- 
  Mark C. Langston    | "History is a pile of debris.  And the angel wants to
 Dept. of Psychology  |  repair the things that have been broken.  But there's 
University of Chicago |  a storm blowing from paradise.  And the storm keeps
 Chicago, IL  60615   |  blowing the angel backwards into the future.  And this


Article: 1529
Subject: Alternative to low-power 22v10...
From: jkubicky@cco.caltech.edu (Joseph J. Kubicky)
Date: 9 Jul 1995 21:48:06 GMT
Links: << >>  << T >>  << A >>

Last week I posted an article looking for info on low-power
22v10-type parts.  Specifically, I'm looking to run stuff in
the low-MHz range.  Recently I realized (duh) that I can
just use a low-end Microchip PIC for what I want to do (basically,
simple waveform generation).  Costs are comparable and power
consumption will definitely be less than if I were to
use a 22v10 (say 5mA, although probably a bit more over temp)
plus an oscillator (lowest power oscillators I've seen 
are something like 20-25mA over temp).  I guess a discrete
oscillator built out of an HC04 (or possible inverters
configured inside the 22v10)  plus a crystal and some
discretes would reduce power consumption considerably
(for the 22v10 scheme), although this takes up more space.
The PIC makes for a very compact and inexpensive
solution, plus it only draws something like 6mA
over temp (including on-board oscillator) at 20MHz (translates
to about 4-5MIPS) and will work down to 2.5V VDD or so.

Jay Kubicky
jkubicky@cco.caltech.edu

PS: I think Motorola has a PIC-like part (HCK705 or something)
that probably has similar specs, but I generally go with
Motorola last as many of their parts seem to have LONG lead
times and I usually have to beg to get literature out of them
(I refuse to pay for it).



Article: 1530
Subject: Re: AHDL reference?
From: kgold@watson.ibm.com (Ken Goldman)
Date: 10 Jul 1995 13:26:57 GMT
Links: << >>  << T >>  << A >>
Russell Petersen <petersr> writes:
> neal@ctd.comsat.com (Neal Becker) wrote:
> >Anyone know where to find a description of AHDL, Altera's HDL?
> >
> 
> Try calling Altera and asking for their AHDL manual. It is pretty short
> and very understandable.
> 
800-800-3753


Article: 1531
Subject: Xilinx 5200 Software
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 10 Jul 1995 16:47:44 GMT
Links: << >>  << T >>  << A >>
Anyone know what version of xact you need for Xilinx 5200's?

John

_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD
UK


Article: 1532
Subject: FPGA as LCD controller
From: kendal@interlog.com (Rolande Kendal)
Date: Mon, 10 Jul 95 18:29:07 GMT
Links: << >>  << T >>  << A >>
>> Program an FPGA to sequencially read a block of memory via DMA, and then
>> write to the LCD driver/s.
>> DMA would never interrupt the uP, so it would just write to this 'video ram'
>> as it would any other.
>>
>This is a great idea, or so I thought.  I implemented it just for kicks a
>few months ago.  It works too, but my bus speed, and the average bus speed
>of the average project built by hobbyists is too slow to do this effectively.
>The DMA takes up too much of the bus from the processor.
>

I posted the following on the net:

 >I was wondering if there is such a thing as RAM that can be accessed randomly via
 >a parallel uP bus, as well a sequencially via serial line.

Got the following responce:

 There is something called Video RAM - VRAM - which is DRAM that
 has a separate shift register that can be loaded in parallel from an
 entire row of the DRAM array and clocked out independently of the
 parallel bus port.  This is usually used in video displays (thus its
 name) and raster printer applications since it makew available much
 more bandwidth for processor access.  All of the large memory
 manufacturers have these types of parts.

So how about accessing the VRAM as per normal on the uP bus, while the FPGA
sequentially accesses the device through the shift register, updating the
LCD display as it goes?

Rolande



Article: 1533
Subject: FPGA modules compatible with 6u VME ???
From: Jason Gomez <jason.gomez@msmail.mtv.gtegsc.com>
Date: 10 Jul 95 11:17:24 -0800
Links: << >>  << T >>  << A >>
Jason Gomez <jason.gomez@msmail.mtv.gtegsc.com> wrote:

 I'm looking for FPGA modules with multiple PCI mezzanine slots and
 compatibility with 6u VME form factor.  Does anyone know of vendors
 that might make this?
 
 Thanks in advance,
 
 Jason Gomez
 GTE
 email: jason.gomez@msmail.mtv.gtegsc.com
 



Article: 1534
Subject: BGAs, Flip Chip, COB, SMT, MCMs-courses this summer
From: course@garnet.berkeley.edu ()
Date: 10 Jul 1995 23:51:59 GMT
Links: << >>  << T >>  << A >>
UC BERKELEY EXTENSION ANNOUNCES

4 Summer Short Courses at the San Francisco Airport

1.  "TESTING ASICS, BGAS, KNOWN GOOD DIE (KGD) AND
    MULTICHIP MODULES"  August 2-4, 1995  (2.1 ceu)

    Topics covered: dynamic simulation at CAE, scan testing       
    testing laminates, environmental stress screening (ESS)

    Instructor:  Robert Hanson, M.S.E.E., AmeriCom Services,
    a test and manufacturing consulting company.  Mr. Hanson
    has extensive experience designing test hardware and 
    operation/test software.

2.  "SURFACE MOUNT ASSEMBLY AND FINE PITCH"  August 8-9, 1995
    (1.4 ceu)

    Topics covered:  introduction to SMT/FPT, SMT/FPT 
    components, SMT substrates, types of SMT/FPT assemblies,
    design for manufacturability, SMT process details, 
    typical defects and inspection, rework/repair, starting
    an SMT operation.

    Instructor:  Charles Hutchins, Ph.D., an independent
    consultant recognized worldwide for his experience in SMT.
    He has been President of the Surface Mount Technology 
    Association, and is the author of 30 technical papers
    and the textbook "Understanding and Using Surface Mount
    and Fine Pitch Technology."

3.  "BALL GRID ARRAY (BGA)/FLIP CHIP AND CHIP ON BOARD (COB)
    TECHNOLOGIES"  August 10-11, 1995 (1.4 ceu)

    Topics covered:  background, package types, properties
    and characteristics, chip attachment and interconnection,
    interconnection materials, printed wiring board design
    and specification, second level assembly, process control,
    reliability, future technology directions.

    Instructor:  Charles E. Bauer, Ph.D., Managing Director
    of TechLead Corporation, an engineering and management
    services company.  He has more than 17 years experience
    in electronics packaging, interconnection and assembly
    from printed wiring boards, ceramic hybrids and IC 
    metallization to multichip modules, micropackaging,
    smart cards and most recently PCMCIA design and assembly.
   
4.  "MULTICHIP MODULE (MCM) DESIGN"  August 14-16 (2.1 ceu)

    Topics covered;  introduction, materials, resistor design,
    thick film, thin film, MCM technology, CAD, thermal 
    management, assembly processes, screening techniques.

    Instructor,  Al Krum, M.S.E.E., a manager at Hughes
    Aircraft where he has more than 20 years experience
    in design, test and manufacturing of microelectronic
    packaging, including hybrids and multichip modules.
    He is the author of numerous papers in the field, and
    holds 2 patents.

For a brochure describing these courses in detail please
contact us as follows:

e-mail to:     course@garnet.berkeley.edu
fax to:        510-643-8683 (att:  Engineering)
write to:      Continuing Education in Engineering
               UC Berkeley Extension
               2223 Fulton St.
               Berkeley, CA 94720

please specify "microelectronic packaging and test courses"




Article: 1535
Subject: RE: Xilinx 5200 Software
From: randraka@ids.net
Date: Tue, 11 Jul 95 14:13:04 +500
Links: << >>  << T >>  << A >>
In Article <3trljg$9q8@yama.mcc.ac.uk>
John Forrest <jf@ap.co.umist.ac.uk> writes:
>Anyone know what version of xact you need for Xilinx 5200's?
>
>From what I understand, Xilinx 5000 series software will be included in the 
6.0 release scheduled for later this year.  Licensed users with current
maintenance can get the 5000 software now simply by requesting it.  

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930    FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital hardware design firm specializing in
obtaining the maximum performance from FPGAs.  Services include complete
design, development, simulation, and integration of these devices and the
surrounding circuits.  We also evaluate, troubleshoot, and improve existing
designs.  Please call or write for a free brochure.



Article: 1536
Subject: Re: Abel and connectedt tri-state outputs
From: alexk@dspis.co.il (Alex Koegel)
Date: 11 Jul 1995 09:18:18 GMT
Links: << >>  << T >>  << A >>
In article qo2@oban.cc.ic.ac.uk,  don@spva.ph.ic.ac.uk (Herbert Larbie) writes:
>Hi,
>
>Is it possible to design and simulate connected tri-state outputs using
>Abel5. For example, connecting to  an 8-bit bus using multiple 74HC373's,
>and only allowing one 373 at a time to access bus via the output enable
>lines. My code for the criteria defined, compiles but will not let me
>do a simulation, halts totally. I need to know if I am missunderstanding the
>software or I am doing something very silly.  The final design will
>implented using fpga's for Actel. Before anyone suggests it, I know and
>can implement a solution using Actel Orcad library and defining a schematic
>to represent the design.
>
>I have already waited a week for Abel technical support people to
>get back to me with a solution, so any help from anyone would be
>greatly welcomed
>
>
>Herbert Larbie
>(Forgive the typos)


Yes you can (I did numerous times). The trick is to understand that ABEL
treats bi-directional I/Os seperately - e.g. it "kinda" monitors the bi-dir
pin using 2 probing points: the output buffer & the input buffer.

The input buffer is treated as a regular input (left side of test vectors row).
The output buffer (tri-statable with some OE control) is monitored (and compared)
at the right side of test vectors. So, one can force logic to a bi-dir pin, as long
as its output is properly disabled.

The distinction between the two, is apparent at the sim results files.

One possible reason for your ABEL simulation to be stuck, is that there's
an oscillating combinatorial feedback through your design. Enter ABEL debug mode
for test vectors to verify you're not hit by a combinatorial feedback.

Usualy, ABEL will determine a stable output response after some pre-determined
oscillations for that specific output have been filtered (logically) out.

Good luck,

Alex Koegel
DSP Communications




Article: 1537
Subject: FPGAs for video coding
From: s.cozens@shef.ac.uk (Saul Cozens)
Date: 11 Jul 1995 12:39:09 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm looking for sources of information, papers, etc. on the subject 
of using FPGA based computation units in video coding applications.
If anyone out there has any suggestions I would be very grateful to
hear them.
Either post replies or email me direct. I'll post the results to the
group in case anyone else is interested.

Cheers

Saul


========================
s.cozens@sheffield.ac.uk




Article: 1538
Subject: JOB AD (UK): Research at Oxford University in Computing
From: Jon Saul <jsaul>
Date: 11 Jul 1995 17:02:56 GMT
Links: << >>  << T >>  << A >>
[from http://www.comlab.ox.ac.uk/oucl/jobs/hwcomp-ro.html]

Research Officer, Hardware Compilation Group, 
=============================================
Oxford University Computing Laboratory.
=======================================

The Computing Laboratory is a full academic department of the
University and at the present time there are twenty-seven academic
staff, nearly fifty research officers and sixty-five doctoral
students, engaged in teaching and carrying out research in computing
science and numerical analysis.

The Hardware Compilation Group works on all aspects of the compilation
of programs to hardware. Our interests include automated
hardware/software codesign, developing appropriate programming
languages, compiling to hardware, provable correctness, designing
reconfigurable computer systems, and implementing challenging
applications such as real time video processing using our own
technology.

We are looking for a Research Officer to work on several aspects of
the design process, and to apply it to the compilation of signal
processing problems into hardware. This will give the opportunity for
the successful applicant to contribute to our hardware compilation
work in general, as well as working on specific aspects of compilation
for signal processing.

Our work is primarily about making computer programs go faster by
replacing the computer with something better. The "something better"
is application-specific hardware. Such hardware can operate many times
faster than a general-purpose computer in many applications.

The novelty of our approach is that we believe that much hardware can,
and should, be designed automatically. To this end we build compilers
and systems which allow programmers to write programs which are then
automatically turned into hardware. By using state-of-art FPGAs (Field
Programmable Gate Arrays), the construction of the automatically
designed hardware can also be automatic. As an example, new
application-specific hardware, and even complete microprocessors, have
been designed, implemented and worked within five minutes; by simply
writing the program you want to be executed. We are working towards
the day when computer users will neither know, nor care, that the
command they just executed might have brought new computers into being
which existed only for the duration of the computation.

This government-funded project will suit someone with a good first
degree in either Computer Science or Electronic Engineering. The
successful applicant will have either a higher degree or equivalent
industrial experience. The work is essentially interdisciplinary, so
we are looking for someone with breadth as well as depth. Previous
experience of parallel programming, SML programming, or digital
hardware design would be useful. The person appointed will be working
as part of a growing team which is working on a broad range of
topics. This means that there is scope for orienting the work towards
the skills and interests of the person appointed.

There is further information on the sort of work which might be
involved, on the Hardware Compilation Group's home page.

Salary will be on the experience related RS1A scale, currently #14,317
to #21,519 per annum (# = pounds sterling). Further details are
available by telephoning +44 1865 273898.

Applications, stating the post being applied for, should be in the
form of a full curriculum vitae together with the names of two
referees. They should be sent to arrive before the closing date of
14th July 1995, to The Administrator, Oxford University Computing
Laboratory, Wolfson Building, Parks Road, Oxford, OX1
3QD. Alternatively, they may be sent via email to
Mike.Field@comlab.ox.ac.uk

Oxford University is an Equal Opportunities Employer.



Article: 1539
Subject: [Q] Comments on Synario
From: amar@cup.hp.com (Amar A. Kapadia)
Date: Tue, 11 Jul 1995 17:03:32 GMT
Links: << >>  << T >>  << A >>
I read about Synario on Data I/O's home page. What has people's experience
been with this tool set for FPGA design?

Specifically, how good is their VHDL synthesis? Do they embed someone
else's synthesis engine or is it their own? Also any word on whether
they will support ORCA?

Thanks,

Amar Kapadia
amar@cup.hp.com


Article: 1540
Subject: I want to work in expert system. Help!
From: Evgeny V. Vlasov <udjin@int.khakassia.su>
Date: Tue, 11 Jul 95 14:28:39 -0300
Links: << >>  << T >>  << A >>
                      Здравствуйте Все!
    Меня интересуют экспертные системы в плане использования.
    А именно для подключения  их  в систему управления произ-
водством  (если  я их названия неправильно пишу,  то пусть их
разработчики на меня не обижаются):
    1. ARTEMIS - разработала КОРПОРАЦИЯ ЛВС где-то  в Москве,
а информация  по словам прошла о них в PC MAGAZIN N2 1994год.
    2. 3 MAVERA - говорят о ее совершенстве.
    3. PRO-EXPERT - тоже что-то интересное.
    4. TIME LINE - хорошо бы получить и поработать на ней.
    Говорят, что обзор этих систем был в QWERTY N11 за 1994г.
    Короче говоря, те у кого эти системы есть, просьба помочь
мне, чтобы не изобретать снова.
    Я думаю, что ВЫ откликнетесь  и поможете найти концы этих
или иных систем, чтобы дать их, поработать и подключить в сис
тему управлением  производством.
                                С уважением ко ВСЕМ, Евгений!


                      How do you do All!
    I is interested by(with) expert systems in the plan of use.
    Namely for connection them in a control system of manufacture ( if I of
their name incorrectly write, let their developers on me not обижаются ):
    1. ARTEMIS - corporation ЛВС somewhere in Moscow Has developed, and the
information on words has passed about them in PC MAGAZIN N2 1994.
    2. 3 MAVERA - speak about its perfection.
    3. PRO-EXPERT - too something interesting.
    4. TIME LINE - well to receive and worker on it.
    Speak, that the review of these systems was in QWERTY N11 for 1994 Shorter
    speaking, those at whom these systems is, request to help me, not to
invent again.
    I think, that you hope me and will help find the ends of these or
other systems, give them, worker and to connect in a system by management
of manufacture.
                                Yours faithfully to ALL, Eugeny!

=============================================================
Russia, Аbakan, Taras Shevchenko street, house 107-2,
For Vlasov Eugeny.
E-mail: udjin@int.khakassia.su
г.Абакан, улица Тараса Шевченко, дом 107-2, Евгению Власову.
=============================================================



Article: 1541
Subject: EP330 driver for APLUS
From: Wout.Klaren@3t.nl (Wout Klaren)
Date: Tue, 11 Jul 1995 20:59:26 GMT
Links: << >>  << T >>  << A >>
Does anyone know how to program a EP330 with APLUS. 
As the EP320 is no longer availlable I want to use the old APLUS
software package to program the EP330 from Altera, but it doen't
recognise it.




Article: 1542
Subject: info
From: "avider" <avider@atmel.com>
Date: Wed, 12 Jul 1995 00:26:02 GMT
Links: << >>  << T >>  << A >>
  Hi:
  
  Please send info on how to get onto this mailing list.  I have gotten your 
  address from an FAE here that thinks we can benefit from seeing the 
  postings.
  
  Ami Vider
  Strategic Marketing Manager - EPLD
  Atmel Corp.
  e-mail:  avider@atmel.com



Article: 1543
Subject: Exemplar users in Australia (or elsewhere)?
From: Mike Reynolds <reynolds@ozemail.com.au>
Date: 12 Jul 1995 04:19:04 GMT
Links: << >>  << T >>  << A >>
Fellow Designers,
    I'm interested in trading notes with other users of 
Exemplar CORE and/or Galileo.  If you use Exemplar and 
would be interested in bootstrapping yourself and the 
rest of us please let me know.

    I am an independent consultant based in Perth, 
Western Australia.  I carry out ASIC and FPGA development 
work for local, eastern states and overseas clients.
Cheers,
Mike.


Article: 1544
Subject: Flex 8000: Locking down pins
From: musall@fstop.csc.ti.com (Ed Musall)
Date: 12 Jul 1995 16:08:36 GMT
Links: << >>  << T >>  << A >>
I am presently working on a couple of Altera FLEX 8000 designs targeted for
8820As.  I have captured the designs but I haven't verified them yet.
One of the designs utilizes 50% and the other is at 60%.  I was hoping
to go ahead and lock down the pins and procede with the board layout but
I am apprehensive about the Fitters ability to succede when I make changes
with the pins lock down.  Please comment on my situation if you 
have experience with the FLEX 8000 devices.

Regards,
Ed

Ed Musall                       Phone:  214-995-8533
Texas Instruments, Inc.         Fax:    214-995-1629
Digital Imaging Products        email:  musall@ti.com
Dallas, Texas                   MSGID:  EDMU






Article: 1545
Subject: Intel FLEXLogic
From: lis@asic.ict.pwr.wroc.pl (Jarek Lis)
Date: 12 Jul 1995 16:16:18 GMT
Links: << >>  << T >>  << A >>


Long time ago I heard about Intel Flexlogic, as a good chip for hobbyist.
I know it was sold to Altera. 
Question:

Does Altera still sell them?
Are tools for programming them still freely avalaible (where?).
When I can find short description of them?


Jaroslaw Lis

+------------------------------------------------------------------------+
| lis@ict.pwr.wroc.pl         | Institute of Engineering Cybernetics     |
| tel  48-71-202636           | Technical University of Wroclaw, Poland  |
| fax  48-71-203408 or 517398 |                                          |
+------------------------------------------------------------------------+



Article: 1546
Subject: Re: Intel FLEXLogic
From: devb@elvis.vnet.net (David Van den Bout)
Date: 12 Jul 1995 12:07:03 -0500
Links: << >>  << T >>  << A >>
>
>Long time ago I heard about Intel Flexlogic, as a good chip for hobbyist.
>I know it was sold to Altera. 
>Question:
>
>Does Altera still sell them?
>Are tools for programming them still freely avalaible (where?).
>When I can find short description of them?

Yes, ALTERA now sells the chip under the part number EPX780 for the
80-macrocell version.  They also have a 160 macrocell version that
used to be called the 8160, but I don't know what they call it.

You can get the PLDshell programming tools by calling ALTERA at
(408) 894-7144.  XESS Corp. also keeps a copy on our ftp server
at ftp.vnet.net in directory pub/xess/pldsh.

You can get a description of the EPX780 chip and the PLDasm
programming language from ftp.vnet.net in directory pub/xess/hyperdoc.
You can also try the HTML file:
	ftp://ftp.vnet.net/pub/xess/hyperdoc/html/fpgawk2.htm

Our FTP server suffered a crash a few days ago.  It may take a few more
days before you can get to any of XESS Corp.'s stuff.  ALTERA also
has a web site at http://www.altera.com.  Maybe they have the information
you want there.


-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 1547
Subject: Dog Food Drive For Joe Costello
From: jcooley@world.std.com (John Cooley)
Date: Thu, 13 Jul 1995 09:09:31 GMT
Links: << >>  << T >>  << A >>

 During the DAC 5-CEO's-Act-Like-Professional-Wrestlers panel, Joe Costello
 (CEO of Cadence) blurted: "We're stuck in a fixed-pie model.  Have you seen
 three big dogs hovering over one bowl of dog food?  It's not a pretty
 picture."  Inspired by Aart De Geus's (CEO of Synopsys) flip reply of: "If
 you think of yourself as a dog, you deserve dog food!", I'm starting a dog
 food drive for Joe Costello!  Mail your cans of dog food to "P.O. Box 6222,
 Holliston, MA 01746-6222" or print this, mark how much & what you want
 bought with a check to pay for it and I'll personally buy & deliver it to
 Cadence Chelmsford in August.  (I believe a good joke is worth the hassle!)

 CANNED DOG FOOD:                       DRY DOG FOOD:
 __ Alpo "Chunky Lamb"   $2.00/3 Cans   __ Purina Dog Chow   $6.00/10 lb bag
 __ Mighty Dog "Chicken" $3.00/5 Cans   __ Kibbles'N Bits   $11.00/20 lb bag
 __ generic horsemeat    $2.00/5 Cans   __ generic beef      $7.00/25 lb bag
 __ Ken-L Ration "Beef"  $1.00/3 Cans   __ Gravy Train       $9.00/20 lb bag
 __ Skippy "Smoky Beef"  $1.00/2 Cans   __ Pedigree "Lamb"  $12.00/22 lb bag

 Clearly hand print how you want to be listed on Joe's "BON APPETIT!" card:

    NAME    (or "Anonymous"):___________________________________

    COMPANY (or "Anonymous"):___________________________________

 All money will be to buy dog food; what Cadence Chelmsford doesn't take will
 be donated to the Framingham Humane Society.
                                               :^)  - John Cooley
                                                      the ESNUG guy

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3567 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1548
Subject: AT&T FPGAs - Opinions needed
From: grcook@bhars10a.bnr.co.uk (Gary Cook)
Date: 13 Jul 1995 09:40:57 GMT
Links: << >>  << T >>  << A >>
Hi,

Can anyone give me any feedback on how AT&T FPGAs compare with the other major
vendors, such as Xilinx and Altera ??? Email me direct if you want.

Thanks,

Gary Cook.

--
PU66 Cad Support Prime     Tel:(44)1279 402615       
BNR Europe Limited         Fax:(44)1279 441589
London Road                Email:grcook@bnr.co.uk
Harlow,England  CM17 9NA.          


Article: 1549
Subject: Synopsys timing simulation of two XC3000 chips
From: kugel@mp-sun6.informatik.uni-mannheim.de (Andreas Kugel)
Date: 13 Jul 1995 12:37:44 GMT
Links: << >>  << T >>  << A >>
I compiled two xilinx xc3000 designs with synopsys. the chips
are connected together as master and slave. I'd like to have a
common testbench for both designs.
in the testbench I instantiate two components MASTER and SLAVE
and configure both components.

vhdldbx cannot load both sdf files, generates lots of errors
with the options:
-sdf master_vss.sdf -sdf_top /testbench/MASTER -sdf slave_vss.sdf -sdf_top /testbench/SLAVE 

is this the wrong syntax ? (it works with ONE component that way!)

all hint welcome

-


--------------------------------------------------------
Andreas Kugel                
Chair of Computer Science V       Phone:(49)621-292-5755
University of Mannheim            Fax:(49)621-292-5756
A5
D-68131 Mannheim
Germany
e-mail:kugel@mp-sun1.informatik.uni-mannheim.de
--------------------------------------------------------





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