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Messages from 1625

Article: 1625
Subject: Multiplier implementation...
From: kadamby@caip.rutgers.edu (Vijayasimha Kadamby)
Date: 6 Aug 1995 02:58:40 -0400
Links: << >>  << T >>  << A >>
Hi!
  I am looking for detailed information on implementation of multipliers on
AT&T's ORCA.  
  Please post the information on this newsgroup or email me at
  kadamby@caip.rutgers.edu

Thanks!
  -Vijay


Article: 1626
Subject: Re: Double side SMT
From: Jozsef Ludvig <ludvig@mp-sun1.informatik.uni-mannheim.de>
Date: 6 Aug 1995 07:57:15 GMT
Links: << >>  << T >>  << A >>
We are currently designing a double sided PCB for our Enable++ project. This
machine is a universal FPGA processor. Its FPGA-Matrix consists out of 16
XC4013 FPGAs (240 pin QFP-cases with 0.5mm pitch), 8 I-Cube I240 FPIDs (304 pin
QFP-cases with 0.5mm pitch) and 96 synchronous SRAMs. There are 11 more XC4005H
(240 pin QFP) and 16 dual-ported-RAMS on the board as IO-Interface and control
logic. Since any I-Cube FPID is connected to almost any FPGA there are some 
4000 nets which connect all parts to some hypercube topology. This looks like
quite a mess. Since we want to operate the board up to a clock of 50MHz and 
no correct termination of lines is possible (Xilinx won't drive the termination
currents!) we tried to place SMDs on both sides of the board to keep lines
short: this works but involves some extreme problems with routing without
beeing to advantageous! This fact has a simple explanation. If there is no
topology which allows to connect most of the pins of two QFPs which are located
side by side on the outer layer then one via is needed for every pin to connect
the SMD pad to the inner layers. The smallest possible via has a drill diameter 
of about 0.4mm (for a 20 layer board with 360x400mm size) and a minimal spacing
of 1.0mm (There is not much to optimize on these figures if you don't have
plenty of money and an extremely good and willing PCB manufacturer!). Spacing
is needed between the vias to get through with at least two lines which
computes to 
a typical via grid of about 1.8 to 2.0mm. Calculating the free area under a 240
or 304 pin QFP it comes out that there is enough space to fanout every pin
inside the case area. And this is exactly what a good autorouter like Specctra
will do: it converts the SMD-case into a virtual PGA- or BGA- (Ball Grid Array)
like structure. This works perfectly with Specctra for single sided boards. 
Since the area inside is not sufficient for two SMDs placed on both sides of
the board top on top the router has to use the outside area, too. And here
trouble starts: First SMDs can't be placed any longer end to end. Plenty of
room is lost 
and actually there is no area gain of 2.0 but only 1.2-1.5 or something like
that. 
Secondly no via under the SMDs can be used as a test point. It is extremely
difficult to perform tests with a logic analyzer or a scope on fine pitch SMDs
directly but it is easy to solder a little test pin to a via! 
The third point is about power/ground lines. 
In the single sided version decoupling capacitors can be placed directly under
the QFP pads, there is no space for this if a double sided board is used. 
It is recomended that QFPs are connected with the shortest possible lines to
the power/ground-layers. The Specctra router is definitely not capable of this
for double sided designs. Since it has to use both directions for fanout,
inside and outside, it will put power-ground vias very close to the pads in the
first step. After this the power-ground configuration has to be protected, the
router isn't allowed any longer to shift any vias or lines. But then some pads
can't be reached any more with lines without violating design rules. In the end
there were some 100-200 errors of this kind on our board. The only possibility
left was to place power/ground vias by hand. This took us a whole week but
worked perfectly. 

Conclusion: there is not much to gain by double sided placement of fine pitch
QFPs. One should use it only if it can't be avoided. This is at least my
personal feeling about it and I believe it to be definitely valid for some
globally connected circuit topologies. It is definitely wrong for designs with
local connections of some symmetry. 

If there are further questions I will be glad to answer them. 

Jozsef Ludvig 
Lehrstuhl fuer Informatik V
Universitaet Mannheim
e-mail: ludvig@mp-sun1.informatik.uni-mannheim.de



Article: 1627
Subject: Re: 16 bit computer on fpga's
From: klee@mistress.informatik.unibw-muenchen.de (Herbert Kleebauer)
Date: Mon, 7 Aug 1995 07:36:53
Links: << >>  << T >>  << A >>
In article <3vpuc5$4b6@wsiserv.Informatik.Uni-Tuebingen.De> schmidt@ti-ibm06.informatik.uni-tuebingen.de (Marco Schmidt) writes:
>From: schmidt@ti-ibm06.informatik.uni-tuebingen.de (Marco Schmidt)
>Subject: Re: 16 bit computer on fpga's
>Date: 3 Aug 1995 07:37:41 GMT

>Peet Badenhorst (pbadenh@firga.sun.ac.za) wrote:
>: About a month ago I think I read about somebody that built a complete 16 
>: bit processor with vga display and keyboard driver in 4 Xilinx FPGA's. 
>: It came with GIF's showing the casing and layout. I seem to have lost the 
>: files.

>: Can somebody please point me in the right direction?
>: Please e-mail me at pbadenh@firga.sun.ac.za
>: Thanks Peet

>please post !

>Thanks.

>Marco


It is not only a processor, it is a complete computer. 
You can download the following files (and some gifs) from:
mistress.informatik.unibw-muenchen.de  /pub/xproz
Only xproz.txt is in English, all other is in German.



xproz.zip : Documentation (Word for Windows) and schematics (WORKVIEW)
            for a computer built with only 4 XILINX FPGA's
            1. FPGA:  16 bit CPU (XILINX 3090 FPGA)
                      - 128 kByte memory-address
                      - 128 kByte i/o-address
                      - 5 Interrupt levels
                      - 3-address instructions
                      - 0.3 MIPS
            2. FPGA:  graphics controller (640x400)
            3. FPGA:  RS232, parallel port
            4. FPGA:  keyboard interface, SCSI controller, timer

xproz_ps.zip: Documentation and schematics in postscript format

xass.zip:  Assembler for the 16 bit cpu

xmos.zip:  Multitasking operating system 

xproz.txt: short ascii description of the 16 bit CPU


            
Herbert Kleebauer



Article: 1628
Subject: Xilinx xc4013 routing problems ??
From: makkarm@ipoint.vlsi.uiuc.edu (Masood Makkar)
Date: 8 Aug 95 00:52:26 GMT
Links: << >>  << T >>  << A >>
Hi fellow FPGAers
 
I'm a fairly new user of Xilinx FPGAs.
I'm having a few problems with my current design using a Xilinx xc4013
FPGA. With only around 84% CLB utlilzation and under 40% flip-flop
utilization, the XACT software is crashing on routing. It always ends up
with 70 unroutes.
 
I'm sure I'm not pushing it to more than available routing resources when
the CLB utilization is not filled.
 
Handrouting all the signals is the last thing that I'm opting for.
 
Any help is well appreciated
 
_ Masood Makkar _
 
email :- makkarm@ipoint.vlsi.uiuc.edu



Article: 1629
Subject: Post: VHDL Source for 5x5 Image convolver in ORCA FPGA
From: jbm@speedy.login.qc.ca (John B. McCluskey)
Date: Tue, 8 Aug 1995 03:16:25 GMT
Links: << >>  << T >>  << A >>

Due to popular demand, I am posting the VHDL and Neocad hard macros for the
5x5 image convolver design implemented in an ORCA 2C04 FPGA.  It uses a
pretty damn fast system clock of 80 Mhz.  It needs a little more work in the
coefficient department, because the lookup tables don't have a 1 to 1
correspondence with the filter taps, but need to be generated by a utility
program from the filter taps.  I haven't gotten around to writing the
utility yet... (uuencoded, gzipped tar file follows at bottom of this post.)

Now that I've paid my usenet dues by posting something semi-useful, I'd like
to mount my soapbox and launch a stupid question or two.

Here's a question for the VHDL experts.   I really like using functions 
and procedures in VHDL, probably because it's more "C" like and I find it
easier to hide complexity in something that looks like a function call.

BUT, there doesn't seem to be any simple mechanism to instantiate technology
specific hardware such as RAM cells in a procedure or function.  I'd like to
define a common set of procedures with different body definitions for each
technology targeted, and use a procedure in the main entity to invoke a
technology specific component (the dreaded hard macro instantiation).  The
sad fact is that no VHDL compiler will synthesize the odd technology cells
like RAMS.  

Everyone is familiar with the typical dff() procedures that make it easy to
instantiate registers, but it seems to be absolutely forbidden to invoke a
component inside a procedure.  Even if it is something as simple as a 1 to 1
mapping of signals from the procedure arguments to an instantiated component,
you can't do it, because procedures are sequential environments.  (Is this
in the LRM?)  

Even cheating and using a C preprocessor to expand predefined macros into
1 to 1 component instantiations doesn't work, since each one needs a
unique component label.  Humphhh!

The upshot is that synthesizeable VHDL code sprinkled with technology
specific cell instantiations is non-portable, and difficult to simulate. 
Does anybody have a better idea? 

John McCluskey
J.McCluskey@ieee.org

-----------------------------cut here-------------------------------
begin 644 convolver.tar.gz
M'XL(`/'+)C```^Q<6W?;2'*F[-G9'>3FG22;R[[TT6;7T@D%HW'AS3,^H4C*
MED>6K8MW['E1(+!%XA@$&`"4K'G9?Y)S\AORGH?\E"3GY.0M;WF<5'4W@`8)
M2IRQ97MV#5NX==775=75U=4`V/J]PT&W_V10N\&-&D;#MDF-X&;,'0FA#C4(
M:1B4.K9MVB;<,:CMU(AQDT)EVRQ)W9B06AQ%Z55TUY7_2+?^C)$T(M-H.@O`
M#D,V<<-AG>P2=P(WD]0/1R0=,[(Q>,TF4R#9)+]]U-\C232+/4:\:,C(6103
M5W->.*1%3OV4^!-WA$7A>12<LQBNIP&;L#!E0^*'Q`W)T\->EY@]PR8[SQYV
M=4*.QWY"+MR$#*.0:7!TR10L?D;@/P!Y;)J";(D_"NO`/R1C(`FCE)PR%I+$
MGX#PB.ZFP'C*QNZY'\5N0*)8&T$!"=@Y"Z":#>1-Q[.$0'6!_XH%EZ@]U)"Z
M(-GI;)3HFR`,(_LL\ERL)QZ2B>O%4:*Y,2-ND$2@@Q?,A@S,!%)<L"`@7.!D
MXL+IU/5>H?H`.V1G?LA0$8\-9S%+T%):<AEZXS@*(Y#B(O93ML5"]S0`,P;^
M%';1-.$&049VQF(&VI,S'P@VXFB6LE@#<9,T!H'3A/R&C"(0:A,52E@JV@)L
M/!I!?8E_SDC+(4\>?4N\(/)>D;.8_=,,$"_KH&RJ8<N>LB0%FX#I/&3TTAFH
M<0FWX7SL@^&&9.,BBA,L3QB)L$53\(6Z4"P!&31HZ!24YE*X("58N47U%E:L
M$TU#943KD5G"L.7()`)K0JTA,47K)-C4033R/:@ZO<!V+0S"&UUSSR-_F!"T
M`KHEF&$$LOL1--PE`..]PZ=/CJ!]DI1!XP'@81>NT2:H:1!%KV93+45KHXTW
M.#5XW-V4A`ST1#^(HP`\(V3))E!HL#V.QB%YXO6"6?**7<*UGE_\@\\8TZ-X
MI&GONQ__T$V_YWH>-0,]G'@W5<<U\=]IV!#_G6;3M&QJ-BR(_]1P[(_Q_UUL
M__LOM;7:I\(':FZ:FIYAR*-=.S*-5LT"@GO_\^__RLD_Z?9ZCW9KW\%6>[;S
MO,;/UJ#@OWJ[^T^>O^C`@1SN/GNV-WCRM#_H=/M]TMO[BI?L?45Z`SRCY.BP
M#R>T<S@X&AS+*[-T9<FKG1VX,#H[XH1F)V9V8O&3O>YQ[Y'5^=5.?F&J%U2]
M,/B%J,7(Z^32[@Q.C@9[@]XQX9="#[('I2`U'&IKH/[>TPKU_T.J;_R>*W_\
M]-D?;N,/6>!>5JC_SV^N).U\W<^4R\XL<;:2>E*'HY?[/2'^CIV);M10QE_^
MW='NP_WNW@D5"M1NP3_8?O?=[[[KFC(8X,77?;@"CHS>K*"G)7I:HK<JZ(T2
MO5&BMP7]FD)_H-)OE\F="G)5G.VR-(T*<E7;[;*RS0IR2R6W2N2M$OD:4O2>
M/C]6&*!'E#C:N74^R3GVOE(9\`H;[%9^A=BW\ZO;!1@MM^6::NNU*EM3<Y&!
MMU_.T2V;CUH5-9BE&LH&I'8%@U5B*)N0.HLV/%!UF&M_VJB@5S68<P#:K*!7
M-9CS`%K1I@>J`G,N8!HE^ENJ_+<JY#=I!3U5Z<ORFV8%O:G2SW57JX+>4NGG
MY"_ZWV>9GY7HNX;BC^@>.2PZPNW\`G@^R2ZXW_VDN`*N3XLK8/MI<05\/U/$
M<7+_N9V)PVGR#M(5\F?!Q.("Y>P5_;WHD;<KXUO906XO&'B^"YNM"@:U!7&L
M*#&TJW12@U;&(3R,7R'T+[`\"P^R8\O8*SNA[%J<`[@%S9J@61,T:Y)&.J64
M5&HH6GI-E*V)LC51MB;*;HFR6Z+LEBB[!64HU\]K7;MVI]9U<-?`71-V>_W:
MYRCN'13V#HIZ!P6]4SNP:_]8.W!PU\!=$W<&[BCN3-Q9N&OAKLT+1#&6KWU:
MB^#?+VM_4LNV-7F\)8^WY?$3>?R)/'XJCS^5QY_)XV?RF,W>_D@>_U@>LYK^
M5![_3![OR.//Y?%S>?QS>?P+>?Q+>?R%//Z5//ZU//Z-//YM+O=7H-)W_[=6
M6^.[0L,;V_C\KW63L[]KYW^6U6SP^1]M`"7%^9_1@+CZ<?[W#K9\_M>Z8O;W
MWW=$S[BU;/;WGW("L&W_/N?_RR9__W9#D[]WIACH\'DV6A7Y#(^F"REP:?S%
M(>;60BZOYO[;*N]\\N=4T%\U%VE4T%\U%VE6T%\U%VE=,UN8RX[;U\Q%NG.I
MJU%!KZ:ZW;G4N"*]KYXLS.?W5TQ(MNW*!']INMNMSN^7IM/S$XBJ]+XTX:A.
M[U6=MZ^</S0K&*Z<H;0J&&B)84Z%=@7#5;.L;$J@,L@,K3:7[_'$0>HGI9:R
MR!JR]LXR/$&[)FC7!.V:I)7MEJ5V,M&3J=V2#*^/"5L?4[<^)G%]3.=$9L>S
MN#ZF;7U,X/J8RO4QJ1-I6R-/Y>PE61SD:U_!O\\_P'RMR+/^X#?]WID?I/HT
M/KNY.JY[_VLX(O^S#<=I-!R\TVPT/N9_[V([ZCT:/.D>[_;(T7'W\)C<UWY%
MHMB;N-,.(><L3O#UV@Z^T8LO25,WR-86.9XQ\G@6$K-)J-,QFQV[36B[[6A:
M@3;8[P/6SN'@X/E@O_>2[$,^L@Z1Y<0/TW72<G2#;_S5Y'WMV>'NT\/=X]UO
M!H(0\A5C'=R@NH@N+S*7%UGKQ%Y29*\3:TF1LQRPL;RH*8N>'T&B]73_X=[N
M?DFS)25T:8FYM,1:6F(O+7&6EC26EC2QY'U[Z\?M;6\R_J<7\<W5<77\IPW3
MY-__&(9I.K9-^?M?X^/\_YUL6V]YT_99U.OVR?%AMS>HD]\NCB!:+YI>QOYH
MG.*@0;=PY,`/."3C;NCIA'2#@'":A,0L8?$Y&^J:UA??D.#',!WQZ<")Y>BA
M-]2>E3^5Z9`LJP&><]]C]63*V)`SR<<;=4L[9-,H3L7G)[P(QKO3*&%0)1;4
M2>!/?/RL*(TPG,/I)"%3%BL?YFAOW7ZPO77,PCH=LNJ03)2M25M2^\2+8OSP
MB5*2@G'"$6%Q',4)&;*4>2FVTEN77AM@%:+!V[IIMD*L+G`OR<[NWK%QTJ7W
M^),9;";USJ-=PEY[T.R)H@RE>K-AYPC%IU3@!HE*2"RT1\B_JII-"7XWY<?\
M*S:RD4:I&Z#R+0&VB?YKZ#:>:Q+C\-X.[/N\EH7M"*RY</.0B8_J,B$.45R]
MR84HMOZ.CL^30%<X.S!5@#ES;)S%T83(!MY442V=<BN680%,H';I(NHWV\^/
MOC`?J"BV-%`9!9@%"CYX6":;"@-V*\-DO`#3@]/=_2H5BT<>V!P+6L*6^X_"
MGKD/V6A0O?5K\;U9G5@MW?PU_ZZ,;=;Q@S3^&9KX+$U?\#^KY'_V@O_9[\W_
MG/;-^]]./_,_.#M8\!1[5?^SRIXCP`1JUUA$Y?Y'K_,_P2Q0%OW/7LW_,EZ`
M&?0K_,]^,_^SWM#_J/G!QC^[]:[C7T6D6LW_N!7+L`=9Y%KT/V-%_Q/,'W3\
M$XJC_[55_Z.K^A]MEOW/6O`_Z[WYG_$._&_G81[_'NH'E@HP9XZK_,]HSOF?
M`!.HW851W1+^9UT;_SBS0%GT/VO%^/>PB'\/*_S/>A/_$^X#_F>BRV7^UT1G
M7-'_G-:'.OY:[7>0_Y7'WP5/67'\-9S6XOAK9N-OQ:B^6OXGF#_D\5>X#_<_
M4_6_UDK^A][3,G+OP<=O*.9>]_@$[6,_>"./,W3S6H\#-$=Q.9,V;M[E'N4A
M#\[*0RZWP')'<W3::)1=1$``UO'AKC[8U0W]N,!RRH)8BB`*N<K\5!9O/]\Y
M/MG=S]KAQ+'+#M^@]B(4#QF#1_K7?77$+U"^AVOEGD$V3$=W<M=JVGBQ2FAK
MZ6WJ5*9V$,C>=VI''7KS?M;+4SLX.ZA(PG+EEWN<J;>X%<NP!UE2UET8L&5J
M9Z^2VED?<&J7N0^$-DM-[1HKIG;@/0V</WXPH<UH.S_RT&9^O]!FED*;61W:
MG`<G=JL<VNRVM0A5A#95J0+E^X4VX1D\M#75T&:M&MJ:[68IM)DG?93#>)!%
M-O-]13;#LM[!I/5Q/FE]7#%I**QQ56!K<!N64>6<X;&^O0ST^CD#9Q8HBX'-
M7#%G>USD;(\K`IOY)H%-.`\$-EM]9N*L^,P$PTK+4@.;\9X#&WT'C^D>Y=.$
M1_./Z;@%ECN:#8Y&YP);7PUL7=U2`QN])K`)<I6Y,K`U(;`9Y<#6:IN+4$5@
M4SV^0/E^@4UX!@]L;36P735F?NW&(30K.%>+)WWXOL1/^"^,)^YK?S*;%#^S
MEK\]AN+BG1%`:%3]<3?^D'W"4KQ_+%ZJ)+/)Q(TO._,O4W("\=:E@^]AR!&^
MD^D0$UQ`TWK*;\,]_EMM?'DS==-Q4B<&"5DJ?DQ-6H:)?ATR#W]!G9"-5@-C
M.^?!GW+CBZA>S/C/ZI]$(7D\"_`EF-'NF.V.X8@//G[P2YTEVX_W=]0_UDV^
M_S\?#V^NCJO?_UNF8])L_0_Q6W!J-)WFQ_?_[V+;VB+9RA[D+'#/(5Q5K^]!
M<'V/TLH>&(?0>5@,<8!<^.E8KO_A1>SLS/=\AD&(QQI^>Q;BVWN^!LATEF:+
M7+BQ-_;QW?$LQK?IQ/5PL8^$X#<!*4O$DAZI/V$B;&'=+$Y%N,UH(-I%<)&P
MV'<#K`N!(`PR=\(!6@9Y`G>3>PD#_F&=7/HL&*+\`#V&0#\:@T2X7@1$N(D?
M!!`1$4(H.N,!4O(*/=4E3+8L_*$$A-@X195PT)<CAA?-0BX*A/^F09[M/+^;
MD$A4!!5S2EZG41>+DHS\<R%4&$&4AU*^>`F'`4)$LO`%/=[-S,>_:Q"KF8AO
M%2#%2/G:(='4!4+\^$(D,5`3%GAN'%\B%%^I)>3W1/LD8_^,+ZP!33#C*ZK`
M$".LCD1#'RSJG\X6(!&L!<8/H!$)-K$;P'`"U[2.=\TZT75]DUR,?6^<+[&!
MB,)YP%BN:(MPB%#0:D-N)"';*(A.P1)0-714L,;I+)&KE40!UIBH4#%+9@&X
M%N`@U#;SW%F"ZXRP)*-)<`D2,'&N#BX;$T.CP@@,;>9.P7*N-ZXKL,(55)^.
M&8$3R/2"RVSQ&"9<0UKT'"!Q@1>QY`B12XX@T&Y((J"(,Y'ENBA0^S@:2M7R
M!7,(-$/J3P.?Q5N04^0ZU!$)ZPEGDU,`08<:#AG_#F/*0L"1UI.5J-)S*4K?
MX#AU0N96.0$2-G%]_"RF>KT3_`PT6[/'BR93/Y`&(+VGAP.8K5"=@EN+55E>
M^)`'OR8V.J\K&@R"[HCQS@%]?QQ&T&,N"U\3[<A9]W?$XC=84<P$F_@DA_=`
M7@'"\"OU0U5(<:-XPF)HHE=A=!%BS;C:4$[$,V"QSL^FKA%M;W?[L'OXDJ"2
M]S7T$JYND@Y/>'\^H11F(&X0W,])618Z!7UVJ6<G"DO68NN3RY,DG9V=K>=+
M!4D/2L2"0;[(QT3032[+:P41L580@N6KXR@+#.&2-9EL63WW"9<MN]3S$R$6
M^G%ZJ:[6!/EPZ>N??,OO\L^F-O++%]#17T`W?V'!GPU_#NE`1DX*RYU#1XWB
MC2890D-`TQF;][7/#@='S_>.D9+/.J^DQOQ=C!XGWMB-D;O_LD.0,>?C1!`H
M9A#]9@&H?#%F(0\G(@T/V>N47$0QG^E]!E.$LI!BDB#72>)#%))AU:H)P%[#
MPEA@/W7\(D]CSY5+5N76U+1D=II>3AD?K-"\,%RQ$48K-X36WZ)FBW]A9C;O
M:YQ.!@V^EE(,878C=`$=@J!@^.+!)M:!:/<UZ5<^7]'*A62J".6@^@B"'%3$
M^Z4-?6Z::-A9HQ!C2P+E=M:6:(_Z47]WOVP4,/1!JTX.:`-V)K3M@67.F5T#
M&TFK2.3[<T)A@.<K7"T?9Q2Q\+>():G(7K].^DWX`R'Z$*SZ($<??*T//M<'
MW^L;BT(#^0'*#.0'7&R4'Q6!/^.':T"%?17)1<0>1BS!9:2X;GS(3_D:99`H
M<%>2<1VQS+LB8LH(+VPBXGC9"M0,N!U4,W1!KR[HU06]NJ!7%_3J@EY=T*M;
M80:*^F(@/FC#'[;DVS",`QZ%RYGATFF83O#`)K(O_]LLP1.YF282`EG:6>SE
MMAH3,NK>_G&=',.>5'"8*H>;RE$<A_63230<L;!#3J,H8&Y87<S3%B],.[(R
M:)4S2%F@,\D;+\$6+\$F+\$V+\%&+YT**4JQ+$,*TQ/(3^H$/`-/KF'#<(.Q
M($9>(,]@SOPX23%WPH2S`H,_O[)%4!3$2NJ;8`K#8$B"'(-EB&Z87+"X`HK2
MN2`+>,B0^3GGRU!&L7O*4SJ^,^H\Q>,9'NPLW-FX<W#7P%VSHT9G33N%@!1J
M&F_8+[[$5B9_3]8-@ZZ+ND_=!.)PBWB77B#S7LR08O\<G(U!.+W$!&ND#<_.
M3LXW$*:./0..W'=8@*AWZ5T1^>'VE^N4TG7"<#2X:]P5M8`+L!A329=G/0FD
M2K(J!,;$M>X%KU!^;A-YS\AN4JA+WJ/9/5,A-+.;5D%H9?>PU>0].[OG%'1.
M=J]1T#6R>TU44MYL\IO8((+Y1.0%&S`4\U9"L[RDLDGE^H+@E-XX6\\Q9!=B
M+!2V0B;^$`M&SQ*>J>"9<W592IDU5V8K9?9<F:.4.5)&'FOYXH`P\MF&LO8?
M5YDSH,HP[$L.Z907#`+MN=2.#>6\4*B&Z23FZD4.@,L.ZCR&R<4971[,AC@V
MB:@UF;V662M$CBT^YT@TN$DAJO#4@&2372@;P3`.=<K9T"Q%`#X9+0*BVK&'
MAMHA\KMT61^G16@9FLN(3(7(6D9D%41)=6#*@DK62Y$,N]-+9\/8)+^!0"B/
MECR:\DCQR)T(>\27V/UX?]O@TYR$?/F`W/WF+M9?(%*)2"4BE8A4(M("T5P-
MT92(ID0T):(I$<T"T5H-T9*(ED2T)*(E$:T"T5X-T9:(MD2T):(M$>T"T5D-
MT9&(CD1T)*(C$9T"L;$:8D,B-B1B0R(V)&*C0&RNAMB4B$V)V)2(38G8+!"-
M*Q!ET$=@'@CXN"=#`>_[8EJ9]5G^G(!WQ75.N2[YQ=@J(BH.KQ)!3CQ#R2+*
MUK-PBQ?@Y9(->S5<2<XP$MV_1$L%+73X;&`80@[&;TE^NBG&?Q$Z3B\)Y<^M
M5!`S`Z&R-HY#,T&&5(!H\C8MR6?.X_,!/2E58&45F$4%8"*\%-%'U`/=4L09
M.4X-S4PT69<U7Y>U6)>=U665Z[*R(";JLD1=5EZ7E4DIZ[+GZ[)E7=D8(H*T
M,I*H+G%VACZ%C6V6AAC,<3DC3JCPF8FA1GL%-W\R@YD\GU&1G=W#^<>@Z(EN
MDLPF4_ZPC.?^>$^,,$,W=7&L#:-P*V3XC.Z<94\'RL]K\H=-28H_N\D>U_'7
MD2Z^C%2>+N4&$`FA!(+KH7_&7S1A1NGCZR9?K';+E^&MG"]J6E'##$TAZI%>
M`3&E\R7.S;8HS"4LF%=L09YL09[<;N(YG,`\8ZMIUK7/6I!);U$#<FD+_MI`
MZ^`=&QB`EK;Y!",;F%*>.@_Y_MOKL^?_;^]:FMHX@C"N\L'ADOR"U%;Y@.0`
MWIE=+4(4AQ4V)XRCF)0K1P$BJ"P>!F(<'_P;\Y/2KYF=0:L7+`91,ZXRZM;L
MO+;[F^YYJ,U$)2.W\Z$='?=I.;#OK[OY4\GBE4`3:+H&F_*@1IVLH7UYH(')
M$&&FS7I4A_Z(`?.E=F7@!YL)7*[\U/EY8;/."NT!1P]:Q-+@.(S>/+38A=F_
M<'E/NN<UW+T$V!.?#Q&0+$AP@?$S5@R8B=ZP);,ZC/6;AJ4;^'5JR13)Q)()
MDMJ2FAY6EE;X=6Q)0!MP&I'\9FKN9):$FB-P,QN6@55W4DMBU9W$DEAU1UN2
MJNXH2V/5G=B28%?P$)^>7;,7(%HD+I,/]M?F/;#3@J)/=A]I):T]`Z?WM7MP
M-1"'M7O2$U>#GKWND:Z9Y>CB)7;WST!#Q;E#T?EFZYM@3A2X(D!B-9P`*HM^
MW]E:,GLD0T"UZ.CTS67<J`;84^=BL%@Q/FE-TT*N!TC%FJH,$/N)Q+@B*X:0
M+YL&^53ER'=!*V-GIP.<"8>[:T'BL#<HLZ%GQ0X+<%A'BU?F`-4`O3:,ESJ,
M$Y@7P8!?/;2D_,W'2_5H%%Y,J^YI4/?;JOLH/1UGI-]53]EH4/-G-$P[TX,\
M9K',W#B5X]2_@C-]DR;X#%ZLPK7&E00R8&[(W&@`G64PU4/FIC_7?R[7T:1D
M4>V69L$E>M7%"C=J&AZ(,IJ&2]VL:V+.HV@VD?/92J[*+*U)DE-+D^@FVM(L
MNY-M"\P\C4E18/[%/Z>7`(D\3^WWCOL@@V2A3@LEC0`E54/).._\KE""F?63
M!1*"!P,D%D=B=AD$1_#K3&`$\Q<X`B[$HT81]7A09%ITR`(Z5(T.XU;:JD"'
MY,FB@R*[`:%!-4C=5U(T'1`0%)L8N+``)/QM)F9I80UQ!+]*'C4XZ/D#A[4`
M#E6#P[A%\RK`(7VRX*#%]4"44)K-AR8O-HKA@'8".B0I&@[H@(C=@$:&RAXU
M."3S!PYQ`(>JP6'<_E<5X-!XJN"`KH**%6]%(`Z4K4_$9GF"5R<*IV)E_7&[
M%>G\@8,*X%`U.(P[6E'!/L.H/?3]WA&&ZK0;6&9KA,^)R8%[D19S_@T%1H[`
MX59O`0.X,_FE.^@?RH-XL+#'=R)D#X+VQ,P@WJP'!^F@.SB0:*\82[;D1.8R
M;L'QCL]U#Z!K,,#R:&OA4Z]WSGT\.^>3EY>KBWC4LN4>N$2QCDBNHR'!QC.7
M)%[2/Y*PQ9_RS.6AF.4-EX-REJ<N!T4M3UP.V0"Y=EFHV;ER.2AS>>QR2.(5
M96)1JBG%8JYBETGYUAW..C*:#J-I=4<8W#?6'V%AUUA_A%%HD#`*'1)&PJ5H
MAT6(Y379JI(P!+/<<V.F409/H2)[W([EPX5H.9XA^V(#D*;3_C[.*,,E%H<@
MF_5E>UI/BG2J\XL\[O]];,HD!<3#WW/W$\FKK^U]@'N[`SCA]]_31*W1[[_'
MB4H:FN*_9FD2[O_]B'3/EU[,%1<C9'0?PEXC,?=6Y.RL.40-VD4GV>6>Q$;Y
M;12;Y#G0V9OGWZ=ZCM693[Y+C8@\Y8TTR!'=MK'F02YG>>9&5]SJF>NMLMWV
MX3NU7.SL!^V`M,'M1W&5X^(DT5^;QS=O39GTIH6&S`2_X>9#^8B'TG$/O6^1
MI35;31_?4E7%-2DGCW<U)-K@:=#>.RNT?__L\%\?`HJWC)KOO=UH*G6:6>F]
MUQ=YBA/5%]$5)L^L?Q35H-`E<(KP%@YV</`)C=(Z'?2BTJ4,<J7@`YO?_2/^
M>\@]=_LG0AS=H9\BM0_37\S##9@T$$8HS&`X@R*#,,O83-W):D;'$?$Y&Y])
M$'@_PR2U/O!H^9#ST.;4W*75U[0.=:\!0"?8_SK%F$\<_W,MP5@@2L5)&NS_
M'Y$X_B?)P%``T'?-5.)__OH?QX#^(W\W'/_RV<\?W^[FK3R-.CM_[NG62\C5
MVM:;,=@.NVV,"8I\)7P%?*1CH6.A$Z$3H.<G:.B'OW:W.*SF=FI":L8+S[9V
M]TK&Z1<9'_@?QZ>6ZU??:[EZE<?U^F^U[T`R8<:+\JG-6AORM15F@4_PP8P?
M?1]OPG=F!(GCC^#N^[VI!G'LL%4T0&;XBX$"H7HQ''D4XP"61()73I!LC!OI
M!?6TT4KQF^=.^,:24KUX\=HM52WXH46+4I57:A%H\[DMU0N#J9THJ6WME"I1
MTTU!B8T5:0LJC_$I3Z=N`U.OJ-2+W$I%;8^,W-KV`Z<W1H<F+8VL6A)GO>-'
M8O6C;JY-B*QJPGIRZ$<S`A19<V%T['*.5(F[)1B7DJ*&*PI,J2DH9:(Y#.5+
G^/>B@C"4(6QD2"&%%%)((8444D@AA1122"&%-(_I?R'K("``H```
`
end






Article: 1630
Subject: Re: AT&T ORCA: Using register input mux?
From: jbm@speedy.login.qc.ca (John B. McCluskey)
Date: Tue, 8 Aug 1995 12:23:51 GMT
Links: << >>  << T >>  << A >>
husby@fnal.gov (Don Husby) writes:

>Has anyone found a way to use the register input mux without having to make a 
>macro?  (Using NeoCad 6.1.1 software).

well, I have NeoCad 7.0, along with the latest ORCA viewlogic symbol libraries,
and there don't seem to be any symbols in the library that use the register
input muxes.  A macro is the only way I have found so far.  See the acc8 macro
in my other post on the 5x5 image convolver.  It saves a lot of hardware 
when you need to reset the accumulator flip flops to the new incoming value.

John McCluskey
J.McCluskey@ieee.org




Article: 1631
Subject: Re: Actel Place and Route response
From: johne@vcd.hp.com (John Eaton)
Date: 8 Aug 1995 15:22:43 GMT
Links: << >>  << T >>  << A >>
Chuck Gollnick   x196 (chuckg@arnet.com) wrote:
: In <3v33ki$1328@usenetw1.news.prodigy.com> CQEM17A@prodigy.com (Jeff Wetch) writes:

: >Net criticality can be done in Mentor by selecting the net in the 
: >schematic
: >and adding a property.  The property name is ALSCRT 

: Of course.  That's exactly what I would have named that property.  NOT!  
: Why not CRITICALITY?

: Chuck Gollnick
: Arnet 
--------------------------------------------------------

It is actually a good idea to name application specific properties
with obscure names. If you pick common names then you run into all
sorts of problems when you use the same capture system with other
venders using the same names.

John Eaton








Article: 1632
Subject: Re: Xilinx xc4013 routing problems ??
From: tom@dilleng.wa.com (Tom Dillon)
Date: Tue, 08 Aug 95 10:48:41 -0700
Links: << >>  << T >>  << A >>
n article <makkarm.807843146@ipoint> you wrote:
>Hi fellow FPGAers
>
>I'm a fairly new user of Xilinx FPGAs.
>I'm having a few problems with my current design using a Xilinx xc4013
>FPGA. With only around 84% CLB utlilzation and under 40% flip-flop
>utilization, the XACT software is crashing on routing. It always ends up
>with 70 unroutes.
>
>I'm sure I'm not pushing it to more than available routing resources when
>the CLB utilization is not filled.
>
>Handrouting all the signals is the last thing that I'm opting for.
>
>Any help is well appreciated

That is a very high usage for a 4013. It would be more confortable around 60 to 65%.

You are probably going to have to do much more work than you would have wanted to.

Are the pins frozen? If not you have a better chance.

Can you shrink the logic? This would help alot.

You could see if Xilinx would let you try the NeoCAD software. This may work better on this 
particular design.

You should look into floor planning the design. This means making modules out of your logic and 
hand placing the modules. 

The next release of the XACT system will have floor planning biult in.

Good luck,

Tom Dillon
DILLON ENGINEERING
2017 Continental Place
Suite 5
Mount Vernon, WA 98273-5649
e-mail: tom@dilleng.wa.com
Voice : (360) 424-3794
FAX   : (360) 424-5894


Article: 1633
Subject: Looking for info on ACM FPGA'96 workshop
From: klindwor@tech17.informatik.uni-hamburg.de (Andre Klindworth)
Date: 9 Aug 1995 08:54:10 GMT
Links: << >>  << T >>  << A >>

Some weeks ago, a CFP has been posted in news.announce.conferences.
Seems that I have lost it. Anybody out there knows where to get
information on this event or who might even provide the CFP to me?

Thanks a lot.

-- 
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
Phone: +49 40 54715-501, Fax: -397  Germany


Article: 1634
Subject: Re: Xilinx xc4013 routing problems ??
From: Yuce Beser <yuce@sh.bel.alcatel.be>
Date: 9 Aug 1995 10:37:57 GMT
Links: << >>  << T >>  << A >>
makkarm@ipoint.vlsi.uiuc.edu (Masood Makkar) wrote:
>Hi fellow FPGAers
> 
>I'm a fairly new user of Xilinx FPGAs.
>I'm having a few problems with my current design using a Xilinx xc4013
>FPGA. With only around 84% CLB utlilzation and under 40% flip-flop
>utilization, the XACT software is crashing on routing. It always ends up
>with 70 unroutes.
> 
>I'm sure I'm not pushing it to more than available routing resources when
>the CLB utilization is not filled.
> 
>Handrouting all the signals is the last thing that I'm opting for.
> 
>Any help is well appreciated

Hi,
One of the reasons XACT ends up with unrouted signals, is the name of the nets;
if you give different names to the nets that are supposed to be the same net
(i.e connected to each other), then each net having a different name will be
considered as different and will not be connected to each other. Some schematic
tools warn you, but some do not. If you are entering your design by using an
HDL, HDL compilers (at least the ones that I used) warn you as well. So, if you
are using a schematic tool, you might want to check your design once more
against this kind of a problem.

If you don't have such a connectivity problem, then you might try to optimise
your design, and give constraints (placer_effort, router_effort) to the router.

You might also try using a XC4025. If it fits and Xact generates no "unroutes",
then I think you must check again if the available resources (number of global
buffers, IO count, CLB resources) of XC4013 is sufficient for your design. If
the problem remains, then either the design is really big, or ... (I don't
know)

Good luck,

Yuce Beser.



Article: 1635
Subject: Re: Looking for info on ACM FPGA'96 workshop
From: wannema@bonsai (Markus Wannemacher)
Date: 9 Aug 1995 10:38:50 GMT
Links: << >>  << T >>  << A >>
Andre Klindworth (klindwor@tech17.informatik.uni-hamburg.de) wrote:

: Some weeks ago, a CFP has been posted in news.announce.conferences.
: Seems that I have lost it. Anybody out there knows where to get
: information on this event or who might even provide the CFP to me?

Hello Andre',
take a look at 

    http://www.cs.washington.edu/research/projects/lis/www/fpga96/

There you will find the CFP.

Markus

------------------------------------------------------------------------------
  @@        @@                                Markus Wannemacher
 @@@        @@@     @@@@@@        @    @      FernUniversit"at Hagen
@@@@        @@@@    @       @@@   @    @      LG Informationstechnik
@@@@  @@@@  @@@@    @@@@   @   @  @    @      LGZ, Profilstr. 10b
 @@@  @@@@  @@@     @      @@@@@  @    @      D-58084 Hagen, Germany
  @@@@@@@@@@@@      @      @      @    @      phone  +49 2331 987 4547
   @@@@@@@@@@       @       @@@    @@@@       fax:   +49 2331 987 375

Internet:  E-Mail:       Markus.Wannemacher@FernUni-Hagen.De
           WWW:          html://www.fernuni-hagen.de/www2bonsai/IT/team/wm.html
--------------------------------------------------------------------------------



Article: 1636
Subject: Re: Dog Food Drive For Joe Costello
From: jcooley@world.std.com (John Cooley)
Date: Wed, 9 Aug 1995 13:58:25 GMT
Links: << >>  << T >>  << A >>
Here's even more fun e-mail I've recieved concerning the dog food drive for
Joe Costello!  :^)
                                        - John Cooley
                                          the ESNUG guy


 From: gunes@jadeite.Eng.Sun.COM (Gunes Aybay)

 >Dear John,
 >
 >Please help advance my career.  Six weeks ago my company, Sun Microsystems,
 >started a new advertising campaign based around a short haired St. Bernard
 >named "Network" as being our new corporate mascot.  (The ads have been in
 >the business press to target MIS managers.)  "Network" is supposed to be
 >Scott McNealy's (CEO of Sun Microsystems) dog.
 >
 >I grew up in Turkey.  To me, St. Bernards are the dogs used for search and
 >rescue operations on European mountains to find buried skiers.  In cartoons, 
 >they're sometimes seen as drunk because they're drawn carrying small barrels
 >of liquor under their collars.  (What this has to do with networking I don't 
 >understand.  I asked my co-workers & none of them associate networking with 
 >St. Bernards or any other dogs either.  They just know that the people 
 >upstairs like it and that's what counts!)  Inside Sun, they have a bulletin
 >board with critical info like how much "Network" weighs and a message of the
 >day like: "Today it was hot.  Network drank a lot of water."  They even put 
 >his dog house in front of Sun's headquarters for a while -- until they moved 
 >it in front of the company cafeteria.  (Is this a good sign about our 
 >cafeteria food, John?  No one here will talk about this.)
 >
 >John, here is how you can help me.  Please take all the *gourmet* dog food 
 >you get from your dog food drive for Joe Costello and ship it to my CEO,
 >Scott McNealy, here in California.  (I'll pay for shipping.)  Please add the
 >following *handwritten* note: 
 >
 >   "Dear Scott, 
 >      One of your best designers, <unreadable name>, thought you'd
 >      love this gourmet dogfood for Network!
 >                                               - John Cooley"
 >
 >When Scott phones you to find out who the unreadable name is, if he seems
 >happy, tell him: "Oh, that was my good friend Gunes Aybay!  Gunes Aybay is 
 >not only a joker, Gunes Aybay is one of your best designers! You should give 
 >Gunes Aybay a raise and a promotion in my opinion, Scott!"  BUT, IF HE SEEMS
 >ANGRY, quickly tell him: "I can't remember who wanted me to send you the dog 
 >food.  I'm really busy now.  Can't talk.  Gotta go!"
 >
 >    - Gunes Aybay
 >      Sun Microsystems
 >
 >P.S.  It's OK to publish this letter on Internet.  Half of Sun's management
 >is busy walking "Network" around the building and the other half are on 
 >"pooper scooper" duty.  They won't have time to find this on Internet!  :^)


===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3661 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Article: 1637
Subject: external connections for efficient internal routing
From: george@cmf.nrl.navy.mil (George Schmitt)
Date: 09 Aug 1995 14:39:52 GMT
Links: << >>  << T >>  << A >>


Suppose I have an FPGA (xilinx 4005 specifically) with a 32
bit data path entering and a 16 bit data path exiting.  Data
enters, is "processed" and then exits.  The processing is
nothing more than a few pipelined registers and perhaps some
bit shifting and masking.  Would the internal routing of the
design be more efficient if the external connections were 
very regular (i.e. 16 IPADs clustered near each other and 
16 OPADs clustered near each other) or irregular (PADs just
"randomly" placed all around the chip).

The regular case certainly has advantages that dataflow
might be able to be kept moving in just one dimension but
I wonder if the noisy nature of the irregular case is good
enough to overcome whatever problems the regular case implies
in terms of local shared resource contention etc.

Has anyone look at or thought about this problem?

Thanks.

-George
 george@cmf.nrl.navy.mil



Article: 1638
Subject: Re: AT&T ORCA: Using register input mux?
From: John McCluskey <jbm@j2mont.jtechmont.login.net>
Date: 9 Aug 1995 15:27:10 GMT
Links: << >>  << T >>  << A >>

>> husby@fnal.gov (Don Husby) writes:

>>> anyone found a way to use the register input mux without having to make a 
>>>  (Using NeoCad 6.1.1 software).

>well, I have NeoCad 7.0, along with the latest ORCA viewlogic symbol libraries,
>and there don't seem to be any symbols in the library that use the register
>input muxes.  A macro is the only way I have found so far.  See the acc8 macro
>in my other post on the 5x5 image convolver.  It saves a lot of hardware 
>when you need to reset the accumulator flip flops to the new incoming value.

>John McCluskey
>J.McCluskey@ieee.org

ARGHH!  What a moron I am!  5 minutes of looking at the AT&T ORCA Macro library (version 3.0) would have revealed the existence of a whole class of flip flops that invoke the 
input multiplexers on the flip flops.   Page 2 of the manual (which is available by FTP 
as a postscript file from ftp://orca.fast.net/orca/viewlogic/viewlogman.ps.Z) sez:

Table 5-1 Flip-Flop/Latch naming conventions (name = abcdef)

a=	F - Static implementation

b=	D - D type flip flop
	J - J/K type flip flop
	L - Cells contain a positive select front end (loadable)
	N - Cells contain a negative select front end (loadable)
	S - R-S type flip flop
	T - Toggle typ flip flop

c= 	Value - Number of clocks

d=	This parameter identifies the enable capability
	S - no enable input
	P - Positive level enable
	N - Negative level enable

e=	This parameter identifes the clock capability
	1 - Positive level sense (latch)
	2 - Negative edge triggered (flip flop)
	3 - Positive edge-triggered (flip flop)
	5 - Negative level sense (latch)

f=	A - No clear or preset inputs
	B - Positive level asynchronous preset
	D - Positive level asynchronous clear
	E - Negative level asynchronous clear
	G - Negative level asynchronous preset
	I - Positive level synchronous clear
	J - Positive level synchronous preset
	L - Negative level synchronous preset
	M - Negative level synchronous clear
	X - Standard library element where GSR asynchronously clears or presets the
	    flip flop depending upon the function of the local clear or preset. If
	    no local clear or preset is present (f=A) then GSR clears the register.
	Y - Element is preset using GSR rather than cleared
	Z - Element not compatible with similar elements available in the standard cell
	    library.

 
-------------------------------------------------------------

So, a positive edge triggered flip flop with a positive level select input mux and positive 
enable input would be encoded as FL1P3AZ  (the Z is tacked on to indicate that there is
no direct equivalent in the standard cell library.

There:  I've corrected myself.

John McCluskey
J.McCluskey@ieee.org




Article: 1639
Subject: Repost: VHDL Source for 5x5 Image convolver in ORCA FPGA
From: John McCluskey <jbm@j2mont.jtechmont.login.net>
Date: 9 Aug 1995 15:58:36 GMT
Links: << >>  << T >>  << A >>

Repost of the VHDL convolver.  CNEWS seems to have munched the
first posting.  Second attempt is via Mosiac... 

John McCluskey
J.McCluskey@ieee.org

-----------------------------cut here-------------------------------
begin 644 convolver.tar.gz
M'XL(`/'+)C```^Q<6W?;2'*F[-G9'>3FG22;R[[TT6;7T@D%HW'AS3,^H4C*
MED>6K8MW['E1(+!%XA@$&`"4K'G9?Y)S\AORGH?\E"3GY.0M;WF<5'4W@`8)
M2IRQ97MV#5NX==775=75U=4`V/J]PT&W_V10N\&-&D;#MDF-X&;,'0FA#C4(
M:1B4.K9MVB;<,:CMU(AQDT)EVRQ)W9B06AQ%Z55TUY7_2+?^C)$T(M-H.@O`
M#D,V<<-AG>P2=P(WD]0/1R0=,[(Q>,TF4R#9)+]]U-\C232+/4:\:,C(6103
M5W->.*1%3OV4^!-WA$7A>12<LQBNIP&;L#!E0^*'Q`W)T\->EY@]PR8[SQYV
M=4*.QWY"+MR$#*.0:7!TR10L?D;@/P!Y;)J";(D_"NO`/R1C(`FCE)PR%I+$
MGX#PB.ZFP'C*QNZY'\5N0*)8&T$!"=@Y"Z":#>1-Q[.$0'6!_XH%EZ@]U)"Z
M(-GI;)3HFR`,(_LL\ERL)QZ2B>O%4:*Y,2-ND$2@@Q?,A@S,!%)<L"`@7.!D
MXL+IU/5>H?H`.V1G?LA0$8\-9S%+T%):<AEZXS@*(Y#B(O93ML5"]S0`,P;^
M%';1-.$&049VQF(&VI,S'P@VXFB6LE@#<9,T!H'3A/R&C"(0:A,52E@JV@)L
M/!I!?8E_SDC+(4\>?4N\(/)>D;.8_=,,$"_KH&RJ8<N>LB0%FX#I/&3TTAFH
M<0FWX7SL@^&&9.,BBA,L3QB)L$53\(6Z4"P!&31HZ!24YE*X("58N47U%E:L
M$TU#943KD5G"L.7()`)K0JTA,47K)-C4033R/:@ZO<!V+0S"&UUSSR-_F!"T
M`KHEF&$$LOL1--PE`..]PZ=/CJ!]DI1!XP'@81>NT2:H:1!%KV93+45KHXTW
M.#5XW-V4A`ST1#^(HP`\(V3))E!HL#V.QB%YXO6"6?**7<*UGE_\@\\8TZ-X
MI&GONQ__T$V_YWH>-0,]G'@W5<<U\=]IV!#_G6;3M&QJ-BR(_]1P[(_Q_UUL
M__LOM;7:I\(':FZ:FIYAR*-=.S*-5LT"@GO_\^__RLD_Z?9ZCW9KW\%6>[;S
MO,;/UJ#@OWJ[^T^>O^C`@1SN/GNV-WCRM#_H=/M]TMO[BI?L?45Z`SRCY.BP
M#R>T<S@X&AS+*[-T9<FKG1VX,#H[XH1F)V9V8O&3O>YQ[Y'5^=5.?F&J%U2]
M,/B%J,7(Z^32[@Q.C@9[@]XQX9="#[('I2`U'&IKH/[>TPKU_T.J;_R>*W_\
M]-D?;N,/6>!>5JC_SV^N).U\W<^4R\XL<;:2>E*'HY?[/2'^CIV);M10QE_^
MW='NP_WNW@D5"M1NP3_8?O?=[[[KFC(8X,77?;@"CHS>K*"G)7I:HK<JZ(T2
MO5&BMP7]FD)_H-)OE\F="G)5G.VR-(T*<E7;[;*RS0IR2R6W2N2M$OD:4O2>
M/C]6&*!'E#C:N74^R3GVOE(9\`H;[%9^A=BW\ZO;!1@MM^6::NNU*EM3<Y&!
MMU_.T2V;CUH5-9BE&LH&I'8%@U5B*)N0.HLV/%!UF&M_VJB@5S68<P#:K*!7
M-9CS`%K1I@>J`G,N8!HE^ENJ_+<JY#=I!3U5Z<ORFV8%O:G2SW57JX+>4NGG
MY"_ZWV>9GY7HNX;BC^@>.2PZPNW\`G@^R2ZXW_VDN`*N3XLK8/MI<05\/U/$
M<7+_N9V)PVGR#M(5\F?!Q.("Y>P5_;WHD;<KXUO906XO&'B^"YNM"@:U!7&L
M*#&TJW12@U;&(3R,7R'T+[`\"P^R8\O8*SNA[%J<`[@%S9J@61,T:Y)&.J64
M5&HH6GI-E*V)LC51MB;*;HFR6Z+LEBB[!64HU\]K7;MVI]9U<-?`71-V>_W:
MYRCN'13V#HIZ!P6]4SNP:_]8.W!PU\!=$W<&[BCN3-Q9N&OAKLT+1#&6KWU:
MB^#?+VM_4LNV-7F\)8^WY?$3>?R)/'XJCS^5QY_)XV?RF,W>_D@>_U@>LYK^
M5![_3![OR.//Y?%S>?QS>?P+>?Q+>?R%//Z5//ZU//Z-//YM+O=7H-)W_[=6
M6^.[0L,;V_C\KW63L[]KYW^6U6SP^1]M`"7%^9_1@+CZ<?[W#K9\_M>Z8O;W
MWW=$S[BU;/;WGW("L&W_/N?_RR9__W9#D[]WIACH\'DV6A7Y#(^F"REP:?S%
M(>;60BZOYO[;*N]\\N=4T%\U%VE4T%\U%VE6T%\U%VE=,UN8RX[;U\Q%NG.I
MJU%!KZ:ZW;G4N"*]KYXLS.?W5TQ(MNW*!']INMNMSN^7IM/S$XBJ]+XTX:A.
M[U6=MZ^</S0K&*Z<H;0J&&B)84Z%=@7#5;.L;$J@,L@,K3:7[_'$0>HGI9:R
MR!JR]LXR/$&[)FC7!.V:I)7MEJ5V,M&3J=V2#*^/"5L?4[<^)G%]3.=$9L>S
MN#ZF;7U,X/J8RO4QJ1-I6R-/Y>PE61SD:U_!O\\_P'RMR+/^X#?]WID?I/HT
M/KNY.JY[_VLX(O^S#<=I-!R\TVPT/N9_[V([ZCT:/.D>[_;(T7'W\)C<UWY%
MHMB;N-,.(><L3O#UV@Z^T8LO25,WR-86.9XQ\G@6$K-)J-,QFQV[36B[[6A:
M@3;8[P/6SN'@X/E@O_>2[$,^L@Z1Y<0/TW72<G2#;_S5Y'WMV>'NT\/=X]UO
M!H(0\A5C'=R@NH@N+S*7%UGKQ%Y29*\3:TF1LQRPL;RH*8N>'T&B]73_X=[N
M?DFS)25T:8FYM,1:6F(O+7&6EC26EC2QY'U[Z\?M;6\R_J<7\<W5<77\IPW3
MY-__&(9I.K9-^?M?X^/\_YUL6V]YT_99U.OVR?%AMS>HD]\NCB!:+YI>QOYH
MG.*@0;=PY,`/."3C;NCIA'2#@'":A,0L8?$Y&^J:UA??D.#',!WQZ<")Y>BA
M-]2>E3^5Z9`LJP&><]]C]63*V)`SR<<;=4L[9-,H3L7G)[P(QKO3*&%0)1;4
M2>!/?/RL*(TPG,/I)"%3%BL?YFAOW7ZPO77,PCH=LNJ03)2M25M2^\2+8OSP
MB5*2@G'"$6%Q',4)&;*4>2FVTEN77AM@%:+!V[IIMD*L+G`OR<[NWK%QTJ7W
M^),9;";USJ-=PEY[T.R)H@RE>K-AYPC%IU3@!HE*2"RT1\B_JII-"7XWY<?\
M*S:RD4:I&Z#R+0&VB?YKZ#:>:Q+C\-X.[/N\EH7M"*RY</.0B8_J,B$.45R]
MR84HMOZ.CL^30%<X.S!5@#ES;)S%T83(!MY442V=<BN680%,H';I(NHWV\^/
MOC`?J"BV-%`9!9@%"CYX6":;"@-V*\-DO`#3@]/=_2H5BT<>V!P+6L*6^X_"
MGKD/V6A0O?5K\;U9G5@MW?PU_ZZ,;=;Q@S3^&9KX+$U?\#^KY'_V@O_9[\W_
MG/;-^]]./_,_.#M8\!1[5?^SRIXCP`1JUUA$Y?Y'K_,_P2Q0%OW/7LW_,EZ`
M&?0K_,]^,_^SWM#_J/G!QC^[]:[C7T6D6LW_N!7+L`=9Y%KT/V-%_Q/,'W3\
M$XJC_[55_Z.K^A]MEOW/6O`_Z[WYG_$._&_G81[_'NH'E@HP9XZK_,]HSOF?
M`!.HW851W1+^9UT;_SBS0%GT/VO%^/>PB'\/*_S/>A/_$^X#_F>BRV7^UT1G
M7-'_G-:'.OY:[7>0_Y7'WP5/67'\-9S6XOAK9N-OQ:B^6OXGF#_D\5>X#_<_
M4_6_UDK^A][3,G+OP<=O*.9>]_@$[6,_>"./,W3S6H\#-$=Q.9,V;M[E'N4A
M#\[*0RZWP')'<W3::)1=1$``UO'AKC[8U0W]N,!RRH)8BB`*N<K\5!9O/]\Y
M/MG=S]KAQ+'+#M^@]B(4#QF#1_K7?77$+U"^AVOEGD$V3$=W<M=JVGBQ2FAK
MZ6WJ5*9V$,C>=VI''7KS?M;+4SLX.ZA(PG+EEWN<J;>X%<NP!UE2UET8L&5J
M9Z^2VED?<&J7N0^$-DM-[1HKIG;@/0V</WXPH<UH.S_RT&9^O]!FED*;61W:
MG`<G=JL<VNRVM0A5A#95J0+E^X4VX1D\M#75T&:M&MJ:[68IM)DG?93#>)!%
M-O-]13;#LM[!I/5Q/FE]7#%I**QQ56!K<!N64>6<X;&^O0ST^CD#9Q8HBX'-
M7#%G>USD;(\K`IOY)H%-.`\$-EM]9N*L^,P$PTK+4@.;\9X#&WT'C^D>Y=.$
M1_./Z;@%ECN:#8Y&YP);7PUL7=U2`QN])K`)<I6Y,K`U(;`9Y<#6:IN+4$5@
M4SV^0/E^@4UX!@]L;36P735F?NW&(30K.%>+)WWXOL1/^"^,)^YK?S*;%#^S
MEK\]AN+BG1%`:%3]<3?^D'W"4KQ_+%ZJ)+/)Q(TO._,O4W("\=:E@^]AR!&^
MD^D0$UQ`TWK*;\,]_EMM?'DS==-Q4B<&"5DJ?DQ-6H:)?ATR#W]!G9"-5@-C
M.^?!GW+CBZA>S/C/ZI]$(7D\"_`EF-'NF.V.X8@//G[P2YTEVX_W=]0_UDV^
M_S\?#V^NCJO?_UNF8])L_0_Q6W!J-)WFQ_?_[V+;VB+9RA[D+'#/(5Q5K^]!
M<'V/TLH>&(?0>5@,<8!<^.E8KO_A1>SLS/=\AD&(QQI^>Q;BVWN^!LATEF:+
M7+BQ-_;QW?$LQK?IQ/5PL8^$X#<!*4O$DAZI/V$B;&'=+$Y%N,UH(-I%<)&P
MV'<#K`N!(`PR=\(!6@9Y`G>3>PD#_F&=7/HL&*+\`#V&0#\:@T2X7@1$N(D?
M!!`1$4(H.N,!4O(*/=4E3+8L_*$$A-@X195PT)<CAA?-0BX*A/^F09[M/+^;
MD$A4!!5S2EZG41>+DHS\<R%4&$&4AU*^>`F'`4)$LO`%/=[-S,>_:Q"KF8AO
M%2#%2/G:(='4!4+\^$(D,5`3%GAN'%\B%%^I)>3W1/LD8_^,+ZP!33#C*ZK`
M$".LCD1#'RSJG\X6(!&L!<8/H!$)-K$;P'`"U[2.=\TZT75]DUR,?6^<+[&!
MB,)YP%BN:(MPB%#0:D-N)"';*(A.P1)0-714L,;I+)&KE40!UIBH4#%+9@&X
M%N`@U#;SW%F"ZXRP)*-)<`D2,'&N#BX;$T.CP@@,;>9.P7*N-ZXKL,(55)^.
M&8$3R/2"RVSQ&"9<0UKT'"!Q@1>QY`B12XX@T&Y((J"(,Y'ENBA0^S@:2M7R
M!7,(-$/J3P.?Q5N04^0ZU!$)ZPEGDU,`08<:#AG_#F/*0L"1UI.5J-)S*4K?
MX#AU0N96.0$2-G%]_"RF>KT3_`PT6[/'BR93/Y`&(+VGAP.8K5"=@EN+55E>
M^)`'OR8V.J\K&@R"[HCQS@%]?QQ&T&,N"U\3[<A9]W?$XC=84<P$F_@DA_=`
M7@'"\"OU0U5(<:-XPF)HHE=A=!%BS;C:4$[$,V"QSL^FKA%M;W?[L'OXDJ"2
M]S7T$JYND@Y/>'\^H11F(&X0W,])618Z!7UVJ6<G"DO68NN3RY,DG9V=K>=+
M!4D/2L2"0;[(QT3032[+:P41L580@N6KXR@+#.&2-9EL63WW"9<MN]3S$R$6
M^G%ZJ:[6!/EPZ>N??,OO\L^F-O++%]#17T`W?V'!GPU_#NE`1DX*RYU#1XWB
MC2890D-`TQF;][7/#@='S_>.D9+/.J^DQOQ=C!XGWMB-D;O_LD.0,>?C1!`H
M9A#]9@&H?#%F(0\G(@T/V>N47$0QG^E]!E.$LI!BDB#72>)#%))AU:H)P%[#
MPEA@/W7\(D]CSY5+5N76U+1D=II>3AD?K-"\,%RQ$48K-X36WZ)FBW]A9C;O
M:YQ.!@V^EE(,878C=`$=@J!@^.+!)M:!:/<UZ5<^7]'*A62J".6@^@B"'%3$
M^Z4-?6Z::-A9HQ!C2P+E=M:6:(_Z47]WOVP4,/1!JTX.:`-V)K3M@67.F5T#
M&TFK2.3[<T)A@.<K7"T?9Q2Q\+>():G(7K].^DWX`R'Z$*SZ($<??*T//M<'
MW^L;BT(#^0'*#.0'7&R4'Q6!/^.':T"%?17)1<0>1BS!9:2X;GS(3_D:99`H
M<%>2<1VQS+LB8LH(+VPBXGC9"M0,N!U4,W1!KR[HU06]NJ!7%_3J@EY=T*M;
M80:*^F(@/FC#'[;DVS",`QZ%RYGATFF83O#`)K(O_]LLP1.YF282`EG:6>SE
MMAH3,NK>_G&=',.>5'"8*H>;RE$<A_63230<L;!#3J,H8&Y87<S3%B],.[(R
M:)4S2%F@,\D;+\$6+\$F+\$V+\%&+YT**4JQ+$,*TQ/(3^H$/`-/KF'#<(.Q
M($9>(,]@SOPX23%WPH2S`H,_O[)%4!3$2NJ;8`K#8$B"'(-EB&Z87+"X`HK2
MN2`+>,B0^3GGRU!&L7O*4SJ^,^H\Q>,9'NPLW-FX<W#7P%VSHT9G33N%@!1J
M&F_8+[[$5B9_3]8-@ZZ+ND_=!.)PBWB77B#S7LR08O\<G(U!.+W$!&ND#<_.
M3LXW$*:./0..W'=8@*AWZ5T1^>'VE^N4TG7"<#2X:]P5M8`+L!A329=G/0FD
M2K(J!,;$M>X%KU!^;A-YS\AN4JA+WJ/9/5,A-+.;5D%H9?>PU>0].[OG%'1.
M=J]1T#6R>TU44MYL\IO8((+Y1.0%&S`4\U9"L[RDLDGE^H+@E-XX6\\Q9!=B
M+!2V0B;^$`M&SQ*>J>"9<W592IDU5V8K9?9<F:.4.5)&'FOYXH`P\MF&LO8?
M5YDSH,HP[$L.Z907#`+MN=2.#>6\4*B&Z23FZD4.@,L.ZCR&R<4971[,AC@V
MB:@UF;V662M$CBT^YT@TN$DAJO#4@&2372@;P3`.=<K9T"Q%`#X9+0*BVK&'
MAMHA\KMT61^G16@9FLN(3(7(6D9D%41)=6#*@DK62Y$,N]-+9\/8)+^!0"B/
MECR:\DCQR)T(>\27V/UX?]O@TYR$?/F`W/WF+M9?(%*)2"4BE8A4(M("T5P-
MT92(ID0T):(I$<T"T5H-T9*(ED2T)*(E$:T"T5X-T9:(MD2T):(M$>T"T5D-
MT9&(CD1T)*(C$9T"L;$:8D,B-B1B0R(V)&*C0&RNAMB4B$V)V)2(38G8+!"-
M*Q!ET$=@'@CXN"=#`>_[8EJ9]5G^G(!WQ75.N2[YQ=@J(BH.KQ)!3CQ#R2+*
MUK-PBQ?@Y9(->S5<2<XP$MV_1$L%+73X;&`80@[&;TE^NBG&?Q$Z3B\)Y<^M
M5!`S`Z&R-HY#,T&&5(!H\C8MR6?.X_,!/2E58&45F$4%8"*\%-%'U`/=4L09
M.4X-S4PT69<U7Y>U6)>=U665Z[*R(";JLD1=5EZ7E4DIZ[+GZ[)E7=D8(H*T
M,I*H+G%VACZ%C6V6AAC,<3DC3JCPF8FA1GL%-W\R@YD\GU&1G=W#^<>@Z(EN
MDLPF4_ZPC.?^>$^,,$,W=7&L#:-P*V3XC.Z<94\'RL]K\H=-28H_N\D>U_'7
MD2Z^C%2>+N4&$`FA!(+KH7_&7S1A1NGCZR9?K';+E^&MG"]J6E'##$TAZI%>
M`3&E\R7.S;8HS"4LF%=L09YL09[<;N(YG,`\8ZMIUK7/6I!);U$#<FD+_MI`
MZ^`=&QB`EK;Y!",;F%*>.@_Y_MOKL^?_;^]:FMHX@C"N\L'ADOR"U%;Y@.0`
MWIE=+4(4AQ4V)XRCF)0K1P$BJ"P>!F(<'_P;\Y/2KYF=0:L7+`91,ZXRZM;L
MO+;[F^YYJ,U$)2.W\Z$='?=I.;#OK[OY4\GBE4`3:+H&F_*@1IVLH7UYH(')
M$&&FS7I4A_Z(`?.E=F7@!YL)7*[\U/EY8;/."NT!1P]:Q-+@.(S>/+38A=F_
M<'E/NN<UW+T$V!.?#Q&0+$AP@?$S5@R8B=ZP);,ZC/6;AJ4;^'5JR13)Q)()
MDMJ2FAY6EE;X=6Q)0!MP&I'\9FKN9):$FB-P,QN6@55W4DMBU9W$DEAU1UN2
MJNXH2V/5G=B28%?P$)^>7;,7(%HD+I,/]M?F/;#3@J)/=A]I):T]`Z?WM7MP
M-1"'M7O2$U>#GKWND:Z9Y>CB)7;WST!#Q;E#T?EFZYM@3A2X(D!B-9P`*HM^
MW]E:,GLD0T"UZ.CTS67<J`;84^=BL%@Q/FE-TT*N!TC%FJH,$/N)Q+@B*X:0
M+YL&^53ER'=!*V-GIP.<"8>[:T'BL#<HLZ%GQ0X+<%A'BU?F`-4`O3:,ESJ,
M$Y@7P8!?/;2D_,W'2_5H%%Y,J^YI4/?;JOLH/1UGI-]53]EH4/-G-$P[TX,\
M9K',W#B5X]2_@C-]DR;X#%ZLPK7&E00R8&[(W&@`G64PU4/FIC_7?R[7T:1D
M4>V69L$E>M7%"C=J&AZ(,IJ&2]VL:V+.HV@VD?/92J[*+*U)DE-+D^@FVM(L
MNY-M"\P\C4E18/[%/Z>7`(D\3^WWCOL@@V2A3@LEC0`E54/).._\KE""F?63
M!1*"!P,D%D=B=AD$1_#K3&`$\Q<X`B[$HT81]7A09%ITR`(Z5(T.XU;:JD"'
MY,FB@R*[`:%!-4C=5U(T'1`0%)L8N+``)/QM)F9I80UQ!+]*'C4XZ/D#A[4`
M#E6#P[A%\RK`(7VRX*#%]4"44)K-AR8O-HKA@'8".B0I&@[H@(C=@$:&RAXU
M."3S!PYQ`(>JP6'<_E<5X-!XJN"`KH**%6]%(`Z4K4_$9GF"5R<*IV)E_7&[
M%>G\@8,*X%`U.(P[6E'!/L.H/?3]WA&&ZK0;6&9KA,^)R8%[D19S_@T%1H[`
MX59O`0.X,_FE.^@?RH-XL+#'=R)D#X+VQ,P@WJP'!^F@.SB0:*\82[;D1.8R
M;L'QCL]U#Z!K,,#R:&OA4Z]WSGT\.^>3EY>KBWC4LN4>N$2QCDBNHR'!QC.7
M)%[2/Y*PQ9_RS.6AF.4-EX-REJ<N!T4M3UP.V0"Y=EFHV;ER.2AS>>QR2.(5
M96)1JBG%8JYBETGYUAW..C*:#J-I=4<8W#?6'V%AUUA_A%%HD#`*'1)&PJ5H
MAT6(Y379JI(P!+/<<V.F409/H2)[W([EPX5H.9XA^V(#D*;3_C[.*,,E%H<@
MF_5E>UI/BG2J\XL\[O]];,HD!<3#WW/W$\FKK^U]@'N[`SCA]]_31*W1[[_'
MB4H:FN*_9FD2[O_]B'3/EU[,%1<C9'0?PEXC,?=6Y.RL.40-VD4GV>6>Q$;Y
M;12;Y#G0V9OGWZ=ZCM693[Y+C8@\Y8TTR!'=MK'F02YG>>9&5]SJF>NMLMWV
MX3NU7.SL!^V`M,'M1W&5X^(DT5^;QS=O39GTIH6&S`2_X>9#^8B'TG$/O6^1
MI35;31_?4E7%-2DGCW<U)-K@:=#>.RNT?__L\%\?`HJWC)KOO=UH*G6:6>F]
MUQ=YBA/5%]$5)L^L?Q35H-`E<(KP%@YV</`)C=(Z'?2BTJ4,<J7@`YO?_2/^
M>\@]=_LG0AS=H9\BM0_37\S##9@T$$8HS&`X@R*#,,O83-W):D;'$?$Y&Y])
M$'@_PR2U/O!H^9#ST.;4W*75U[0.=:\!0"?8_SK%F$\<_W,MP5@@2L5)&NS_
M'Y$X_B?)P%``T'?-5.)__OH?QX#^(W\W'/_RV<\?W^[FK3R-.CM_[NG62\C5
MVM:;,=@.NVV,"8I\)7P%?*1CH6.A$Z$3H.<G:.B'OW:W.*SF=FI":L8+S[9V
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`
end







Article: 1640
Subject: Clocking methods - which is prefered?
From: aweir@onsys.com (Alan Weir)
Date: 9 Aug 1995 18:43:58 GMT
Links: << >>  << T >>  << A >>
If one were to implement an ISA interface (for example) which includes an
IOW- signal with lots of data setup and hold prior to/following the 
rising edge, which would be the prefered implementation of a write 
register.

o - Use a system clock (BCLK at 8Mhz), synchronise IOW- through 3
    D-types to produce a one clock period signal which one AND's with 
    a Register Select signal to produce Clock Enable which is presented
    to the register to be written along with the system clock and the
    data.

OR

o - Use the IOW- signal as the register clock and the Register Select 
    signal as the Clock Enable.

I realise that the purist (synchronous) solution is the first method but 
what are the drawbacks to the second method. The advantages are that I 
can latch data in an ISA short cycle (92nS) whereas the first solution 
requires 3 clock cycles (360nS @ 8MHz) resulting in an ISA standard 
cycle (530nS). The design will be implemented in a Xilinx 52xx. 

-- Alan



Article: 1641
Subject: Re: AT&T ORCA: Using register input mux?
From: fjk@nozone.cnet.att.com (f.j.koons)
Date: Wed, 9 Aug 1995 18:55:35 GMT
Links: << >>  << T >>  << A >>

You'll need to use a hard macro to utilize the front-end 2-1 MUXes on 
ORCA PFU registers. This is true for both versions 6.1.1 and 7.0 of Foundry. 
AT&T is working on enhancing the technology mapper to automatically take 
advantage of this hardware.

Fred Koons
AT&T Microelectronics



Article: 1642
Subject: Re: Clocking methods - which is prefered?
From: mooredan@ux5.cso.uiuc.edu (Daniel Lee Moore)
Date: 9 Aug 1995 20:10:40 GMT
Links: << >>  << T >>  << A >>
aweir@onsys.com (Alan Weir) writes:

>If one were to implement an ISA interface (for example) which includes an
>IOW- signal with lots of data setup and hold prior to/following the 
>rising edge, which would be the prefered implementation of a write 
>register.

I think you are trying to make a I/O Port type interface.  If so take a 
look at Eggebrecht's book: Interfacing to the IBM Personal Computer from
Sams Publishing.  It show a very simple interface which could easily be
implemented in a FPGA or PALs (it's shown in 74 TTL).

The interface does not use the system clock.  I have built the interface
and have used it without any problems, I may have a PS file laying
around of the one I made.  I built it with TTL.
-- 
*******************************************************************************
* Daniel L. Moore                                           mooredan@uiuc.edu *
* University of Illinois at Urbana-Champaign    --     College of Engineering *
*******************************************************************************


Article: 1643
Subject: Xilinx FPGAs ---> Xilinx EPLDs
From: aguyer@eecs.wsu.edu (Al Guyer)
Date: Wed, 9 Aug 1995 20:27:57 GMT
Links: << >>  << T >>  << A >>
We have designs using the XC4003 and have tested and perfected (to a
limited extent ;)  ) our design.  We have heard that it is possible to
take the bitstream for the XC4003 and write it to a Xilinx EPLD.

Is this for real?  We sure could use such an option, since it would
help immensely with our final design.

Alan Guyer
aguyer@eecs.wsu.edu
Engineering Tech II
Washington State University



Article: 1644
Subject: Re: AT&T ORCA: Using register input mux?
From: husby@fnal.gov (Don Husby)
Date: 9 Aug 1995 21:36:32 GMT
Links: << >>  << T >>  << A >>
jbm@j2mont.jtechmont.login.net wrote:
>  Page 2 of the manual (which is available by FTP as a postscript file from 
> ftp://orca.fast.net/orca/viewlogic/viewlogman.ps.Z) sez:

I found this file, but it didn't have anything remotely resembling the text 
you gave here. ??



Article: 1645
Subject: Re: AT&T ORCA: Using register input mux?
From: husby@fnal.gov (Don Husby)
Date: 9 Aug 1995 21:40:17 GMT
Links: << >>  << T >>  << A >>
fjk@nozone.cnet.att.com wrote:
> You'll need to use a hard macro to utilize the front-end 2-1 MUXes on 
> ORCA PFU registers. This is true for both versions 6.1.1 and 7.0 of
> Foundry.  AT&T is working on enhancing the technology mapper to
> automatically take advantage of this hardware.

What is the deal with version 7.0?  Has AT&T released a version 7.0 of 
NeoOrca?  How can I get an upgrade from my NeoCad 6.1?



Article: 1646
Subject: RE: Xilinx FPGAs ---> Xilinx EPLDs
From: randraka@ids.net
Date: Thu, 10 Aug 95 11:29:02 +500
Links: << >>  << T >>  << A >>
In Article <DD299t.ILH@serval.net.wsu.edu>
aguyer@eecs.wsu.edu (Al Guyer) writes:
>We have designs using the XC4003 and have tested and perfected (to a
>limited extent ;)  ) our design.  We have heard that it is possible to
>take the bitstream for the XC4003 and write it to a Xilinx EPLD.
>
>Is this for real?  We sure could use such an option, since it would
>help immensely with our final design.


No, you can't put the bitstream into the EPLDs.  There are two options that are
open to you however:
  1.  Use a hardwire part, which is a mask programmed version of the SRAM FPGA. 
      Since this has to be done in fabrication of the part, it only makes sense 
      if you volume supports the nre.

  2.  Assuming you used the unified libraries, you can change the library and
      to the EPLD you are targeting and re-run PPR.  This won't get you the
      same timing or layout, but it is better than starting from scratch. 
      If your design is tight in terms of performance or size, you may need to 
      do some redesign to tailor it to the EPLD architecture to improve it.  
      While not a magic cure-all, the use of the unified library can be 
      helpful in circumstances like yours.
-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930    FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital hardware design firm specializing in 
obtaining the maximum performance from FPGAs.  Services include complete 
design, development, simulation, and integration of these devices and the 
surrounding circuits.  We also evaluate, troubleshoot, and improve existing
designs.  Please call or write for a free brochure.


Article: 1647
Subject: Re: external connections for efficient internal routing
From: Yuce Beser <yuce@sh.bel.alcatel.be>
Date: 10 Aug 1995 12:45:08 GMT
Links: << >>  << T >>  << A >>
george@cmf.nrl.navy.mil (George Schmitt) wrote:
>
>
>Suppose I have an FPGA (xilinx 4005 specifically) with a 32
>bit data path entering and a 16 bit data path exiting.  Data
>enters, is "processed" and then exits.  The processing is
>nothing more than a few pipelined registers and perhaps some
>bit shifting and masking.  Would the internal routing of the
>design be more efficient if the external connections were 
>very regular (i.e. 16 IPADs clustered near each other and 
>16 OPADs clustered near each other) or irregular (PADs just
>"randomly" placed all around the chip).

If you have critical time constraints that are difficult to be achieved, then
it is better to specify these time constraints and leave the placement of IOs
to the router. For some designs, it is not possible to satisfy both the time
constraints and fixing the locations of IOs. If you leave it to the router, it
usually ends up placing the data bus irregularly, and ends up with better
delays. But, first I would try to achieve both, as regularity (as you define)
helps board design be simple, and testing easier.


Yuce Beser
"speaking for myself"



Article: 1648
Subject: EDA Newsgroup Archive Via WWWeb
From: josedc@teleport.com (Jose De Castro)
Date: 10 Aug 1995 05:45:48 -0700
Links: << >>  << T >>  << A >>

Greetings!

I've set up an archive of some EDA related newgroups which can be browsed 
and searched via a WWWeb browser (e.g. Netscape or Mosaic) at the following 
URL (Uniform Resource Locator):

    http://vhdl.org/~josedc/cgi/fetch.cgi

The archive was started in July and includes the following newsgroups (of
which comp.lang.vhdl is currently the most active):

       comp.arch.fpga 
       comp.cad.cadence 
       comp.cad.synthesis 
       comp.lang.verilog 
       comp.lang.vhdl 
       comp.lsi.cad 
       comp.sys.mentor

This service is a personal contribution to the internet community and 
any feedback would be appreciated, especially if it was helpful in some
situation or if it could be improved in some way.  

My usual disclaimer is that this is NOT an official service of VI (VHDL
International) or VIUF (VI User Forum) or Mentor Graphics (my employer)
and although this service could not exist without their support and
encouragement, you may assume that any mistakes or opinions are probably 
my own ... blah blah blah

Regards,
Jose  8')
-- 
Jose De Castro       | phone:+1(503)695-1139
Mentor Graphics Corp | mailto:josedc@teleport.com
ASIC Vendor Engineer | http://teleport.com/~josedc/


Article: 1649
Subject: Re: external connections for efficient internal routing
From: "David M. Zar" <dzar>
Date: 10 Aug 1995 13:19:09 GMT
Links: << >>  << T >>  << A >>
george@cmf.nrl.navy.mil (George Schmitt) wrote:
>
>

>...  Would the internal routing of the
>design be more efficient if the external connections were 
>very regular (i.e. 16 IPADs clustered near each other and 
>16 OPADs clustered near each other) or irregular (PADs just
>"randomly" placed all around the chip).


I have thought about this and have some similar designs I have done
that have this same kind of issue.  What I have found in my specific
cases is that if you let the tools randomly place ports, routability
goes DOWN.  I did not really expect this as I thought the tools might 
try to minimize routing congestion.  Alas, when I place the ports 
in a logical fashon, the number of routing resources went down, and
my delays went down, too!  All in all, I use random placement for a 
quick way to see if my design will have a chance of fitting and running
at speed, but then I take the time to think about pin assignments and
"do it right."

Just my $0.02

dave





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