Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 1725

Article: 1725
Subject: Re: Email Address of Xilinx
From: daveb@perth.DIALix.oz.au (David Brooks)
Date: 21 Aug 1995 08:09:40 +0800
Links: << >>  << T >>  << A >>
yadav@bhishma.cse.iitb.ernet.in (Navneet S Yadav) writes:

>Emanuel Fontes (efontes@telepac.pt) wrote:
>: Hello.
>: Does anyone can help find and Email address where i can place some doubts 
>: to Xilinx about Viewlogic version of their development system ?
>: Emanuel Fontes

>	join the xilinx users mailing list, send a request to 
>xilinx-users-request@sandia.gov with the following in the body of the
>mail

>	list:add your_email_address


>--
>cheers,
>							yadav

>email: yadav@cse.iitb.ernet.in			


Also, email to hotline@xilinx.com
I've found them very prompt & helpful in replying.

-- 
David R. Brooks <daveb@perth.DIALix.oz.au>    Tel/fax. +61 9 434 4280
PGP public key via finger or keyservers
Public key fingerprint:  20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34 


Article: 1726
Subject: Any one using synthesizable HDL megacells ?
From: kirani@cinenet.net (kayvon irani)
Date: 21 Aug 1995 01:03:23 GMT
Links: << >>  << T >>  << A >>

	Hi every one:

	I'd like to find out if any one out there has tried the path of

	Megacell(Verilog/VHDL) -> FPGA -> Gate Array. If so, please share

	your experience by posting a short message. Thanks very much.

p.s. ( Megacells are synthesizable HDL codes for such components as UARTs,
       interrupt controllers, micro-controllers, DSPs, etc.)

	Kayvon Irani
	H/W Design Engineer
	Lear Astronics 

	kirani@hollywood.cinenet.net



Article: 1727
Subject: Re: List of FPGA Based Computing Machines
From: wannema@bonsai (Markus Wannemacher)
Date: 21 Aug 1995 11:21:47 GMT
Links: << >>  << T >>  << A >>
Jon Gunnar Solheim (jon@idt.unit.no) wrote:

: Hello.

: Do any of you know the new url for the list of FPGA Fased Computing
: Machines? 

: The old url was 'http://bongo.cc.utexas.edu/~guccione/', but my web-client
: complains, and says that the server (bongo.cc.utexas.edu) doesn't have a
: DNS entry.

The new url:

  http://www.io.com/~guccione/HW_list.html


------------------------------------------------------------------------
  @@        @@                                Markus Wannemacher
 @@@        @@@     @@@@@@        @    @      FernUniversit"at Hagen
@@@@        @@@@    @       @@@   @    @      LG Informationstechnik
@@@@  @@@@  @@@@    @@@@   @   @  @    @      LGZ, Profilstr. 10b
 @@@  @@@@  @@@     @      @@@@@  @    @      D-58084 Hagen, Germany
  @@@@@@@@@@@@      @      @      @    @      phone  +49 2331 987 4547
   @@@@@@@@@@       @       @@@    @@@@       fax:   +49 2331 987 375

Internet:  E-Mail:       Markus.Wannemacher@FernUni-Hagen.De
           WWW:          html://www.fernuni-hagen.de/www2bonsai/IT/team/wm.html
           talk:         wm@{tokyo|tenno}.fernuni-hagen.de
------------------------------------------------------------------------



Article: 1728
Subject: Need Help-FPGA Dev/Des.Eng.
From: amaraju@onramp.net (eddie amara)
Date: Mon, 21 Aug 1995 09:09:04 -0500
Links: << >>  << T >>  << A >>
      

FPGA Development Engineer

Responsibilities:Development of FPGA architecture and of the integrated
circuits that implement the architecture.Specific resposibilities include
working with FPGA software developers to ensure that the architecture can
be effectively exploited by the software and working with the marketing
organization to understand the needs of the customers.

Skills/Exp.:Understand the FPGA architecture trade-off.Good understanding
of full custom circuit design,System knowledge and logic design.

Education:PhD/MS in EE/CS/Physics and at least 3 years exp.

Location:Allentown,PA.

Salary:$50 to $80K + 12% bonus

NO NEW GRADS OR THOSE WITH ONLY UNIVERSITY WORK EXPERIENCE,THANKS.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1729
Subject: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 21 Aug 1995 09:16:07 -0500
Links: << >>  << T >>  << A >>
                        Prestigious Research Labs!!!!

Join one of the fastest growing divisions of this Fortune 50 Corp. FPGA !!!!!

FPGA Applications Engineer-Owns the complete implementation of the
design.Supports the FAE and ultimately responsible for having the design
work in the customers system.

Other resposibilities-Customer design win support.
                      Support customers and FAE with problem designs
                      Contribute to regional tag teams
                      Periodically visit customer base
                      Act as a Hardware or CAD platform champion
                      Customer and FAE training   
                      Apps notes  
                      Documentation

Skills/Exp-System logic design 
           Programmable logic
           FPGAs
           Schematic capture tools
           FPGA place and route tools
           Good communication and writing skills

Education-BS or MS in EE or CS and 5 years of system and or logic design
will be considered.      

Salary-$50 to $70 +12% bonus

Location--Allentown,Pa.


no new grads or those withonly university work,thanks.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1730
Subject: Help Needed-Technical Marketing Eng.FPGA-Allantown,Pa.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 21 Aug 1995 09:31:57 -0500
Links: << >>  << T >>  << A >>
                                 FORTUNE 100

Technical Marketing Engineering position in the FPGA product family in the
areas of strategic marketing and product development.  Will participate in
FPGA activities  including the identification of target applications in
response to customer input. Perform the FPGA implementation and
corresponding documentation for the target applications.
Publish/participate in application notes,product briefs,data sheets and
other documentation.

Job Requirements-Solid understanding of system logic design using
programmable logic,FPGAs,schematic capture tools, FPGA place/route
tools,and logic synthesis. Good interpersonal communication and writing
skills. 

At least 3 years of system and/or logic design experience. 3 years
experience with popular FPGA products such as Xilinx,Altera,Actel or
Quicklogic devices.

Education-BSEE or BSCS 

Salary-50 to 70K + 12% Bonus

Location-Allentown,Pa.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1731
Subject: Help Needed-FPGA Technical Engineer-Allentown,Pa.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 21 Aug 1995 09:32:48 -0500
Links: << >>  << T >>  << A >>
                                  Fortune 100

Technical Engineering position in FPGA product family in the Systems
Integration Group supporting  the FPGA product family and its CAE design
kits. 

Responsibilities include the integration and testing of 3rd party CAe
design kits,including the development of test cases, verification of
libraries and design flows.

Must be experienced in synthesis and schematic capture,functional and
timing simulation using popular 3rd party CAE tools (Synopsys, Verilog,
Mentor,VHDL) and in logic verification methods.FPGA design experience
strongly desirable. FPGA architecture knowledge or programming skills a
plus. Strong technical,interpersonal communication, and writing skills.

At least 3 years experience.

Education-BS or MS in EE or CS.

Location-Allentown,Pa.

Salary- 50 to 70K + 12% Bonus

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1732
Subject: Help Needed-FPGA Product Engineer-Allentown,Pa.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Mon, 21 Aug 1995 09:35:15 -0500
Links: << >>  << T >>  << A >>
                              FORTUNE 100

Product Engineering position in FPGA product family supporting 3rd party
CAE design kits.

Responsibilities include development, integration, testing, delivery,
documentation, and support of FPGA Product family. Opening are in Synopsys
and Cadence/Verilog.

Experience in schematic capture,functional and timing simulation, and
synthesis. Knowledge of netlist formats,simulation modeling, and awk/perl.
FPGA design experience desirable.  Strong technical,interpersonal
communication, and writing skills. At least 3 years experience.

Education-BS or MSEE or CS

Salary-50 to 70K + 12% Bonus

Location-Allentown,Pa.

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1733
Subject: Altera EPM9560 device availability
From: klindwor@tech17.informatik.uni-hamburg.de (Andre Klindworth)
Date: 21 Aug 1995 14:43:00 GMT
Links: << >>  << T >>  << A >>

Hello everybody,

We finished a commercial design project some weeks ago which
uses an Altera CPLD from the new MAX9000 series.
PCB-prototypes are allready in fabrication, but we have a
hell of troubles in getting the Altera Chip. The Altera people
tell us that the devices we need are available with no problems,
but the distributors tell us that the devices are not yet available.
Thus, we are trapped.

Therefore, I would like to ask if anybody out there knows where to obtain
an EPM9560 chip. We need it in the 208-pin QFP package, speed-grade 25 ns
(industrial) or 20 ns (commercial) or may even provide the device.
Naturally, we would prefer to obtain the in-circuit programmable
variant, but there have been reports that the first devices of the
EPM9560 had an error and thus did not have the in-circuit reprogrammablity
feature and such a device would be ok too.

And we need it REALLY URGENTLY !!!!!!!!!!!

Any help, pointers or suggestions appreciated.
-- 
-----------------------------------------------------------------------
Andre' Klindworth                   Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de  Vogt-Koelln-Str.30, D-22527 Hamburg
Phone: +49 40 54715-501, Fax: -397  Germany


Article: 1734
Subject: Re: List of FPGA Based Computing Machines
From: guccione@io.com (Steve Guccione)
Date: 21 Aug 1995 12:18:59 -0500
Links: << >>  << T >>  << A >>
Sorry.  I've been meaning to post the new URL, but wanted to wait
until I was sure I would be at this new site for a while.

Since I am no longer at University of Texas at Austin, I have moved
the list (and the on-line bibliographies and my personal pages) to
www.io.com, a commercial provider.  The URL for the List of FPGA Based
Computing Machines is:

   http://www.io.com/~guccione/HW_list.html

Please update your links.

Thanks, and sorry for all of the recent URL changes.  Most were due to
changes in the UT system.

-- Steve
-- 8/21/95



Article: 1735
Subject: Re: Simulation not matching lab results
From: coffey@iol.ie (Aedan Coffey)
Date: 21 Aug 1995 18:41:26 GMT
Links: << >>  << T >>  << A >>
There are two things I'm aware of that can cause a XIlinx device to
behave very differently from Xdelay's predictions:

1	We have seen in excess of 20nS being added to a single net by the
	tie function in makebits. Try generating an LCA file after makebits
	and running xdelay on that. Makebits with the -t option will
	not tie unused routing resources if this does turn out
	to be the problem.

2	Xilinx spec their devices at 85C junction temperatature, xdelay
	and ppr also assume this. It's not hard to exceed this temperature
	even in normal use. Does chilling the device help?

Hope this helps.

		Aedan Coffey.

	Toucan Technology Ltd, Galway, Ireland.


Article: 1736
Subject: Re: Design protection
From: jackg@downhaul.crc.ricoh.com (Jack Greenbaum)
Date: 21 Aug 1995 19:07:22 GMT
Links: << >>  << T >>  << A >>

In article <1995Aug18.215119.1558@super.org> john@vcc.com (John Schewel) writes:
   I would like to introduce another angle to the subject of 
   obscuring code.....
[...]
   With the coming of reconfigurable computing, it is quite possible that
   designs will come from individual creativity and not a contract. It is 
   this case I wish to explore.
[...]
  With the introduction of Hardware Objects(HO) (digital designs to be included
   in an application program for 'hardwiried acceleration')  used on
   reconfigurable computing systems, we anticipate many individuals designing
   useful functions to be used like 'c' libraries. In these cases, the 'customer'
   would not be interested in 'source code' but rather useability. 

Not allowing the customer to modify a "hardware object" for a
reconfigurable computing environment degrades the usefulness of such a
platform. Without the ability to change the interface to such library
blocks your design will suffer. 

[...]
   There will be in the coming year(s) a new opportunity for reusable functions
   to have general market value.  To protect the intellectual property one can
   certainly place a copyright label within the design, but it would seem that
   some form of incryption would be useful. I am not only speaking of VHDL, but
   verilog, schematic etc. designs. 

   Are there any comments on this ?

I don't see what difference a reconfigurable platform make with regard
to this issue. When you licence for a software library, sometimes you
get source, sometimes you don't. Same thing with a hardware
library. 



Note that you can get a public domain source code implementation of libc
from the Free Software Foundation.
--
Jack Greenbaum -- Research Engineer, Ricoh California Research Center
---------------------------------------------------------------------
Digital: jackg@crc.ricoh.com   |  http://www.crc.ricoh.com/~jackg
---------------------------------------------------------------------
Analog:  (415) 496-5711 voice  |  2882 Sand Hill Rd. Suite 115
         (415) 854-8740 fax    |  Menlo Park, CA 94025-7002
---------------------------------------------------------------------
-- 
Jack Greenbaum -- Research Engineer, Ricoh California Research Center
---------------------------------------------------------------------
Digital: jackg@crc.ricoh.com   |  http://www.crc.ricoh.com/~jackg
---------------------------------------------------------------------


Article: 1737
Subject: Re: FPGAs with embedded RAM
From: leow@uclink.berkeley.edu (Ka-Chung Wong)
Date: 21 Aug 1995 20:42:10 GMT
Links: << >>  << T >>  << A >>
In article <1995Aug18.182926.424@decus.org.nz>,
 <granville@decus.org.nz> wrote:
>In article <1995Aug16.203135.24706@super.org>, <GCAT@dorval.mpbtech.qc.ca> writes:
>> Hello,
>> 
>> it impact on percentage utilization in the logic portion of the 
>> design?  How do the tools handle RAM?
>> 
>> Any input welcome....           Thanks
>> 
>> 

> Also check the INtel FLexLOGIC parts - the cells in these can be 128x8
>RAM, I believe.
>
>

Actually, Intel FlexLogic is now called ALTERA FlashLogic.  Altera aquired 
all Intel programmable logic business....

If you ask me, Actel's 3200DX is way too small, though they claim a very
fast speed.  Their SRAM module can be configured into 64x4 or 32x8 mode,
The biggest family member, A32400DX, has only 16 such module.

To implement a 8kbit LUT, you probably wanna look at Altera's Flex10K,
which has up to 24Kbits... of RAM.

That's my three cents worth.

Leo


Article: 1738
Subject: Looking for Good Introductory Book on FPGAs and ELPDs
From: clerk@igs.net (Don Clerk)
Date: 22 Aug 1995 03:34:04 GMT
Links: << >>  << T >>  << A >>
I am looking for a good introductory textbook on FPGAs and ELPDs suitable
for a graduate electrical engineer who wants to do design work with
embedded controllers.

I would appreciate any suggestions anyone has.

Thanks
Don 



Article: 1739
Subject: Re: Looking for Good Introductory Book on FPGAs and ELPDs
From: devb@jazzmin.vnet.net (David Van den Bout)
Date: 22 Aug 1995 07:22:09 -0500
Links: << >>  << T >>  << A >>
Don:

If you are looking for a good introductory book on FPGAs and PLDs, then
I am going to recommend the following:

"Field Programmable Gate Arrays" by Oldfield and Dorf.
   ISBN 0-471-55665-3

"FPGA Workout" by Van den Bout.
   ISBN 0-964-21870-4

The second book is mine, of course, so all claims of impartiality are
null and void.  You can get more information about it by ftp'ing to
ftp.vnet.net and changing to directory pub/users/xess.


-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 1740
Subject: Re: FPGAs with embedded RAM
From: dlanza@kobold.ess.harris.com (David Lanza)
Date: 22 Aug 1995 16:33:38 GMT
Links: << >>  << T >>  << A >>
In <1995Aug16.203135.24706@super.org> <GCAT@dorval.mpbtech.qc.ca> writes:


I have used Xilinx FPGAs extensively and am very satisfied with their
overall performance.  I have only used the RAM features once, but with no
no problems.  Each CLB can be used to implement logic (Up to 9 inputs and
3 outputs each) or used as up to 32 bits of RAM, but not both.  I hope
this helps.  Let me know if you need more information, I'll try to point
you in the right direction.

Dave Lanza
dlanza@harris.com



>Hello,

>My current FPGA application uses Actel FPGAs with small external look-
>up tables using about 2kbits to 8kbits of RAM.  I am now considering 
>options for my second generation and am looking at FPGA families with 
>on-board RAM.

>As far as I can determine, my options are AT&T and Xilinx, whose 
>PLCs and CLBs can be used as small RAM blocks.  I have also read that 
>Altera is cooking up a new family with embedded diffused SRAM blocks.

>Does anyone know if this new family is out?  As anyone used it? 

>Does anybody have any experiences to share regarding the use of RAM 
>in Xilinx and AT&T?  Any problems with routability, timing?   Does 
>it impact on percentage utilization in the logic portion of the 
>design?  How do the tools handle RAM?

>Any input welcome....           Thanks


>Catherine Gyselinck                    ----------------------------
>MPB Technologies                       |  Speak softly but carry  |
>gcat@dorval.mpbtech.qc.ca              |  a +6 two-handed sword   |
>tel: (514) 683-1490                    ----------------------------
>fax: (514) 683-1727
--

  David Lanza
  dlanza@harris.com


Article: 1741
Subject: Re: Any one using synthesizable HDL megacells ?
From: taub@cirrus.com (Ed Taub)
Date: 22 Aug 1995 17:08:25 GMT
Links: << >>  << T >>  << A >>

I have taken an HDL portion of an IEEE 1284 printer controller ASIC I
worked on for Cirrus Logic and synthesized it to Xilinx XC4013 for
test.

It worked great. I reported my results at Design Supercon'95. I used
Synopsys FPGA compiler and embedded the single Xilinx on a PC ISA
prototype board for test. It saved numerous ASIC tape-outs. 

I have no doubt that synthesizing cores would work, as long as the
core would fit in a single FPGA.  Partitioning across multiple FPGAs
makes the task more difficult.

Ed




Article: 1742
Subject: Synario/OrCad/Viewlogic
From: mikelot@ix.netcom.com (mike lottridge)
Date: Tue, 22 Aug 1995 20:30:04 GMT
Links: << >>  << T >>  << A >>
if you've used any of the above three tools, I'd appreciate some pro's
and con's on what you found...

thanks!




Article: 1743
Subject: CADmazing Web Page Update
From: Web Admin <webadmin@cadmazing.com>
Date: 22 Aug 1995 23:02:08 GMT
Links: << >>  << T >>  << A >>
CADmazing Solutions would like to announce a major update to our WWW site.
We've added a new consultants registration form for job seekers in ASIC design
to fill out and submit to us. We've also created a job listings page. Our site
also contains a comprehensive list of DA-Related links, a company overview, and
information about visiting the Silicon Valley. Please visit us at:

http://www.cadmazing.com/

Web Maste (webadmin@cadmazing.com)
CADmazing Solutions, Inc., Direct Number: (408) 653-1400
--------------------------------------------------------
Specialists in the IC EDA Marketplace - CAD and Design Services
2100 Walsh Ave., Suite C-1, Santa Clara, CA 95050

World Wide Web : http://www.cadmazing.com/cadmazing



Article: 1744
Subject: Re: Synario/OrCad/Viewlogic
From: rxjf20@email.sps.mot.com (Doug Shade)
Date: 23 Aug 1995 15:59:12 GMT
Links: << >>  << T >>  << A >>
In article <41debk$86c@ixnews5.ix.netcom.com>
mikelot@ix.netcom.com (mike lottridge) writes:

> if you've used any of the above three tools, I'd appreciate some pro's
> and con's on what you found...

Depends on what you want to do.  Perhaps you can let us know the type
of things you want to do....

Doug Shade
rxjf20@email.sps.mot.com


Article: 1745
Subject: Quicklogic/Cypress/Warp3
From: msnook@armltd.co.uk (Mark Snook)
Date: 24 Aug 1995 12:14:40 GMT
Links: << >>  << T >>  << A >>
I have been looking for a cheap way to evaluate Quicklogic pASIC parts
using VHDL. Quicklogic have a $99 evaluation kit, but it doesn't
currently support VHDL (coming soon).

I notice today that Cypress also has similar parts. Are they
identical? If so, Cypress says that the pASIC parts are supported by
Warp3. Has anyone any experience of designing for these parts using
Warp3. I have seen various comments about Warp posted on this
newsgroup relating to the subset of VHDL supported. I don't care if
VHDL is not fully supported, only whether Warp provides all that is
required to get an efficient design completed. 

Any comments and what is the approx. price?

Mark Snook
(mark.snook@armltd.co.uk)


Article: 1746
Subject: Re: Synario/OrCad/Viewlogic
From: mikelot@ix.netcom.com (mike lottridge)
Date: Thu, 24 Aug 1995 15:56:16 GMT
Links: << >>  << T >>  << A >>


rxjf20@email.sps.mot.com (Doug Shade) wrote:

>In article <41debk$86c@ixnews5.ix.netcom.com>
>mikelot@ix.netcom.com (mike lottridge) writes:

>> if you've used any of the above three tools, I'd appreciate some pro's
>> and con's on what you found...

>Depends on what you want to do.  Perhaps you can let us know the type
>of things you want to do....

sorry -- that was a bit vague! i'm looking for tools for cpld/fpga
design that support a mix of schematic entry + vhdl

>Doug Shade
>rxjf20@email.sps.mot.com




Article: 1747
Subject: Orca FLoor planning tool
From: husby@fnal.gov (Don Husby)
Date: 24 Aug 1995 16:04:26 GMT
Links: << >>  << T >>  << A >>
While struggling with routing an ORCA design, I wrote a simple floor planning 
tool for NeoORCA parts.  You can get it (along with a bunch of other 
FPGA-related tools) via anon-ftp at 
    esesrv0.fnal.gov:/pub/docs/xilinx/awks.zip

See the read.me file in that directory for a short description of other 
tools.

Also, the files grid.ps and orca_pln.ps contain layout sheets that can help 
with laying out and routing a design.

The .man page for the new tool follow....

=========================================
xplace:
  Extend the syntax of the NeoCad preference file (*.prf) to allow floor
planning of arrays and data paths.  Xplace reads a script (*.xpl) that
specifies placement in terms of patterns, tables, and expressions.  It scans
the design file for PFUs, Tbufs, and IOBs that match these specifications and
puts placement directives in the preference file.

For example, a placement directive such as:

PFU REGISTER%d/Bit%d  Row[ $1 * 2 ], Col[ 8 - $2 ]

would place any PFU with the name REGISTERx/BITy into location (2x,8-y).
(See below for a complete description of the sysntax of an .xpl file)

Usage:
  ncd2eq ncdfile		! Must first create data files with ncd2eq
  xplace ncdfile		! extension is optional

Example:
  ncd2eq tst.ncd
  xplace tst

Files:
  *.xpl				! Xplace script
  *.prf				! Preference file - read and written by 
xplace
  *.pad				! Pad summary (generated by ncd2eq)
  *.tri				! Tbuf summary (generated by ncd2eq)
  *.blk				! Block summary (generated by ncd2eq)
  %XACT%\awks\xplace.exe	! Executable
  %XACT%\awks\xplace.awk	! awk source code 
  %XACT%\awks\ncd2eq.exe	! Executable
  ncdread.exe			! Neocad ncd reader (Used by ncd2eq)
========================================

.xpl script Syntax:  Xplace recognizes the following directives:

PFU <pat> <row>, <col>		! Place PFUs matching pattern <pat> at 
locations
				! specified by expressions <row> and <col>.
PAD <pat> <loc>			! Place Pads
HLL <pat> <row>, <col>, <buf>	! Place TBUF as horizontal long line
HHL <pat> <row>, <col>, <buf>	! Place TBUF as horizontal half line
VLL <pat> <row>, <col>, <buf>	! Place TBUF as  vertical  long line
VHL <pat> <row>, <col>, <buf>	! Place TBUF as  vertical  half line

SET <var> <Const>		! Set a variable to a constant.
TBL <name> <V0> <V1> ... <Vn>	! Create a lookup table with indices 0 to n
MAP <name> <I1..In> = <V1..Vn>	! Create a table with indices I1 to In.

Patterns:
  A pattern is a full "Unix" regular expression which matches block names 
from
the schematic.  The pattern may contain sub-patterns enclosed in parentheses 
which match, for example, bit numbers or register numbers.  When one of these 
sub-patterns matches a field in a block name, the contents of that field are 
placed in the reserved variables $1, $2, ... $n.  These variables can be used 
in the location expressions (e.g. <row>).
  In addition to regular expression syntax, two special sub-patterns are
defined:
     %d is defined as ([0-9]*) and matches any number.
     %s is defined as ([A-Za-z][A-Za-z0-9_]*) and matches any name.

Expressions:
  Locations are specified as expressions.  These are pretty much standard 
arithmetic expressions which use the operators +,-,*,/,%, and ().  They 
operate
on numbers, strings, variables, or tables.  They can return a number or a 
string.

Variables:
  Variables can be set using the SET directive, or they can be set as a part 
of
pattern matching.  The special variables $1..$n reference sub-patterns that 
were matched by <pat>.  When used in expressions, a variable should be
referenced with a $.

Tables and Maps:
  These are lookup tables.  They are useful for creating complicated 
placements
which are difficult to express as equations.  They also map an arithmetic
expression to a text value (or vice-versa).  There are two forms of table
delcaration.  The TBL form simply assigns a list of values using numeric
indices.  The MAP form allows indices to be specified as any arbitrary number
or string.  Table values are referenced with square brackets:  Name[Index].

PFUs:
  PFUs are placed by specifying a single letter for row and column.

PADs:
  PADs are placed by specifying a pad number.

TBUFs:
  TBUFs are placed on a particular long-line.  At each site (ROW,COL) there 
are
four long-line TBUFs and four half-line TBUFs which can drive either
horizontal or vertical lines.  The <buf> field must be a number from 0 to 3 
to
specify which line to drive.  Note that the number refers to a line and NOT a
TBUF number.  This compensates for the fact that long-lines in the ORCA chip
are twisted between blocks.

Example:
  The following example uses most of the features of xplace.  The imaginary 
design consists of four "PORTS", each of which has a 32-bit wide RAM, a 
32-bit adder which puts its result on a common 32-bit tristate bus.  The 
placement is horizontal in grey-code order: PORTA, PORTB, PORTD, PORTC.

--- Begin test.xpl ---
TBL PRow     K L M N O P Q R		# Rows - 4 bits per row = 32 bits
MAP AddCol   A B D C = F H J L		# Columns to place Adders
MAP RamCol   A B D C = E G I K		# Columns to place Ram cells

# Place RAM cells of the form PORTx/RAM/Qy where y=0,4,8...28
PFU PORT%s/RAM/Q%d       PRow[$2/4],  RamCol[$1]

# Place ADDer cells of the form PORTx/ADD/NIBy where y=0,1,2..7
PFU PORT%s/ADD/NIB%d     PRow[$2],    AddCol[$1]

# Place even TRIstate buffers on horizontal long lines.
HLL PORT%s/TRI32/BIT([123]?[02468])$ PRow[$2/4],  AddCol[$1], $2%4

# Place odd buffers on horizontal half lines.
HHL PORT%s/TRI32/BIT([123]?[13579])$ PRow[$2/4],  AddCol[$1], $2%4



Article: 1748
Subject: Re: Looking for Good Introductory Book on FPGAs and ELPDs
From: sbaker@best.com
Date: 24 Aug 1995 18:06:48 GMT
Links: << >>  << T >>  << A >>
>   clerk@igs.net (Don Clerk) writes:
>  I am looking for a good introductory textbook on FPGAs and ELPDs suitable
>  for a graduate electrical engineer who wants to do design work with
>  embedded controllers.
>  
>  I would appreciate any suggestions anyone has.
>  
>  Thanks
>  Don 
>  
>  
>>>>


The best such book and also a good continuing reference is "Field Programmable Devices" by Stephen D. Brown (U. Toronto).  It's 
172 pages and only $29.50 plus shipping.  It was published this April.

We have found this of great value to novices and experts.

Call Debbie Wallace at 408-356-5119 to order or get more information.  You can also email at sbaker@best.com.

Debbie


Article: 1749
Subject: Re: Quicklogic/Cypress/Warp3
From: barry@sr.hp.com (Barry Brown)
Date: 24 Aug 1995 18:11:04 GMT
Links: << >>  << T >>  << A >>
Mark Snook (msnook@armltd.co.uk) wrote:
: I have been looking for a cheap way to evaluate Quicklogic pASIC parts
: using VHDL. Quicklogic have a $99 evaluation kit, but it doesn't
: currently support VHDL (coming soon).

: I notice today that Cypress also has similar parts. Are they
: identical? If so, Cypress says that the pASIC parts are supported by
: Warp3. Has anyone any experience of designing for these parts using


Cypress is the foundry for QuickLogic, so I believe they are identical.
The $99 thing from Cypress is Warp2 (Warp3 costs more), and I don't
believe that one supports the FPGA products.




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search