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Messages from 1800

Article: 1800
Subject: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
From: driscoll@src.honeywell.com (Kevin Driscoll)
Date: 4 Sep 1995 18:16:15 -0500
Links: << >>  << T >>  << A >>
> synopsis:  Eddie post an in-appropriate article to the group
>            John warms up a flame thrower, and sets it to medium
>            Eddie shows total lack of understanding of why he is being toasted
>            Philip jumps in to defend poor John (got to protect these farmers)
             Kevin too (who shouldn't, but can't resist spiking a floater)

>> amaraju@onramp.net (eddie amara) writes:
>> Mind your own business pal, I have a job to do and yours is not to get
>> into my business. Yes, we do look for somebody for a position  and that
>> position is usually better than what they have now, have a problem with
>> that? You wish you can make the money us headhunters make.

If you are making so much money, why don't you try earning it instead of
using this netiquette abusing "shortcut"?  From your postings, we can
see that you are a lazy money grubber.  These are just the characteristics
that would inspire readers of this newsgroup to trust you in a career deal.


Article: 1801
Subject: looking for fpga burn and PCB design house in BA
From: muzok@msn.com (muzo)
Date: Tue, 05 Sep 1995 03:46:38 GMT
Links: << >>  << T >>  << A >>
hi,

I am designing a simple test PCI card with a xilinx  fpga on it. I am not sure
which device I'll be using yet. I am looking for a design house which can burn
my fpga desing (synthesised (sp?) using exemplar) and design a the PCB board
for me (including manufacturing a few sample cards). I am looking for pointers
on such places in bay area and also I am open to suggestions on fpga
programmers, PCB manufacturers from my film (is that the right term ?) etc.

thanks ahead for any/all help

muzo

PS: I am relatively new at this stuff so add any helpful suggestions you might
have for a beginner.

standard disclaimer



Article: 1802
Subject: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
From: weigand@stimpy.eecis.udel.edu (Steven Weigand)
Date: 5 Sep 1995 04:18:25 GMT
Links: << >>  << T >>  << A >>
In article <amaraju-0409951515320001@dal17.onramp.net>,
eddie amara <amaraju@onramp.net> wrote:
>Mind your own business pal, I have a job to do and yours is not to get
>into my business. Yes, we do look for somebody for a position  and that
>position is usually better than what they have now, have a problem with
>that? You wish you can make the money us headhunters make.
>
>
>In article <DE8nrM.py@world.std.com>, jcooley@world.std.com (John Cooley) wrote:
>
>:If you want to blow off this headhunter and deal with the company directly,
>:it's AT&T in their Microelectronics Division.  I even have the e-mail address
>:somewhere for these people.  Remember: Headhunters are only interested in
>:getting *somebody* in this job so they can collect a fee -- they don't give
>:a damn if it's you or anyone else.  As long as they collect their fee,
>:they're happy.
>:                           - John Cooley
>:                             Part Time EDA Consumer Advocate
>:                             Full Time ASIC, FPGA & EDA Design Consultant

Heh.  Well,  recruiters have been able to get me in touch with people
that are able to hire me a lot more than I've been able to do alone,  so
let's not be too hard on them.  Like Mr. Amara said,  they perform a 
valid function,  and they deserve the money they get.  I personally
wouldn't want to be a recruiter,  since I'm having enough trouble 
in life worrying about finding *myself* a job,  and it's probably real
tough competition anyway.  

Ciao for now,
  - Steve Weigand
    (weigand@ee.udel.edu)



Article: 1803
Subject: Re: Help Needed-FPGA Apps Eng.-AllentownPA.-Recruiter
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Tue, 05 Sep 95 07:05:19 GMT
Links: << >>  << T >>  << A >>
In article <1995Sep5.190326.2216@super.org>,
   schott@super.org (Brian Schott) wrote:
>Geeze Eddie, 'Tis better to keep silent and be thought a fool than to
>speak and remove all doubt. 
>
>Personally, as someone with: 1) FPGA application experience and 2) a
>contract expiring at the end of the year, I *was* considering applying
>for the position.  I did know that the position is with AT&T (FPGA +
>Allentown, PA = AT&T).  However, since you responded to John with
>"mine's bigger than yours" (doubtful) and clearly view applicants as
>losers who bring you money, why should I bother?
>
>Had you responded with "I provide X, Y, and Z services that are
>valuable to applicants", you might have engendered some respect.  In
>the future I suggest you think up some benefits of your leechcraft.
>
>Brian Schott
>
>In article <amaraju-0409951515320001@dal17.onramp.net>,
>eddie amara <amaraju@onramp.net> wrote:
>>Mind your own business pal, I have a job to do and yours is not to get
>>into my business. Yes, we do look for somebody for a position  and that
>>position is usually better than what they have now, have a problem with
>>that? You wish you can make the money us headhunters make.
>>
>>
Well, I'm not sure if comp.lang.vhdl is the right place for this stuff,
but I certainly know one headhunter I won't offend with my resume.  I'd
expect that would go for a lot of other poorly-positioned, poorly-paid
engineers that Eddie lives off of.

Erik


Article: 1804
Subject: ICCAD-95 Program and Forms Available at http://www.e2w3.com/iccad/
From: skmurphy@netcom.com (Sean Murphy)
Date: Tue, 5 Sep 1995 08:30:53 GMT
Links: << >>  << T >>  << A >>
   The ICCAD-95 WWW Site (http://www.e2w3.com/iccad/) Has the Complete
   Program, Conference Registration, Tutorial Registration, and Hotel 
   Reservation Forms On-Line. Deadlines are Fast Approaching--Register Now.

The 1995 International Conference on Computer-Aided Design (ICCAD-95) will
be held Sunday, November 5 through Thursday, November 9, at the Red Lion in
San Jose, California. The Conference is sponsored by the IEEE Computer
Society, the IEEE Circuits and Systems Society, and the ACM Special Interest
Group on Design Automation, in cooperation with IEEE Electron Devices
Society.

DEADLINES are fast approaching for grants, hotel reservations, and 
conference advance registration:
   Sept. 18: ICCAD-95 Grant Requests Due
   Oct. 6: Last Day to Reserve a Room at the Red Lion
   Oct 13: Last Day for Advanced Registration

The WWW Site contains forms and information for Grants, Reservations, and
Advanced Registration, as well as the complete text of the technical program
guide. There are also links to all of the sponsor's WWW sites, exhibitor
WWW sites, and information on events and activities in Silicon Valley.

Overview of Conference Schedule & Events:
Sun Nov. 5 : Early Registration 5-8pm in Red Lion Foyer
             ACM/SIGDA Mtg 5:30pm in San Juan/San Carlos Room
             (Panel on EDA Applications of Electronic Publishing follows)
Mon Nov. 6 : Technical Program 9am-5:30pm at Red Lion
             Evening Panel 6-7:30pm in the Thunderbird Ballroom: "Chief
             Technologists Tell All: What's Hot? What's Not? What's Next?"
Tue Nov. 7 : Technical Program 9am-5:30pm at Red Lion
             Dinner Party 7-10pm in the Red Lion Ballroom
Wed Nov. 8 : Technical Program 9am-5:30pm at Red Lion
Thu Nov. 9 : Tutorials Program 9am-5pm at Red Lion
             1. Practical Aspects of Formal Hardware Verification
             2. Hardware/Software Codesign of Embedded Systems
             3. Optimization Techniques for Low Power VLSI Circuits
             4. The Systematic Design of Asynchronous Circuits

______________________________________________________________________________
Sean Murphy, President, Leader-Murphy, Inc. (skmurphy@netcom.com 408 252-9676)
WWW-Enabled Applications and Methodology Consulting: "Knowledge, Refined from
Information Derived from Data, is the Fundamental Asset of the Enterprise"
URL: http://www.l-m.com/l-m.html & http://www.e2w3.com/
______________________________________________________________________________





Article: 1805
Subject: Re: Xilinx PROMs
From: stuart_clubb@bytech.win-uk.net (STUART CLUBB)
Date: Tue, 05 Sep 1995 13:58:00 GMT
Links: << >>  << T >>  << A >>

K>In <40d8s8$pod@ingate.adc.com>, swam@adc.com (Steve Swam) writes:
K>
K>>John Obenauf (John.Obenauf%aeup@msg.ti.com) wrote:
K>>: Does anyone know of who makes alternative devices to Xilinx's PROMs?  
K>>: Specifically interested in the 1765 deivce.
K>>
K>>Atmel makes a series of replacement parts.  They are also reprogrammable.
K>
K>
K>What Atmel parts are you referring to, specifically?
K>
I don't know about ATMEL parts, but AT&T (who make the ATT3000 series which
are a drop in replacement for Xilinx 3000 & 3100 series) make the following
parts:

ATT1736x
ATT1765x
ATT17128x

Where x is either blank or an 'A' for OTP parts or a 'F' for EEROM parts 
(reprogrammable !)

Available in 8 pin DIP (PD8), 8 pin SOIC (SO8) or 20 pin PLCC (M20)

Also available in commercial of industrial (-40 to +85 C) temp ranges.

Hope this is of some help
Stuart

---
 * PowerAccess 1.06 Taglines...one line freedom of speech!




Article: 1806
Subject: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
From: amaraju@onramp.net (eddie amara)
Date: Tue, 05 Sep 1995 09:21:10 -0500
Links: << >>  << T >>  << A >>
I do understand why John got on my case, its for cross posting in a disc
group. all he had to do was to ask and I would have stopped. Ours is a
very competitive businees and i must look for every angle I can to help me
be successful even if it means bending the rules a bit. I'm sure the
company any of ya'll work for looks for any advantage it takes to be
successful, thats all I was doing.

Eddie

In article <DE8nrM.py@world.std.com>, jcooley@world.std.com (John Cooley) wrote:

:If you want to blow off this headhunter and deal with the company directly,
:it's AT&T in their Microelectronics Division.  I even have the e-mail address
:somewhere for these people.  Remember: Headhunters are only interested in
:getting *somebody* in this job so they can collect a fee -- they don't give
:a damn if it's you or anyone else.  As long as they collect their fee,
:they're happy.
:                           - John Cooley
:                             Part Time EDA Consumer Advocate
:                             Full Time ASIC, FPGA & EDA Design Consultant
:
:===========================================================================
: Trapped trying to figure out a Synopsys bug?  Want to hear how 3443 other
: users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
: 
:      !!!     "It's not a BUG,               jcooley@world.std.com
:     /o o\  /  it's a FEATURE!"                 (508) 429-4357
:    (  >  )
:     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
:     _] [_         Verilog, VHDL and numerous Design Methodologies.
:
:     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
:   Legal Disclaimer: "As always, anything said here is only opinion."
:
:eddie amara <amaraju@onramp.net> wrote:
:>                        Prestigious Research Labs!!!!
:>
:>Join one of the fastest growing divisions of this Fortune 50 Corp. FPGA !!!!!
:>
:>FPGA Applications Engineer-Owns the complete implementation of the
:>design.Supports the FAE and ultimately responsible for having the design
:>work in the customers system.
:>
:>Other resposibilities-Customer design win support.
:>                      Support customers and FAE with problem designs
:>                      Contribute to regional tag teams
:>                      Periodically visit customer base
:>                      Act as a Hardware or CAD platform champion
:>                      Customer and FAE training   
:>                      Apps notes  
:>                      Documentation
:>
:>Skills/Exp-System logic design 
:>           Programmable logic
:>           FPGAs
:>           Schematic capture tools
:>           FPGA place and route tools
:>           Good communication and writing skills
:>
:>Education-BS or MS in EE or CS and 5 years of system and or logic design
:>will be considered.      
:>
:>Salary-$50 to $70 +12% bonus
:>
:>Location--Allentown,Pa.
:>
:>
:>no new grads or those withonly university work,thanks.
:>
:>-- 
:>Eddie Amara
:>SpencerSearch,Inc.
:>Voice 214-931-3060
:>Fax   214-931-8471
:>amaraju@onramp.net

-- 
Eddie Amara
SpencerSearch,Inc.
Voice 214-931-3060
Fax   214-931-8471
amaraju@onramp.net


Article: 1807
Subject: Re: Actel PCI App Note
From: victory@wwa.com
Date: 5 Sep 1995 14:24:27 GMT
Links: << >>  << T >>  << A >>
AT&T Microelectronics also can provide PCI code in VHDL.

Note that the AT&T ORCA part can meet all VHDL specs: clock to out,
clock setup, IV drive curves, etc.

Contact your local AT&T Microelectronics Representative, or call
1-800-372-2447 if you need to find out who that is.


DISCLAIMER:  Victory Sales represents AT&T Microelectronics in 
Illinois/Wisconsin/Indiana/Ohio.

                                __      __
Michael Duerr            ______ \ \    / / ______
Applications Engineer      _____ \ \  / / _____      Phone (708) 490 - 0300
                              ___ \ \/ / ___         Fax   (708) 490 - 1499
Victory Sales                    _ \  / _
1030 W. Higgins Rd, Suite 101       \/     Internet: victory@wwa.com
Hoffman Estates, Illinois 60195            ATT Mail: attme!attmail!victorysales




Article: 1808
Subject: FPGA to masked gate array conversion
From: tompkins@appliedmicro.ns.ca (Jim Tompkins)
Date: 5 Sep 1995 12:51:12 -0300
Links: << >>  << T >>  << A >>
Does anyone have experience with FPGA (e.g. xilinx) to masked
gate array conversions?  I know that a company called Orbit
Semiconductor offers this service.  Has anyone used it?
Does anyone know of any other companies offering a similar
service?

Thanks for any help.

Jim

--
Jim Tompkins
Hardware Designer            Internet : tompkins@appliedmicro.ns.ca   
Applied Microelectronics              Voice    : (902) 421-1250   
1046 Barrington Street                Fax      : (902) 429-9983  
Halifax, NS  CANADA B3H 2R1                                       


Article: 1809
Subject: Questionnaire for my Technical Writing class.
From: Karl Beil <kbeil>
Date: 5 Sep 1995 17:52:52 GMT
Links: << >>  << T >>  << A >>

Subject
_______

I'm a University of North Carolina at Charlotte computer engineering student.
At present I'm in a Technical Writing class. My assignment is to interview professionals so as to gather data on technical writing. =
The interviews I have to do are both face to face and via the net. The questionnaire will not be intrusive, any question you don't w=
ant to answer, don't answer.

Face to face interview
______________________

If you live and/or work in the Charlotte N.C. area, and would like to have a
face to face interview done, please E-Mail me and we can set up an appointment
at your convenience.

Responses
_________

Please E-Mail responses to kbeil@uncc.edu, or just click on kbeil above.

Questionnaire
_____________
1.   What is your profession?
2.   How long have you been in your profession?
3.   What is you highest level of education?
4.   What percentage of your time is spent writing and how many hours per week 
     this is?
5.   What type of writing do you do most often and what percentage of your time
     is spent on it?
	A) Second most often?
	B) Third most often?
6.   At what grade level do you do the above writing.
	A) Does the grade level change according the audience?
	B) Please list the grade levels you use and for which audience it
	   is used.  
7.   Has the amount of writing you have done increased or decreased as your rank
     increased, and by how much at each level?
8.   Do you expect the amount of writing you do to continue to increase or
     decrease as your rank increases? If so please explain. 
9.   Has your ability to write well helped you receive promotions? If so please 
     explain.
10.  Do you do most of your writing long hand, on a typewriter, or on a 
     computer?
	A)Please explain why?
	B)If you use a computer, what software do you prefer?



Thank you for answering these questions. 

Karl Beil
kbeil@uncc




Article: 1810
Subject: Re: Help Needed-FPGA Apps Eng.-AllentownPA.-Recruiter
From: schott@super.org (Brian Schott)
Date: Tue, 5 Sep 1995 19:03:26 GMT
Links: << >>  << T >>  << A >>
Geeze Eddie, 'Tis better to keep silent and be thought a fool than to
speak and remove all doubt. 

Personally, as someone with: 1) FPGA application experience and 2) a
contract expiring at the end of the year, I *was* considering applying
for the position.  I did know that the position is with AT&T (FPGA +
Allentown, PA = AT&T).  However, since you responded to John with
"mine's bigger than yours" (doubtful) and clearly view applicants as
losers who bring you money, why should I bother?

Had you responded with "I provide X, Y, and Z services that are
valuable to applicants", you might have engendered some respect.  In
the future I suggest you think up some benefits of your leechcraft.

Brian Schott

In article <amaraju-0409951515320001@dal17.onramp.net>,
eddie amara <amaraju@onramp.net> wrote:
>Mind your own business pal, I have a job to do and yours is not to get
>into my business. Yes, we do look for somebody for a position  and that
>position is usually better than what they have now, have a problem with
>that? You wish you can make the money us headhunters make.
>
>
>
>In article <DE8nrM.py@world.std.com>, jcooley@world.std.com (John Cooley) wrote:
>
>:If you want to blow off this headhunter and deal with the company directly,
>:it's AT&T in their Microelectronics Division.  I even have the e-mail address
>:somewhere for these people.  Remember: Headhunters are only interested in
>:getting *somebody* in this job so they can collect a fee -- they don't give
>:a damn if it's you or anyone else.  As long as they collect their fee,
>:they're happy.







Article: 1811
Subject: Re: FPGA to masked gate array conversion
From: walton@emc.com (John Walton)
Date: 5 Sep 1995 19:41:48 GMT
Links: << >>  << T >>  << A >>
In article <tompkins.810316022@appliedmicro.ns.ca>, tompkins@appliedmicro.ns.ca (Jim Tompkins) writes:
|> Does anyone have experience with FPGA (e.g. xilinx) to masked
|> gate array conversions?  I know that a company called Orbit
|> Semiconductor offers this service.  Has anyone used it?
|> Does anyone know of any other companies offering a similar
|> service?
|> 
|> Thanks for any help.
|> 
|> Jim
|> 
|> --
|> Jim Tompkins
|> Hardware Designer            Internet : tompkins@appliedmicro.ns.ca   
|> Applied Microelectronics              Voice    : (902) 421-1250   
|> 1046 Barrington Street                Fax      : (902) 429-9983  
|> Halifax, NS  CANADA B3H 2R1                                       

Xilinx has Hardwire. 


Article: 1812
Subject: Re: FPGA to masked gate array conversion
From: davem@hbmltd.demon.co.uk
Date: Tue, 05 Sep 95 21:55:00 XAC
Links: << >>  << T >>  << A >>

In article <42i95s$3r4@ns0.emc.com>, <walton@emc.com> writes:
> 
> In article <tompkins.810316022@appliedmicro.ns.ca>, 
tompkins@appliedmicro.ns.ca (Jim Tompkins) writes:
> |> Does anyone have experience with FPGA (e.g. xilinx) to masked
> |> gate array conversions?  I know that a company called Orbit
> |> Semiconductor offers this service.  Has anyone used it?
> |> Does anyone know of any other companies offering a similar
> |> service?
 
> Xilinx has Hardwire. 
> 
But it's expensive.  There are a number of more cost-effective solutions.  I 
used ASIC Solutions in Calfornia & was pleased with the results

============
Dave Mould



Article: 1813
Subject: Re: Altera's Max+Plus2 vhdl output, bad!
From: Jan Decaluwe <jand>
Date: 6 Sep 1995 08:25:34 GMT
Links: << >>  << T >>  << A >>
flxchen@smtp.dlink.com.tw (Felix K.C. CHEN) wrote:
>The VHDL output file of Altera's Max+PlusII conatins timing parameters,
>therefore, I'd like to simulate my design with Viewlogic's Powerview
>VHDL simulator, which is IEEE-compliant.
>
>Though the VHDL file passed the Vhdl analyzer, it could not be
>simulated.  The reason is that in the file there are configuration 
>statements missing.  Those instantiated components are unbounded!!!
>
>To think I use Exemplar's core to synthesize my VHDL into *.tdf.
>With VHDL in and VHDL out, I could have the familiar tools, without
>having to generate redundant schematic files, netlist files. etc.
>Now it seems that the interface between Max+Plus II and Powerview 
>is much worse than Altera advertises.
>

I don't think it's that bad. The VHDL standard specifies a default
mechanism to resolve component bindings, in case they're not 
specified in configuration specifications. This is based on the
most recently analyzed architecture. So, if your library is 
preanalyzed, an IEEE-compliant simulator should be able to resolve
the bindings automatically. Actually, this is a typical way
to incorporate standard libraries.

However, a minimal (largely empty) configuration declaration
is required to get the binding resolution process going. It can be
in a separate file and it would look like:

  configuration CONFIGURATION_NAME of YOUR_ENTITY is
    for ALTERA_ARCHITECTURE
    end for;
  end CONFIGURATION_NAME;

With this configuration, you could "simulate" your design. But is it
a meaningful one, that deserves being written out? I doubt it. This could 
hardly be a very exciting simulation, as there is no test bench to 
stimulate and observe the design.

Writing the test bench is, of course, a designer's task. As you will
instantiate your design under test in it, the test bench becomes
the real top-level of the simulation. You can only get it work
by configuring it, perhaps with a minimal configuration as above.
As soon as you have that, all lower-level bindings can be resolved
based on the most recently analyzed architecture. With what max+plus 
writes out (an entity-architecture pair) and what you have to do anyway
(writing the test bench), it should work.

Feedback is appreciated, even if this solves your problem :-)

Regards, Jan

-- 
===================================================================
Jan Decaluwe              ===              Easics               ===
Design Manager            ===  VHDL-based ASIC design services  ===
E-mail: jand@easics.be       ===================================
Tel: +32-16-270 400
Fax: +32-16-270 319         Kapeldreef 60, B-3001 Leuven, BELGIUM



Article: 1814
Subject: pci board design guide
From: maya@asp.co.il (Maya Reuveni)
Date: Wed, 6 Sep 1995 09:03:13 GMT
Links: << >>  << T >>  << A >>
I am designing a Pci bus add on card for a pc.
does anybody know about hand books for Pci design ?
thanks
maya
-- 

    Maya Reuveni                                  Tel: 972-9-986976
    Manager of Hardware Department                Fax: 972-9-986980
    HaTaasiya 9, Raanana 43100, Israel.           E-mail: maya@asp.co.il




Article: 1815
Subject: SDRAM memory control
From: oded@asp.co.il (Oded Ilan)
Date: Wed, 6 Sep 1995 10:35:09 GMT
Links: << >>  << T >>  << A >>
Hello,
has anyone used SDRAMs, controlled by FPGA's, in their system? is implementing
the control more efficient than controlling the common DRAM?

thanks,

oded






Article: 1816
Subject: Lattice ispLSI problem
From: lis@cyber.ict.pwr.wroc.pl (Jarek Lis)
Date: 6 Sep 1995 12:00:26 GMT
Links: << >>  << T >>  << A >>


Hello *,

   Is there any more detailed description of Lattice ispLSI1016 part
avalaible on the net. I grabbed few catalogue pages, but they don't cover
exact architecture of central switching matrix. My design (16 bit counter
with programmable modulo) unfortunately cannot be routed. Given advice
'try to repartitioning logic' I'd like to know where are limiting factors
so I can modify in right direction.



-- 

Jaroslaw Lis

+------------------------------------------------------------------------+
| lis@ict.pwr.wroc.pl         | Institute of Engineering Cybernetics     |
| tel  48-71-202636           | Technical University of Wroclaw, Poland  |
| fax  48-71-203408 or 517398 |                                          |
+------------------------------------------------------------------------+



Article: 1817
Subject: Xilinx FPGA(XC3000) netlister for Chipmunk/diglog
From: "Ingo Cyliax" <cyliax@cs.indiana.edu>
Date: Wed, 6 Sep 1995 08:37:44 -0500
Links: << >>  << T >>  << A >>

Has anyone a Chipmunk (diglog) netlist generator and libraries for
Xilinx parts (xnf netlists) ? I'm debating on whether to write one,
but didn't want to re-invent he wheel, if possible. 

Thanks, -ingo
-- 
/* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */


Article: 1818
Subject: Xilinx FPGA(XC3000) netlister for Chipmunk/diglog
From: "Ingo Cyliax" <cyliax@cs.indiana.edu>
Date: Wed, 6 Sep 1995 08:41:47 -0500
Links: << >>  << T >>  << A >>
Has anyone a Chipmunk (diglog) netlist (ntk) generator and libraries
for Xilinx parts (xnf netlists) ? I'm debating on whether to write one,
but didn't want to re-invent the wheel, if possible.

Thanks, -ingo
-- 
/* Ingo Cyliax, cyliax@cs.indiana.edu, +1 812 333 4854, +1 812 855 6984 (day) */


Article: 1819
Subject: Re: WWW Site about Synthesis for FPGAs
From: mjm@hpqtdzk.sqf.hp.com (Murdo McKissock)
Date: Wed, 6 Sep 1995 15:01:44 GMT
Links: << >>  << T >>  << A >>
Michael Gschwind (mike@vlsivie.tuwien.ac.at) wrote:

: A technical report with our collected experience about synthesis for
: FPGAs is now available via WWW at URL
: http://www.vlsivie.tuwien.ac.at/mike/vhdl4fpga 

I get an error message : "No route to host".  Is anyone having trouble with
this net address?

--Murdo


Article: 1820
Subject: ABEL language software
From: adam@howland (Adam Krolnik)
Date: 6 Sep 1995 16:01:42 GMT
Links: << >>  << T >>  << A >>

Is there any public domain software for ABEL? I am looking for a  
definition of the language, and any software that reads and parses the  
files.

---
   Adam Krolnik
   Design Verification Engineer
   FirePower Systems, Inc.
   Menlo Park, CA. 94025
   adam@firepower.com


Article: 1821
Subject: Looking for a Chip Supplier
From: rickey@kofax.com (Michael Rickey)
Date: Wed, 6 Sep 1995 22:37:11 GMT
Links: << >>  << T >>  << A >>
Kofax Image Products needs a vendor to supply a 70K gate CMOS ASIC
with .6 or .8 micron technology at about 15K pieces per year. The
device has been designed in VHDL using View Logic tools. Any
suggestions for a supplier of this device would be greatly
appreciated.

Please respond to dean@kofax.com or myself.  Thanks in advance for any
help you may be able to provide.

Also, if you have any recommendations on additional news groups that
would be appropriate for a posting of this type please send them my
way.


R. Michael Rickey
Manager, SQA
Kofax Image Products

Your "Component Imaging" source



Article: 1822
Subject: Re: HW VIDEO ALGORITHMS
From: "0000-Admin(0000)" <stevek>
Date: 7 Sep 1995 00:43:54 GMT
Links: << >>  << T >>  << A >>
We've developed a series of IIR and FIR filter designs using both
distributed arithmetic (DA) and a fully-parallel approach.  An application
note on the DA approach is on our Web site at:

http://www.xilinx.com

under Application Notes.  The trade-off between DA and the fully-parallel
approach is speed and area.

For example, a 16-tap, 8-bit FIR filter has the following characteristics
using the XC4000E-3 FPGA silicon:

Implementation Method        CLBs       Performance
==========================  ======      ===========
Distributed Arithmetic        432           55 MHz
Fully-Parallel                 68          5.5 MHz

If you have a specific application that you would like to implement,
please contact us at 'dsp@xilinx.com'.

-- Steve Knapp
   Corporate Applications Manager
   Xilinx, Inc.



Article: 1823
Subject: Re: How to: dual port memory
From: "0000-Admin(0000)" <stevek>
Date: 7 Sep 1995 01:08:17 GMT
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Depending on your application, the PLD + SRAM could be implemented
using a Xilinx XC4000E FPGA.  The XC4000E supports memories up to
256-words deep, but shallower memories are preferred.  Width is
not an issue.

If you'd like to review the XC4000E, it is available on the Xilinx
webLINX Web site at:

http://www.xilinx.com

or you can receive a compressed, uuencoded PostScript file by sending
an E-mail message to 'xdocs@xilinx.com' with 'send 80002' in the
Subject header.

If you have more details about your specific application, please
let us know.

-- Steve Knapp
   Corporate Applications Manager
   Xilinx, Inc.



Article: 1824
Subject: Re: Repost: VHDL Source for 5x5 Image convolver in ORCA FPGA
From: "0000-Admin(0000)" <stevek>
Date: 7 Sep 1995 01:14:29 GMT
Links: << >>  << T >>  << A >>



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