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# Messages from 1850

Article: 1850
Subject: Protel Libs,XC2000,XC3000
From: Greg Omond <gomond@werple.mira.net.au>
Date: 9 Sep 1995 06:56:49 GMT
Links: << >>  << T >>  << A >>
Has anyone got PROTEL for WINDOWS
SCHEMATIC library components for the
XC2000 and
XC3000 series chips that treat the entire
chip as a component. ie: I don't want the
library,s for creating XNF files, but
rather to display the chip as a whole on
the
schematic dwg. I also want the PCB
components for 132 pin PQFP to PTH
sockets, (AMP
brand) for PROTEL for>


Article: 1851
Subject: Looking for Scan-Path-Insertion-Too
From: Stefan Kamps <100446.3473@CompuServe.COM>
Date: 9 Sep 1995 13:58:09 GMT
Links: << >>  << T >>  << A >>
Hello

I am looking for an VHDL based tool for automatically inserting scan p
FPGAs.

Thanks, Stefan

----------------------------------------------------------------------
Stefan Kamps
MTC Micro Tech Consulting
E-Mail: 100446.3473@compuserve.com
----------------------------------------------------------------------


Article: 1852
Subject: Re: Lattice ispLSI problem
From: jothi@singnet.com.sg
Date: Sat, 09 Sep 95 09:48:21 PDT
Links: << >>  << T >>  << A >>

> Jaroslaw Lis
> | lis@ict.pwr.wroc.pl         | Institute of Engineering Cybernetics     |
>
Hi,
There are macros meant for this purpose and they are sleek. Only problem

with them is that they do not support the product term clock. You need to

copy them into your own name and use pt.clk if you need. Use them to solve your

problems than to start from basic. You can do wonders with it if you know what

is the architecture. These CPLDs are very predictable than FPGAs and we use a

lot of them. A data book from Lattice will give you a good start about the

architecture.

Thanks
jothi@singnet.com.sg


Article: 1853
Subject: Re: Can someone send me '96 FPGA call for papers?
Date: 09 Sep 1995 18:21:57 GMT
Links: << >>  << T >>  << A >>
FPGA '96: Call for Papers

1996 ACM/SIGDA Fourth International Symposium on
Field-Programmable Gate Arrays

Monterey, California
February 11-13, 1996

As Field-Programmable Gate Arrays have become essential to the design
of digital systems there is increased desire to improve their
performance, density and automated design. This symposium, sponsored
by ACM/SIGDA, seeks contributions, but is not limited to, the
following areas:

o FPGA Architecture: logic & routing, memory, I/O, new commercial
architectures.

o CAD for FPGAs: Logic optimization, technology mapping, placement,
routing.

o Interactions: between CAD, architecture, applications, and
programming technology.

o Field-Programmable Systems: emulation and computation, partitioning/routing

o Applications: novel uses of FPGAs

o Field-Programmable Interconnect

o Process Technology and FPDs

o Field-Programmable Analog Arrays

Authors should submit 20 copies of their work (maximum 10 pages,
minimum point size 10) by October 6, 1995. Notification of acceptance
will be sent by November 13, 1995. A proceedings of accepted papers
will be published (which is different from the publication policy of
the workshops in 1992 and 1994). Authors must assign copyright of
their accepted papers to ACM as a condition of publication. Final
versions of accepted papers will be limited in length to seven pages,
and will have to be submitted by December 4th, 1995. Submissions
should be sent to:

Carl Ebeling, FPGA '96 Program Chair
Department of Computer Science and Engineering
Box 352350
University of Washington
Seattle, WA 98195-2350
ebeling@cs.washington.edu, phone: (206) 543-9342, fax: (206) 543-2969

General Chair: 	Jonathan Rose, University of Toronto
Program Chair: 	Carl Ebeling, University of Washington
Publicity Chair:Jason Cong, UCLA
Finance Chair: 	Steve Trimberger, Xilinx
Local Chair:	Pak Chan, UC Santa Cruz

Program Committee

Michael Butts, Quickturn
Pak Chan, UCSC
Paul Chow, U. Toronto
Jason Cong, UCLA
Ewald Detjens, Exemplar
Carl Ebeling, U. Washington
Gareth Jones, Pilkington
Dwight Hill, Synopsys
Sinan Kaptanoglu, Actel
Jonathan Rose, U. Toronto
Richard Rudell, Synopsys
Rob Rutenbar, CMU
Takayasu Sakurai, Toshiba
Martine Schlag, UCSC
Tim Southgate, Altera
Steve Trimberger, Xilinx
Nam-Sung Woo, AT&T

--
Brad L. Hutchings - (801) 378-2667 - hutch@ee.byu.edu
Brigham Young University - Electrical Eng. Dept. - 459 CB - Provo, UT 84602
Reconfigurable Logic Laboratory


Article: 1854
Subject: Re: pci board design guide
From: Alex Koegel <alex.koegel@dspis.co.il>
Date: 10 Sep 1995 09:47:15 GMT
Links: << >>  << T >>  << A >>
Maya,

Look at Altera app. note on PCI design.

Alex Koegel
HW Director
DSPC Israel


Article: 1855
Subject: Overview of FPGAs available?
From: david@trurl.df.lth.se (David Svensson)
Date: 10 Sep 1995 19:18:44 GMT
Links: << >>  << T >>  << A >>
Is there an overview list with prices and capabilities of FPGAs made by

David Svensson


Article: 1856
Subject: Q: using FPGA for data compression\decompression
From: kendal@interlog.com (Rolande Kendal)
Date: Mon, 11 Sep 95 05:06:16 GMT
Links: << >>  << T >>  << A >>
I am working on a solid state recorder project, and I was wondering if
an FPGA interfaced to a CODEC and memory, could provide me with
sufficient data compression/decompression, that it would be a practical
solution?

If you have any suggestions then I would be pleased to hear from you.

Also, if I proceed with using an FPGA, I will be seeking someone to implement
the design work.

Rolande Kendal			<The sun shines on everyone.>

-----------------------------------------------------
Copia Technologies Incorporated
200 Alton Ave.
Toronto, ON, M4L 2M6

voice: (416) 466-8258
fax: (416) 406-0127
-----------------------------------------------------


Article: 1857
Subject: Q: FPGA used for data compression/decompression
From: kendal@interlog.com (Rolande Kendal)
Date: Mon, 11 Sep 95 05:10:27 GMT
Links: << >>  << T >>  << A >>
I am working on a solid state recorder project, and I was wondering if
an FPGA interfaced to a CODEC and memory, could provide me with
sufficient data compression/decompression, that it would be a practical
solution?

If you have any suggestions then I would be pleased to hear from you.

Also, if I proceed with using an FPGA, I will be seeking someone to implement
the design work.

Rolande Kendal			<The sun shines on everyone.>

-----------------------------------------------------
Copia Technologies Incorporated
200 Alton Ave.
Toronto, ON, M4L 2M6

voice: (416) 466-8258
fax: (416) 406-0127
-----------------------------------------------------


Article: 1858
Subject: Re: WWW Site about Synthesis for FPGAs
From: mjm@hpqtdzk.sqf.hp.com (Murdo McKissock)
Date: Mon, 11 Sep 1995 07:56:29 GMT
Links: << >>  << T >>  << A >>
: I get an error message : "No route to host".  Is anyone having trouble with

Thanks to those who replied.  The WWW server was fixed on 7 Sept.

The article contains useful data on the implementation of some common
structures.  It is specific to Synopsys and Xilinx 4000.

--Murdo


Article: 1859
Subject: Re: Re: pci board design guide
From: Michael Ruettger <100660.1705@CompuServe.COM>
Date: 11 Sep 1995 09:10:13 GMT
Links: << >>  << T >>  << A >>
hi maya
AMD has published an application note titeled "PCI Bus Interface
Using AMD PLDs". Included are PCI-Bus Overview, Specs, Schematic
and the source for a MicroSim State machine. (Publication# 19896
March 1995).

Also you can get complete PCI-Interface chips from AMCC in San
Diego (S5930-S5933 "Matchmaker").

mike


Article: 1860
Subject: ATMEL WWW site?
From: dimitris@engn.uwindsor.ca (Dimitris Phoukas)
Date: Mon, 11 Sep 1995 17:03:03 GMT
Links: << >>  << T >>  << A >>
Does anybody if ATMEL has a WWW server?

--
Dimitris Phoukas
University of Windsor
Electrical Engineering
Windsor, ON, N9B 3P4


Article: 1861
Subject: Re: Looking for Scan-Path-Insertion-Too
Date: 11 Sep 1995 17:08:40 GMT
Links: << >>  << T >>  << A >>
Stefan Kamps <100446.3473@CompuServe.COM> wrote:
>Hello
>
>I am looking for an VHDL based tool for automatically inserting scan p
>FPGAs.
>
>Thanks, Stefan
>
>----------------------------------------------------------------------
>Stefan Kamps
>MTC Micro Tech Consulting
>E-Mail: 100446.3473@compuserve.com
>----------------------------------------------------------------------

Some of the FPGAs available on the market already include a built-in
JTAG (IEEE 1149.1) scan path.  These include the Xilinx XC4000/A/D/E/H
FPGA families, the XC5200 FPGA family, and the XC8100 FPGA family.

Also, the XC4000/A/D/E/H FPGA families and the XC5200 FPGA family include
a 'Readback' facility.  This facility provides the internal values of
flip-flop and logic and is read out serially (assuming that the security
bit isn't set that dissables this facility).

Instead of inserting a scan path that consumes valuable programmable
resources, you might be able to use the built-in resources.  These do

If you would like to review the data sheets for the devices mentioned
earlier, and are on the Web, check out:

http://www.xilinx.com/products/fpgaspec.htm

or contact our Literature Support person at 'karene@xilinx.com' and ask for
information on the XC4000E, XC5200, and XC8100 families.  These data sheets
include information on the boundary-scan and readback logic.

If you would like information on how to instantiate the boundary-scan or
readback logic in VHDL or Verilog, I'd recommend a Xilinx publication called
'HDL Synthesis for FPGAs Design Guide.'

Again, this is available on the Web at

http:/www.xilinx.com/products/appsweb.htm#FPGA

You will have to look around a little in this section and the file is large.
If you'd prefer, you can also order this information on CD-ROM.  Again,
contact our Literature Support person at 'karene@xilinx.com' and ask for
the AppLINX (September 1995) CD-ROM.  By the way, this also includes the
XC4000E and XC5200 data sheets.

-- Steve Knapp
Corporate Applications Manager
Xilinx, Inc.


Article: 1862
Subject: Re: Looking for Scan-Path-Insertion-Too
Date: 11 Sep 1995 17:09:01 GMT
Links: << >>  << T >>  << A >>
Stefan Kamps <100446.3473@CompuServe.COM> wrote:
>Hello
>
>I am looking for an VHDL based tool for automatically inserting scan p
>FPGAs.
>
>Thanks, Stefan
>
>----------------------------------------------------------------------
>Stefan Kamps
>MTC Micro Tech Consulting
>E-Mail: 100446.3473@compuserve.com
>----------------------------------------------------------------------

Some of the FPGAs available on the market already include a built-in
JTAG (IEEE 1149.1) scan path.  These include the Xilinx XC4000/A/D/E/H
FPGA families, the XC5200 FPGA family, and the XC8100 FPGA family.

Also, the XC4000/A/D/E/H FPGA families and the XC5200 FPGA family include
a 'Readback' facility.  This facility provides the internal values of
flip-flop and logic and is read out serially (assuming that the security
bit isn't set that dissables this facility).

Instead of inserting a scan path that consumes valuable programmable
resources, you might be able to use the built-in resources.  These do

If you would like to review the data sheets for the devices mentioned
earlier, and are on the Web, check out:

http://www.xilinx.com/products/fpgaspec.htm

or contact our Literature Support person at 'karene@xilinx.com' and ask for
information on the XC4000E, XC5200, and XC8100 families.  These data sheets
include information on the boundary-scan and readback logic.

If you would like information on how to instantiate the boundary-scan or
readback logic in VHDL or Verilog, I'd recommend a Xilinx publication called
'HDL Synthesis for FPGAs Design Guide.'

Again, this is available on the Web at

http:/www.xilinx.com/products/appsweb.htm#FPGA

You will have to look around a little in this section and the file is large.
If you'd prefer, you can also order this information on CD-ROM.  Again,
contact our Literature Support person at 'karene@xilinx.com' and ask for
the AppLINX (September 1995) CD-ROM.  By the way, this also includes the
XC4000E and XC5200 data sheets.

-- Steve Knapp
Corporate Applications Manager
Xilinx, Inc.


Article: 1863
Subject: CORRECTED PINOUT: XC4010 and XC4013 in 225-Pin Ball Grid (BG225) Package
From: "Steven K. Knapp" <stevek>
Date: 11 Sep 1995 17:22:49 GMT
Links: << >>  << T >>  << A >>
The pinout information for the Xilinx devices:

- XC4010BG225, and
- XC4013BG225

are incorrect in the 1994 Data Book (3rd Edition).

the following locations:

World-Wide Web
--------------
http://www.xilinx.com/products/appsweb.htm#PKG
Color, bottom-side footprint in Adobe Acrobat format.
from the Web.

Compressed/Uuencoded PostScript File via E-mail
-----------------------------------------------
Send an E-mail message to 'xdocs@xilinx.com' with 'send 80012' in
the Subject header.  Requires a PostScript printer.

Xilinx Bulletin Board
---------------------

Request a FAX
-------------
If none of these methods is convenient, contact the Xilinx Customer
Response Center at 1-800-255-7778 or E-mail them at 'hotline@xilinx.com'.
Ask them to FAX you the "BG225 Corrected Pinout."

Xilinx Applications regrets this error and any inconvenience that it
may have caused.

-- Steve Knapp
Corporate Applications Manager
Xilinx, Inc.


Article: 1864
Subject: Re: Looking for Scan-Path-Insertion-Too
From: "Steven K. Knapp" <stevek>
Date: 11 Sep 1995 19:18:41 GMT
Links: << >>  << T >>  << A >>
Correction on Web location for 'HDL Synthesis for FPGAs Design Guide':

http://www.xilinx.com/products/appsweb.htm#FPGA

I keep forgetting the double forward-slash on the UURL.

-- Steve Knapp


Article: 1865
Subject: Re: ATMEL WWW site?
From: chan_isd@ix.netcom.com (Scott Evans)
Date: 12 Sep 1995 05:31:22 GMT
Links: << >>  << T >>  << A >>
In article <dimitris-1109951303030001@thor.engn.uwindsor.ca>,
dimitris@engn.uwindsor.ca (Dimitris Phoukas) wrote:
>Does anybody if ATMEL has a WWW server?
>

There is not one yet (it's in the works).

Meanwhile they can be contacted at
e-mail: fpga@atmel.com
phone: 408 436 4119

Scott Evans


Article: 1866
Subject: Archive reminder
From: jma@b117d.super.org (Jeffrey M. Arnold)
Date: Tue, 12 Sep 1995 13:22:01 GMT
Links: << >>  << T >>  << A >>
After a few months of neglect (it's amazing how fast bits decay) the
comp.arch.fpga archive web page is back up to date.  The page can be
found at:

http://www.super.org:8000/FPGA/caf.html

and contains:

1) The group charter;

2) An archive of posted messages with various retrieval mechanisms;

3) A list of upcoming events of interest to the custom computing
community;

4) Pointers to organizations engaged in FPGA based computing research;

Enjoy!

------
Jeffrey Arnold
IDA Center for Computing Sciences (formerly the Supercomputing Research Center)
17100 Science Dr.
Bowie, MD 20715
email: jma@super.org


Article: 1867
Subject: positions available-hardware design
From: eugen@research.nj.nec.com@research.nj.nec.com (Eugen Schenfeld)
Date: 12 Sep 1995 09:26:15 -0400
Links: << >>  << T >>  << A >>

\documentstyle[fullpage]{letter}

\begin{document}

\centerline{\large \bf RESEARCH POSITION AVAILABLE}

\centerline{\bf August 9, 1995}

The NEC Research Institute of Princeton, NJ is seeking candidates for
research positions in the area of Parallel Processing Architectures. Of
particular interest are candidates who have a broad architecture view, who
have a new vision for future original architectures and who are able to
purse an independent research program, including the establishing of a lab
and prototype construction to demonstrate new ideas. Original proposals for
parallel architectures, addressing some of the following issues, are
required:

\begin{itemize}

\item CPU architectures for parallel processing.
\item Parallel interconnection networks and switching elements.
\item Aspects of routing VLSI implementation for parallel processing networks,
\item Trends of future technologies (optical interconnections, VLSI, memory)
and their impact on new parallel architectures.
\item Parallel programming environments (e.g., PCN, PVM).
\item Parallel programming languages (e.g., HPF).
\item Parallel applications and their match with architectures.
\item Parallel OS (e.g., Micro-Kernels, Nano-Kernels).

\end{itemize}

The emphasis is on a broad view, not on a narrow, limited research program.
The successful candidate should have a working experience in hardware
(building prototypes, VLSI design, high speed electronics), and not only
deal with the theoretical aspects of parallel processing (e.g. simulations,
theorem proving).

The NEC Research Institute, founded in 1988, conducts long-term basic
research in the sciences underlining future technologies of computers
and communications (C\&C). The goal of the Institute is to make
fundamental contributions to the computing and physical sciences basic
to the processing and interpretation of information. The Institute's
parent company is NEC Corporation, a global leader in computers,
communications, electronics and information services. On May 2, 1990,
the NEC Research Institute dedicated its \$30 million new facilities on a twenty-one acre site in the Princeton area. This region was selected because of its tradition of basic research and invention. The Institute supports the belief that research results should be available in the open literature and therefore emulates the liberal publication policies of universities. Scientists at the NEC Research Institute seek to expand the base of scientific knowledge and enhance mutual understanding among the people of all nations. Candidates should have a {\bf recent research activity} demonstrating their role in the above topics and have a {\bf lab. working experience} with instrumentation and measurement equipment. A Ph.D. degree (or a very near completion of one) in Computer Science, Computer Engineering or Electrical Engineering is needed for this position. NEC Research Institute is an equal opportunity employer. Applicants must show documentation of eligibility for employment. Interested applicants are kindly invited to send their resumes, few recent papers and arrange for three letters of refferences to be sent {\bf directlly} to: \centerline{Dr. Eugen Schenfeld} \centerline{NEC Research Institute} \centerline{4 Independence Way} \centerline{Princeton, NJ 08540} \centerline{Phone: 609-951-2742} \centerline{fax: 609-951-2482} \centerline{email: eugen@research.nj.nec.com} \end{document}  Article: 1868 Subject: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" ) From: jcooley@world.std.com (John Cooley) Date: Tue, 12 Sep 1995 17:43:41 GMT Links: << >> << T >> << A >>  [ Citing the posted request (plus the numerous private e-mails) from the Europeans and Japanese who can't get "Integrated System Design" magazine, I'm reposting the original contest report here. - John ] !!! "It's not a BUG, jcooley@world.std.com /o o\ / it's a FEATURE!" (508) 429-4357 ( > ) \ - / The Unexpected Results From A Hardware Design Contest: _] [_ Verilog Won & VHDL Lost? -- You Be The Judge! by John Cooley, the ESNUG guy Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 I knew I hit a nerve. Usually when I publish a candid review of a particular conference or EDA product I typically see around 85 replies in my e-mail "in" box. Buried in my review of the recent Synopsys Users Group meeting, I very tersely reported that 8 out of the 9 Verilog designers managed to complete the conference's design contest yet *none* of the 5 VHDL designers could. I apologized for the terseness and promised to do a detailed report on the design contest at a later date. Since publishing this, my e-mail "in" box has become a veritable Verilog/VHDL Beirut filling up with 169 replies! Once word leaked that the detailed contest write-up was going to be published in the DAC issue of "Integrated System Design" (formerly "ASIC & EDA" magazine), I started getting phone calls from the chairman of VHDL International, Mahendra Jain, and from the president of Open Verilog International, Bill Fuchs. A small army of hired gun spin doctors (otherwise know as PR agents) followed with more phone calls. I went ballistic when VHDL columnist Larry Saunders had approached the Editor-in-Chief of ISD for an advanced copy of my design contest report. He felt I was "going to do a hatchet job on VHDL" and wanted to write a rebuttal that would follow my article... and all this was happening before I had even written *one* damned word of the article! Because I'm an independent consultant who makes his living training and working *both* HDL's, I'd rather not go through a VHDL Salem witch trial where I'm publically accused of being secretly in league with the Devil to promote Verilog, thank you. Instead I'm going present *everything* that happened at the Design Contest, warts and all, and let *you* judge! At the end of court evidence, I'll ask you, the jury, to write an e-mail reply which I can publish in my column in the follow-up "Integrated System Design". The Unexpected Results ---------------------- Contestants were given 90 minutes using either Verilog or VHDL to create a gate netlist for the fastest fully synchronous loadable 9-bit increment-by-3 decrement-by-5 up/down counter that generated even parity, carry and borrow. Of the 9 Verilog designers in the contest, only 1 didn't get to a final gate level netlist because he tried to code a look-ahead parity generator. Of the 8 remaining, 3 had netlists that missed on functional test vectors. The 5 Verilog designers who got fully functional gate-level designs were: Larry Fiedler NVidea 3.90 nsec 1147 gates Steve Golson Trilobyte Systems 4.30 nsec 1909 gates Howard Landman HaL Computer 5.49 nsec 1495 gates Mark Papamarcos EDA Associates 5.97 nsec 1180 gates Ed Paluch Paluch & Assoc. 7.85 nsec 1514 gates The surprize was that, during the same time, *none* of 5 VHDL designers in the contest managed to produce any gate level designs. Not VHDL Newbies vs. Verilog Pro's ---------------------------------- The first reaction I get from the VHDL bigots (who weren't at the competition) is: "Well, this is obviously a case where Verilog veterans whipped some VHDL newbies. Big deal." Well, they're partially right. Many of those Verilog designers are damned good at what they do -- but so are the VHDL designers! I've known Prasad Paranjpe of LSI Logic for years. He has taught and still teaches VHDL with synthesis classes at U.C. Santa Cruz University Extention in the heart of Silicon Valley. He was VP of the Silicon Valley VHDL Local Users Group. He's been a full time ASIC designer since 1987 and has designed *real* ASIC's since 1990 using VHDL & Synopsys since rev 1.3c. Prasad's home e-mail address is "vhdl@ix.netcom.com" and his home phone is (XXX) XXX-VHDL. ASIC designer Jan Decaluwe has a history of contributing insightful VHDL and synthesis posts to ESNUG while at Alcatel and later as a founder of Easics, a European ASIC design house. (Their company motto: "Easics - The VHDL Design Company".) Another LSI Logic/VHDL contestant, Vikram Shrivastava, has used the VHDL/Synopsys design approach since 1992. These guys aren't newbies! Creating The Contest -------------------- I followed a double blind approach to putting together this design contest. That is, not only did I have Larry Saunders (a well known VHDL columnist) and Yatin Trivedi (a well known Verilog columnist), both of Seva Technologies comment on the design contest -- unknown to them I had Ken Nelsen (a VHDL oriented Methodology Manager from Synopsys) and Jeff Flieder (a Verilog based designer from Ford Microelectronics) also help check the design contest for any conceptual or implementation flaws. My initial concern in creating the contest was to not have a situation where the Synopsys Design Compiler could quickly complete the design by just placing down a DesignWare part. Yet, I didn't want to have contestants trying (and failing) to design some fruity, off-the-wall thingy that no one truely understood. Hence, I was restricted to "standard" designs that all engineers knew -- but with odd parameters thrown in to keep DesignWare out of the picture. Instead of a simple up/down counter, I asked for an up-by-3 and down-by-5 counter. Instead of 8 bits, everything was 9 bits. recycled COUNT_OUT [8:0] o---------------<---------------<-------------------o | | V | ------------- -------- | DATA_IN -->-| up-by-3 |->-----carry----->-| D Q |->- CARRY_OUT | [8:0] | down-by-5 |->-----borrow---->-| D Q |->- BORROW_OUT | | | | | | UP -->-| logic | | | | DOWN -->-| |-o------->---------| D[8:0] | | ------------- | new_count [8:0] | Q[8:0] |->-o---->------o | | | | o------<-----o CLOCK ---|> | o->- COUNT_OUT | -------- [8:0] new_count [8:0] | ----------- | | even | -------- o-->-| parity |->-parity-->-| D Q |->- PARITY_OUT | generator | (1 bit) | | ----------- o--|> | | -------- CLOCK ----o Fig.1) Basic block diagram outlining design's functionality The even PARITY, CARRY and BORROW requirements were thrown in to give the contestants some space to make significant architectural trade-offs that could mean the difference between winning and losing. The counter loaded when the UP and DOWN were both "low", and held its state when UP and DOWN were "high" -- exactly opposite to what 99% of the world's loadable counters traditionally do. UP DOWN DATA_IN | COUNT_OUT ----------------------------------------- 0 0 valid | load DATA_IN 0 1 don't care | (Q - 5) 1 0 don't care | (Q + 3) 1 1 don't care | Q unchanged Fig. 2) Loading and up/down counting specifications. All I/O events happen on the rising edge of CLOCK. To spice things up a bit further, I chose to use the LSI Logic 300K ASIC library because wire loading & wire delay is a significant factor in this technology. Having the "home library" advantage, one saavy VHDL designer, Prasad Paranjpe of LSI Logic, cleverly asked if the default wire loading model was required (he wanted to use a zero wire load model to save in timing!) I replied: "Nice try. Yes, the default wire model is required." To let the focus be on design and not verification, contestants were given equivalent Verilog and VHDL testbenches provided by Yatin Trivedi & Larry Saunder's Seva Technologies. These testbenches threw the same 18 vectors at the Verilog/VHDL source code the contestants were creating and if it passed, for contest purposes, their design was judged "functionally correct." For VHDL, contestants had their choice of Synopsys VSS 3.2b and/or Cadence Leapfrog VHDL 2.1.4; for Verilog, contestants had their choice of Cadence Verilog-XL 2.1.2 or Chronologic VCS 2.3.2 plus their respective Verilog/VHDL design environments. (The CEO of Model Technology Inc., Bob Hunter, was too paranoid about the possiblity of Synopsys employees seeing his VHDL to allow it in the contest.) LCB 300K rev 3.1A.1.1.101 was the LSI Logic library. I had a concern that some designers might not know that an XOR reduction tree is how one generates parity -- but Larry, Yatin, Ken & Jeff all agreed that any engineer not knowing this shouldn't be helped to win a design contest. As a last minute hint, I put in every contestant's directory an "xor.readme" file that named the two XOR gates available in LSI 300K library (EO and EO3) plus their drive strengths and port lists. To be friendly synthesis-wise, I let the designers keep the unrealistic Synopsys default setting of all inputs having infinite input drive strength and all outputs were driving zero loads. The contest took place in three sessions over the same day. To keep things equal, my guiding philosophy throughout these sessions was to conscientiously *not* fix/improve *anything* between sessions -- no matter how frustrating! After all that was said & done, Larry & Yatin thought that the design contest would be too easy while Ken & Jeff thought it would have just about the right amount of complexity. I asked all four if they saw any Verilog or VHDL specific "gotchas" with the contest; all four categorically said "no." Murphy's Law ------------ Once the contest began, Murphy's Law -- "that which can go wrong, will go wrong" -- prevailed. Because we couldn't get the SUN and HP workstations until a terrifying 3 days before the contest, I lived through a nightmare domino effect on getting all the Verilog, VHDL, Synopsys and LSI libraries in and installed. Nobody could cut keys for the software until the machine ID's were known -- and this wasn't until 2 days before the contest! (As it was, I had to drop the HP machines because most of the EDA vendors couldn't cut software keys for HP machines as fast as they could for SUN workstations.) The LSI 300K Libraries didn't arrive until an hour before the contest began. The Seva guys found and fixed a bug in the Verilog testbench (that didn't exist in the VHDL testbench) some 15 minutes before the constest began. Some 50 minutes into the first design session, one engineer's machine crashed -- which also happened to be the licence server for all the Verilog simulation software! (Luckily, by this time all the Verilog designers were deep into the synthesis stage.) Unfortunately, the poor designer who had his machine crash couldn't be allowed to redo the contest in a following session because of his prior knowlege of the design problem. This machine was rebooted and used solely as a licence server for the rest of the contest. The logistics nightmare once again reared its ugly head when two designers innocently asked: "John, where are your Synopsys manuals?" Inside I screamed to myself: "OhMyGod! OhMyGod! OhMyGod!"; outside I calmly replied: "There are no manuals for any software here. You have to use the online docs available." More little gremlins danced in my head when I realized that six of the eight data books that the LSI lib person brought weren't for the *exact* LCB 300K library we were using -- these data books would be critical for anyone trying to hand build an XOR reduction tree -- and one Verilog contestant had just spent ten precious minutes reading a misleading data book! (There were two LCB 300K, one LCA 300K and five LEA 300K databooks.) Verilog designer Howard Landman of HaL Computer noted: "I probably wasted 15 minutes trying to work through this before giving up and just coding functional parity -- although I used parentheses in hopes of Synopsys using 3-input XOR gates." Then, just as things couldn't get worst, everyone got to discover that when Synopsys's Design Compiler runs for the first time in a new account -- it takes a good 10 to 15 minutes to build your very own personal DesignWare cache. Verilog contestant Ed Paluch, a consultant, noted: "I thought that first synthesis run building [expletive deleted] DesignWare caches would *never* end! It felt like days!" Although, in my opinion, none of these headaches compromised the integrity of the contest, at the time I had to continually remind myself: "To keep things equal, I can *not* fix nor improve *anything* no matter how frustrating." Judging The Results ------------------- Because I didn't want to be in the business of judging source code *intent*, all judging was based solely on whether the gate level passed the previously described 18 test vectors. Once done, the design was read into the Synopsys Design Compiler and all constraints were removed. Then I applied the command "clocks_at 0, 6, 12 clock" and then took the longest path as determined by "report_timing -path full -delay max -max_paths 12" as the final basis for comparing designs -- determining that Verilog designer Larry Fiedler of NVidia won with a 1147 gate design timed at 3.90 nsec. reg [9:0] cnt_up, cnt_dn; reg [8:0] count_nxt; always @(posedge clock) begin cnt_dn = count_out - 3'b 101; // synopsys label add_dn cnt_up = count_out + 2'b 11; // synopsys label add_up case ({up,down}) 2'b 00 : count_nxt = data_in; 2'b 01 : count_nxt = cnt_dn; 2'b 10 : count_nxt = cnt_up; 2'b 11 : count_nxt = 9'bX; // SPEC NOT MET HERE!!! default : count_nxt = 9'bX; // avoiding ambiguity traps endcase parity_out <= ^count_nxt; carry_out <= up & cnt_up[9]; borrow_out <= down & cnt_dn[9]; count_out <= count_nxt; end Fig. 3) The winning Verilog source code. (Note that it failed to meet the spec of holding its state when UP and DOWN were both high.) Since judging was open to any and all who wanted to be there, Kurt Baty, a Verilog contestant and well respected design consultant, registered a vocal double surprize because he knew his design was of comparable speed but had failed to pass the 18 test vectors. (Kurt's a good friend -- I really enjoyed harassing him over this discovery -- especially since he had bragged to so many people on how he was going to win this contest!) An on the spot investigation yielded that Kurt had accidently saved the wrong design in the final minute of the contest. Even further investigation then also yielded that the 18 test vectors didn't cover exactly all the counter's specified conditions. Larry's "winning" gate level Verilog based design had failed to meet the spec of holding its state when UP and DOWN were high -- even though his design had successfully passed the 18 test vectors! If human visual inspection of the Verilog/VHDL source code to subjectively check for places where the test vectors might have missed was part of the judging criteria, Verilog designer Steve Golson would have won. Once again, I had to reiterate that all designs which passed the testbench vectors were considered "functionally correct" by definition. What The Contestants Thought ---------------------------- Despite NASA VHDL designer Jeff Solomon's "I didn't like the idea of taking the traditional concept of counters and warping it to make a contest design problem", the remaining twelve contestants really liked the architectural flexiblity of the up-by-3/down-by-5, 9 bit, loadable, synchronous counter with even party, carry and borrow. Verilog designer Mark Papamarcos summed up the majority opinion with: "I think that the problem was pretty well devised. There was a potential resource sharing problem, some opportunities to schedule some logic to evaluate concurrently with other logic, etc. When I first saw it, I thought it would be very easy to implement and I would have lots of time to tune. I also noticed the 2 and 3-input XOR's in the top-level directory, figured that it might be somehow relevant, but quickly dismissed any clever ideas when I ran into problems getting the vectors to match." Eleven of contestants were tempted by the apparent correlation between known parity and the adding/subtracting of odd numbers. Only one Verilog designer, Oren Rubinstein of Hewlett-Packard Canada, committed to this strategy but ran way out of time. Once home, Kurt Baty helped Oren conceptually finish his design while Prasad Paranjpe helped with the final synthesis. It took about 7 hours brain time and 8 hours coding/sim/synth time (15 hours total) to get a final design of 3.05 nsec & 1988 gates. Observing it took 10x the original estimated 1.5 hours to get a 22% improvement in speed, Oren commented: "Like real life, it's impossible to create accurate engineering design schedules." Two of the VHDL designers, Prasad Paranjpe of LSI Logic and Jan Decaluwe of Easics, both complained of having to deal with type conversions in VHDL. Prasad confessed: "I can't believe I got caught on a simple typing error. I used IEEE std_logic_arith, which requires use of unsigned & signed subtypes, instead of std_logic_unsigned." Jan agreed and added: "I ran into a problem with VHDL or VSS (I'm still not sure.) This case statement doesn't analyze: "subtype two_bits is unsigned(1 downto 0); case two_bits'(up & down)..." But what worked was: "case two_bits'(up, down)..." Finally I solved this problem by assigning the concatenation first to a auxiliary variable." Verilog competitor Steve Golson outlined the first-get-a-working-design-and- then-tweak-it-in-synthesis strategy that most of the Verilog contestants pursued with: "As I recall I had some stupid typos which held me up; also I had difficulty with parity and carry/borrow. Once I had a correctly functioning baseline design, I began modifying it for optimal synthesis. My basic idea was to split the design into four separate modules: the adder, the 4:1 MUXes, the XOR logic (parity and carry/borrow), and the top counter module which contains only the flops and instances of the other three modules. My strategy was to first compile the three (purely combinational) submodules individually. I used a simple "max_delay 0 all_outputs()" constraint on each of them. The top-level module got the proper clock constraint. Then "dont_touch" these designs, and compile the top counter module (this just builds the flops). Then to clean up I did an "ungroup -all" followed by a "compile -incremental" (which shaved almost 1 nsec off my critical path.)" Typos and panic hurt the performance of a lot of contestants. Verilog designer Daryoosh Khalilollahi of National Semiconductor said: "I thought I would not be able to finish it on time, but I just made it. I lost some time because I would get a Verilog syntax error that turned up because I had one extra file in my Verilog "include" file (verilog -f include) which was not needed." Also, Verilog designer Howard Landman of Hal Computers never realized he had put both a complete behavioral *and* a complete hand instanced parity tree in his source Verilog. (Synopsys Design Compiler just optimized one of Howard's dual parity trees away!) On average, each Verilog designer managed to get two to five synthesis runs completed before running out of time. Only two VHDL designers, Jeff Solomon and Jan Decaluwe, managed to start (but not complete) one synthesis run. In both cases I disqualified them from the contest for not making the deadline but let their synthesis runs attempt to finish. Jan arrived a little late so we gave Jan's run some added time before disqualifying him. His unfinished run had to be killed after 21 minutes because another group of contestants were arriving. (Incidently, I had accidently given the third session an extra 6 design minutes because of a goof on my part. No Verilog designers were in this session but VHDL designers Jeff Solomon, Prasad Paranjpe, Vikram Shrivastava plus Ravi Srinivasan of Texus Instruments all benefited from this mistake.) Since Jeff was in the last session, I gave him all the time needed for his run to complete. After an additional 17 minutes (total) he produced a gate level design that timed out to 15.52 nsec. After a total of 28 more minutes he got the timing down to 4.46 nsec but his design didn't pass functional vectors. He had an error somewhere in his VHDL source code. Failed Verilog designer Kurt Baty closed with: "John, I look forward to next year's design contest in whatever form or flavor it takes, and a chance to redeem my honor." Closing Arguments To The Jury ----------------------------- Closing aurguments the VHDL bigots may make in this trial might be: "What 14 engineers do isn't statistically significant. Even the guy who ran this design contest admitted all sorts of last minute goofs with it. You had a workstation crash, no manuals & misleading LSI databooks. The test vectors were incomplete. One key VHDL designer ran into a Synopsys VHDL simulator bug after arriving late to his session. The Verilog design which won this contest didn't even meet the spec completely! In addition, this contest wasn't put together to be a referendum on whether Verilog or VHDL is the better language to design in -- hence it may miss some major issues." The Verilog bigots might close with: "No engineers work under the contrived conditions one may want for an ideal comparision of Verilog & VHDL. Fourteen engineers may or may not be statistally significant, but where there's smoke, there's fire. I saw all the classical problems engineers encounter in day to day designing here. We've all dealt with workstation crashes, bad revision control, bugs in tools, poor planning and incomplete testing. It's because of these realities I think this design contest was *perfect* to determine how each HDL measures up in real life. And Verilog won hands down!" The jury's veridict will be seen in the next "Integrated System Design". You The Jury... --------------- You the jury are now asked to please take ten minutes to think about what you have just read and, in 150 words or less, send your thoughts to me at "jcooley@world.std.com". Please don't send me "VHDL sucks." or "Verilog must die!!!" -- but personal experiences and/or observations that add to the discussion. It's OK to have strong/violent opinions, just back them with something more than hot air. (Since I don't want to be in the business of chasing down permissions, my default setting is *whatever* you send me is completely publishable. If you wish to send me letters with a mix of publishable and non-publishable material CLEARLY indicate which is which.) I will not only be reprinting replied letters, I'll also be publishing stats on how many people had reported each type of specific opinion/experience. - John Cooley Part Time EDA Consumer Advocate Full Time ASIC, FPGA & EDA Design Consultant P.S. In replying, please indicate your job, your company, whether you use Verilog or VHDL, why, and for how long. Also, please DO NOT copy this article back to me -- I know why you're replying! :^) =========================================================================== Trapped trying to figure out a Synopsys bug? Want to hear how 3349 other users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)! !!! "It's not a BUG, jcooley@world.std.com /o o\ / it's a FEATURE!" (508) 429-4357 ( > ) \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, _] [_ Verilog, VHDL and numerous Design Methodologies. Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 Legal Disclaimer: "As always, anything said here is only opinion."  Article: 1869 Subject: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter From: suzanne@world.std.com (suzanne M southworth) Date: Tue, 12 Sep 1995 21:25:52 GMT Links: << >> << T >> << A >> Eddie---Eddie--Eddie.....relax! I think you wish you could make the money John Cooley makes! The consulting/training business is very lucrative if you're good at it. John, thanks for letting us all know that it's AT&T. eddie amara (amaraju@onramp.net) wrote: : Mind your own business pal, I have a job to do and yours is not to get : into my business. Yes, we do look for somebody for a position and that : position is usually better than what they have now, have a problem with : that? You wish you can make the money us headhunters make. : In article <DE8nrM.py@world.std.com>, jcooley@world.std.com (John Cooley) wrote: : :If you want to blow off this headhunter and deal with the company directly, : :it's AT&T in their Microelectronics Division. I even have the e-mail address : :somewhere for these people. Remember: Headhunters are only interested in : :getting *somebody* in this job so they can collect a fee -- they don't give : :a damn if it's you or anyone else. As long as they collect their fee, : :they're happy. : : - John Cooley : : Part Time EDA Consumer Advocate : : Full Time ASIC, FPGA & EDA Design Consultant : : : :=========================================================================== : : Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other : : users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)! : : : : !!! "It's not a BUG, jcooley@world.std.com : : /o o\ / it's a FEATURE!" (508) 429-4357 : : ( > ) : : \ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys, : : _] [_ Verilog, VHDL and numerous Design Methodologies. : : : : Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222 : : Legal Disclaimer: "As always, anything said here is only opinion." : : : :eddie amara <amaraju@onramp.net> wrote: : :> Prestigious Research Labs!!!! : :> : :>Join one of the fastest growing divisions of this Fortune 50 Corp. FPGA !!!!! : :> : :>FPGA Applications Engineer-Owns the complete implementation of the : :>design.Supports the FAE and ultimately responsible for having the design : :>work in the customers system. : :> : :>Other resposibilities-Customer design win support. : :> Support customers and FAE with problem designs : :> Contribute to regional tag teams : :> Periodically visit customer base : :> Act as a Hardware or CAD platform champion : :> Customer and FAE training : :> Apps notes : :> Documentation : :> : :>Skills/Exp-System logic design : :> Programmable logic : :> FPGAs : :> Schematic capture tools : :> FPGA place and route tools : :> Good communication and writing skills : :> : :>Education-BS or MS in EE or CS and 5 years of system and or logic design : :>will be considered. : :> : :>Salary-$50 to $70 +12% bonus : :> : :>Location--Allentown,Pa. : :> : :> : :>no new grads or those withonly university work,thanks. : :> : :>-- : :>Eddie Amara : :>SpencerSearch,Inc. : :>Voice 214-931-3060 : :>Fax 214-931-8471 : :>amaraju@onramp.net : -- : Eddie Amara : SpencerSearch,Inc. : Voice 214-931-3060 : Fax 214-931-8471 : amaraju@onramp.net  Article: 1870 Subject: XC3030 XC1736 "Done still low" From: pac1@waikato.ac.nz Date: 13 Sep 95 15:10:45 +1200 Links: << >> << T >> << A >>  I'm trying to download a makebit from xact5 to a XC3030 PGA via LPT1 cable to a XC1736 socket. After I reset the PGA, XACT5 says "programming ....." and then "done still low" or something like this as if the PGA is not programmed correctly so it isn't putting Done pin high. Anyone had this problem - - can you give any suggestions on my problem? Regards, PC (Peter Cossey)  Article: 1871 Subject: Newbie question about PLDshell From: jgodden@csulb.edu (John Godden) Date: 13 Sep 1995 05:10:05 GMT Links: << >> << T >> << A >>  I'm using intels PLDshell Plus version 3.1 and would like to know if this is the most current version and if not.... then where/how can I get an upgrade. Please email me direct. Thanks in advance John  Article: 1872 Subject: Fast FPGA's? From: otoe@si.sintef.no (Ola Torudbakken) Date: 13 Sep 1995 09:08:39 +0200 Links: << >> << T >> << A >>  I need some recommendation of FPGA's which may achieve a system speed of 40MHz. I'm not interested in hearing about FPGA products which can be used to implement really fast counter designs. What I'm looking at, is an FPGA which can operate at a system speed of 40MHz. The design implements a big state machine and a quite complex data-path. Ola  Article: 1873 Subject: UART for Actel FPGA needed From: Todd Date: 13 Sep 1995 14:15:02 GMT Links: << >> << T >> << A >> does anyone have a macro or VHDL code to implement a UART? I'm using an Actel 10 or 12 series fpga. I'm really more interested in receiving serial code than transmitting. please email me instead of posting here. thanks! Todd a0460010@shsun3.dseg.ti.com  Article: 1874 Subject: Re: Newbie question about PLDshell From: leow@uclink.berkeley.edu (Ka-Chung Wong) Date: 13 Sep 1995 17:21:45 GMT Links: << >> << T >> << A >> In article <435p3d$ark@garuda.csulb.edu>,
John Godden <jgodden@csulb.edu> wrote:
>  I'm using intels PLDshell Plus version 3.1 and would like to know
>if this is the most current version and if not.... then where/how

PLDshell, along with Intel's programmable logic business, is now Altera's
product.
The latest version is v.5.0.  You can obtain the SW on Altera's BBS:
408-954-0104.

Hope this help.

Leo