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Messages from 1975

Article: 1975
Subject: Protel Xilinx Libraries
From: swam@adc.com (Steve Swam)
Date: 27 Sep 1995 15:16:54 GMT
Links: << >>  << T >>  << A >>
Does anyone know if there are Xilinx libraries available for Protel Schematic
capture?

Thanks in advance!

sms

+----------+ 
| / / /    |   Steve Swam                    voice:  (612)946-3146
|/ / /     |   ADC Telecommunications        fax:    (612)946-3499
|     A D C    4900 W. 78th Street, MS-256   email:  swam@adc.com
|          |   Minneapolis, MN  55435-5410   
|          |
+----------+   URL -> http://www.adc.com/~sms/index.html

"Meetings are indispensable when you don't want to do anything"
			    -- John Kenneth Galbraith (1908-  )


Article: 1976
Subject: Re: NEW person
From: wirthlim@fpga.ee.byu.edu (Michael J. Wirthlin)
Date: 27 Sep 1995 09:48:57 -0600
Links: << >>  << T >>  << A >>

In article <448827$oub@sparky.midwest.net>, Terry Bailey <INTERNET@SIU.EDU> writes:
|> I just got through with a design that has entirely toooooo many chips on 
|> it and want to investigate FPGA's and PLD's.  Can someone tell me what 
|> the difference is and why I would use one over the other to put a lot of 
|> my and, or, flipflops, counters into??  Thanks  

Although the distinction between PLDs and FPGAs is becoming more unclear,
there are a number of general differences between the two:

PLD's:
   - have high fan-in capability
   - more predictable routing

FPGA's:
   - usually register rich
   - lower fan-in than PLD's
   - provide rich, yet complex routing

The general rule-of-thumb I have heard is that PLDs are better suited for complex
control and FGPAs are better suited for datapath applications. 
-- 
Michael J. Wirthlin
Brigham Young University - Electrical Engineering Department
Reconfigurable Logic Laboratory (801) 378-7206


Article: 1977
Subject: Re: FPGA for a 20k gates micro-controller.
From: granville@decus.org.nz
Date: 28 Sep 95 07:23:52 +1200
Links: << >>  << T >>  << A >>
In article <43s65h$5do@athena.ulaval.ca>, gel101@gel.ulaval.ca (Vincent Rowley) writes:
> Hi,
> 
> I want to use FPGAs to build a 20k gates micro-controller who can
> run at 40 MHz.
> 
> I search informations, like data sheets and data books, from FPGAs
> manufacturers. All web sites, email and postal addresses are
> welcomes.
> 
> I also search informations about software tools required to
> implement these manufacturers FPGAs.
> 
> If you reply to the group, please reply also to me.
> 
> Thanks,
> 
> Vincent Rowley
> 
> -----------------------------------------------------------------
> --  Vincent Rowley               --  Laboratoire de Vision et  --
> --                               --  Systemes Numeriques       --
> --                               --  Universite Laval          --
> --                               --  Cite Universitaire        --
> --                               --  Quebec, Canada            --
> --  Email: gel101@gel.ulaval.ca  --  G1K 7P4                   --
> -----------------------------------------------------------------
 A couple of months ago, I did a similar search - only I was looking for
80x51 cores.
 There is a XILINX example , using the 6502, and some VHDL bureau's had
80x51's in the works.
 The conclusion was , however
-i) given a std process ( eg 0.8u), the std silicon 80x51's will ALWAYS
be significantly faster and cheaper than FPGA's.
ii) a CPU core alone is easier to do than a MicroCOntroller, with
RAM/SFR/TIMERS etc

 From memory, busspeeds of 2MHz were quoted, for FPGA uC's

As 51's now routinely hit 300nS cycles times, with some heading to 100nS,
there is little point in doing a STD core.

 For very specialised apps, a custom uC, with a core that matched the system
could have merit, but I doubt the $$ would stack up.

 Much better is to look at coupling a FPGA/EPLD tightly to a uC, and we have
done a number of projects with 80x51+EPLD, and have seen some 80x51+FPGA's.

 The industry does need better 'bus-able' EPLD/FPGA designs, and I think some
suppliers are addressing this problem, but only from the top end (as always :-(
===== Mandeno Granville FAX +64 9 6301 720, 128 Grange Rd Auckland 3 NZ ======
* Developers and suppliers of serious MicroController Embedded Control Tools *
* 89c2051, 89c1051 Emulator / ChipreProgrammers 			     *
* x51 C, Pascal & Modula-2 Compilers, Simulators, Emulators & FLASH Pgmrs    *
* Contact : Jim Granville . Email above.                                     *

> 
> 


Article: 1978
Subject: XACT <-> Orcad Interface
From: David Mauro <08962500524-0001@t-online.de>
Date: 27 Sep 1995 19:58:00 GMT
Links: << >>  << T >>  << A >>
Hi!
I'm trying to find out a good solution for the problem how to make XACT 
and Orcad STD/VST work together.

Does anybody know anything about this topic?
Please answer By email!

Thanks and CU
DAVID




Article: 1979
Subject: Re: FPGA for a 20k gates micro-controller.
From: Ray Andraka <randraka@ids.net>
Date: 27 Sep 1995 21:16:47 GMT
Links: << >>  << T >>  << A >>
granville@decus.org.nz wrote:
>  Much better is to look at coupling a FPGA/EPLD tightly to a uC, and we have
> done a number of projects with 80x51+EPLD, and have seen some 80x51+FPGA's.
> 
>  The industry does need better 'bus-able' EPLD/FPGA designs, and I think some
> suppliers are addressing this problem, but only from the top end (as always :-(
> ===== Mandeno Granville FAX +64 9 6301 720, 128 Grange Rd Auckland 3 NZ ======

Xilinx 6200 parts which are being introduced this fall/winter are supposed
to address exactly that situation!  i don't know the prices yet.

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930     FAX 401/884-7950
email randraka@ids.net

The Andraka Consulting Group is a digital hardware design firm specializing
in high performance FPGA designs.  Services include complete design,
development, simulation and integration of these devices and the
surrounding circuits.  We also evaluate, troubleshoot and improve
existing designs.  Please call or write for a free brochure.



Article: 1980
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: Jan Decaluwe <jand>
Date: 27 Sep 1995 22:48:09 GMT
Links: << >>  << T >>  << A >>
jcooley@world.std.com (John Cooley) wrote:

>I fully understand the philosphy of moving to higher levels of abstraction
>and think its a beautiful concept on paper.  But, then again, Communism
>is quite beautiful in theory, too.  Both make for great coffee shop
>discussions but it's the actual attempt at implementing either idea that
>seems to be fairly impractical (and painful) in most cases these days.
>

The big advantage of "proof by deceptive analogy" is that it lets you
prove anything you want, for example:

Moving to higher levels of abstraction is a beautiful concept, just
like Economic Liberalism (*). Whenever they are applied, these concepts
result in large productivity gains. But the reasons for this success
seem to be far from obvious, and as they challenge conventional wisdom,
these concepts are continuously criticized.

(*) original meaning, not contemporary US meaning

Regards, Jan
-- 
===================================================================
Jan Decaluwe              ===              Easics               ===
Design Manager            ===  VHDL-based Internet Coffee Shop  ===
E-mail: jand@easics.be       ===================================
Tel: +32-16-270 400
Fax: +32-16-270 319         Kapeldreef 60, B-3001 Leuven, BELGIUM



Article: 1981
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: Jan Decaluwe <jand>
Date: 28 Sep 1995 00:04:42 GMT
Links: << >>  << T >>  << A >>
ekatjr@eua.ericsson.se (Robert Tjarnstrom) wrote:
>In article <43fgn7$45f@news.Belgium.EU.net>, Jan Decaluwe <jand> writes:
>>jcooley@world.std.com (John Cooley) wrote:
>>
>>
>>>I personally tend to see hardware when I design hardware, 
>>
>>This argument is widely used against design methodologies that rely
>>on higher levels of abstration. I believe it is misleading. 

>Am I correct if I understand that you indicate that the designer should not tend
>to see HW while designing, but rather focus on modeling the functionality at as
>high abstraction level as possible? If so, I could not disagree more.
>

No, I don't say that the designer should not "see HW", but yes, I suggest 
that he should raise the abstraction level as high as possible. There is
no inconsistency here: we define "as high as possible" as the level at which 
you can trust the synthesis tool to take care of the lower level details in 
terms of area, performance, power, and other cost factors.

Again, I believe that the "need to see HW" argument is misleading, as there
are many levels at which HW can be "seen". Rather, the point I have is that 
design is currently often done at an abstraction level below the one that 
synthesis technology permits.

Let's be specific (as this is hopefully not just a coffee shop discussion). 
The original topic of this thread was "abstract" typing, i.e. using integers, 
booleans and enum types instead of std_logic types. This is one of the methods 
to raise the abstraction level, with *tremendous* advantages in terms of code 
clarity, maintainability and reusability. On the other hand, using these types 
has no disadvantage in terms of RTL synthesis results (Synopsys DC). 
If something has only advantages and no disadvantages, one should obviously do it.

Regards, Jan

-- 
===================================================================
Jan Decaluwe              ===              Easics               ===
Design Manager            ===  VHDL-based ASIC design services  ===
E-mail: jand@easics.be       ===================================
Tel: +32-16-270 400
Fax: +32-16-270 319         Kapeldreef 60, B-3001 Leuven, BELGIUM



Article: 1982
Subject: Re: Protel Xilinx Libraries
From: "Steven K. Knapp, Xilinx, Inc." <stevek>
Date: 28 Sep 1995 00:47:14 GMT
Links: << >>  << T >>  << A >>
swam@adc.com (Steve Swam) wrote:
>Does anyone know if there are Xilinx libraries available for Protel Schematic
>capture?
>
Yes there are!  The Protel Advanced Schematic 2.2 supports
the Xilinx XC2000, XC3000/A, XC3100A, and XC4000/A/D/H
FPGA families and the XC7200A and XC7300 EPLD families.

The Xilinx libraries are available directly from Protel
Technology at TEL:  1-408-243-8143.  The contact there is
Matthew Schwaiger

-- Steve Knapp
   Corporate Applications Manager
   Xilinx, Inc.



Article: 1983
Subject: Re: FPGA for a 20k gates micro-controller.
From: "Steven K. Knapp, Xilinx, Inc." <stevek>
Date: 28 Sep 1995 00:54:24 GMT
Links: << >>  << T >>  << A >>
Ray Andraka <randraka@ids.net> wrote:
>granville@decus.org.nz wrote:
>>  Much better is to look at coupling a FPGA/EPLD tightly to a uC, and we have
>> done a number of projects with 80x51+EPLD, and have seen some 80x51+FPGA's.
>> 
>>  The industry does need better 'bus-able' EPLD/FPGA designs, and I think some
>> suppliers are addressing this problem, but only from the top end (as always :-(
>> ===== Mandeno Granville FAX +64 9 6301 720, 128 Grange Rd Auckland 3 NZ ======
>
>Xilinx 6200 parts which are being introduced this fall/winter are supposed
>to address exactly that situation!  i don't know the prices yet.
>
The Xxilinx XC6200 is the first FPGA family optimized for co-processing in
embedded system applications.

You can find out more information about the Xilinx XC6200 FPGA on the Web at

http://www.xilinx.com/products/fpgaspec.htm#XC6200

-- Steve Knapp
   Corporate Applications Manager
   Xilinx, Inc.



Article: 1984
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: Jonathan AH Hogg <jonathan@dcs.gla.ac.uk>
Date: Thu, 28 Sep 1995 09:25:19 GMT
Links: << >>  << T >>  << A >>
On 27 Sep 1995, Robert Tjarnstrom wrote:

> If low number of code lines is essential then everybody should be using functional 
> languages. There you have a significant reduction of code lines. However, we do not 
> see many applications coded in functional languages. There must be a reason for that. 
> Anyone has an idea why?? Poor performance ??

indeed we are in the process of producing an HDL toolset written entirely
in the lazy functional language Haskell. poor performance is a label that
is acquired early and is very difficult to shake off.

> Tools are clearly better on logic minimization and should of course be used for that.
> However, I have not seen any tool good at making architectural trade-offs and solutions.

it's still early days yet for hardware synthesis. no-one really
understands what an HDL should look like. an HDL that's based on a
software language is not a good starting point in my opinion. designing
software and designing hardware are two different paradigms. since when 
did gate arrays have `for' loops? software is based on control flow, 
hardware is based on data flow.

we need to develop new tools and ways of working, not rubbish the whole 
concept and go back to rubbing stick diagrams together...

:-jonathan

-- 
Jonathan AH Hogg, Computing Science, The University, Glasgow G12 8QQ, Scotland.
jonathan@dcs.gla.ac.uk http://www.dcs.gla.ac.uk/~jonathan (+44)141 3398855x2069



Article: 1985
Subject: Xilinx Flash FPGA ??
From: NICOLAS TRIBIE <tribien@esiee.fr>
Date: 28 Sep 1995 12:23:28 GMT
Links: << >>  << T >>  << A >>
Can I find a Xilinx 4XXX FPGA with a Flash EPROM ( or an EEPROM ) instead 
of a SRAM ? 

 I need to have all the I/O ports free for my application.




-- 
_______________________________________________________________________________
Nicolas Tribie			  |  Member of ESIEESPACE, Aerospatial club:
ESIEE, Comp. Arch. Departement	  |     - Experimental rockets,
2 Bd Blaise Pascal BP99           | 	- Remote Sensing Experiments,
93162 Noisy-le-Grand Cedex        | 	- Micro Satellites (not me..)
email : tribien@esiee.fr	  | 
http://www.esiee.fr/~tribien	  |  http://www.esiee.fr/~space
_______________________________________________________________________________



Article: 1986
Subject: Re: Functional Languages for Hardware Description was REPOST: Design Contest Write-up
From: mel@rocky.cs.cornell.edu (Miriam Leeser)
Date: 28 Sep 1995 16:10:30 GMT
Links: << >>  << T >>  << A >>

We are working on a functional hardware description language called
HML, that is based on the computer language SML.  

It has several advantages over existing hardware description
languages, especially VHDL and Verilog.  The descriptions are MUCH
briefer than  VHDL descriptions, and we do automatic type inference
as well as interface inference so that users do not have to specify
these.  

HML supports behavioral and structutral description as well as a
mixture of the two.  We have a set of tools that automatically
generate VHDL from HML descriptions, including generating the types.

There was a paper on HML a few weeks ago at CHDL:

"HML: An Innovative Hardware Description Language and its Translation
to VHDL" Yanbing Li and Miriam Leeser in Proceedings of CHDL'95.

HML related papers are available by ftp from:

ftp://orac.ee.cornell.edu/pub/hw-verify

the relevant reports are:

hml2vhdl-techrep.ps.gz  An introduction to HML and its translation to
VHDL

hml-techrep.ps.gz  An older report discussing language features.
(Note: not all these features have been implemented.)

Miriam Leeser
Assoc Prof
Cornell University
School of Electrical Engineering

Miriam.Leeser@cornell.edu


Article: 1987
Subject: Re: FPGA for a 20k gates micro-controller.
From: Vincent Rowley <gel101@gel.ulaval.ca>
Date: Thu, 28 Sep 1995 12:28:52 -0400
Links: << >>  << T >>  << A >>
>> gel101@gel.ulaval.ca (Vincent Rowley) writes:
>>
>> Hi,
>> 
>> I want to use FPGAs to build a 20k gates micro-controller who can
>> run at 40 MHz.
>> 
>> I search informations, like data sheets and data books, from FPGAs
>> manufacturers. All web sites, email and postal addresses are
>> welcomes.
>> 
>> I also search informations about software tools required to
>> implement these manufacturers FPGAs.
>>
>> Vincent Rowley
>> 

> granville@decus.org.nz wrote:
>
> For very specialised apps, a custom uC, with a core that matched the system
>could have merit, but I doubt the $$ would stack up.
>
> Much better is to look at coupling a FPGA/EPLD tightly to a uC, and we have
>done a number of projects with 80x51+EPLD, and have seen some 80x51+FPGA's.
>
> The industry does need better 'bus-able' EPLD/FPGA designs, and I think 
some
>suppliers are addressing this problem, but only from the top end (as 
always :-(

I think that my question is not very clear and I want to precise what
I want to do.

I want to use FPGA's for the implementation of a digital controller
with an open architecture designed to manage data flow between the
processing modules of an embedded computer vision system. This
controller should be capable of tracking edge segments and building
automatically a database which contains a linked list of edge features.

I want to develop my custom micro-controller whit VHDL because I
project to re-target my design to normalized CMOS library to make
an ASIC IC.

Vincent Rowley

------------------------------------------------------------------
--  Vincent Rowley               --  Laboratoire de Vision et   --
--                               --  Systemes Numeriques,       --
--                               --  Dept. de genie electrique  --
--                               --  et de genie informatique,  --
--                               --  Pavillon Pouliot,          --
--                               --  Universite Laval,          --
--                               --  Quebec, Canada             --
--  Email: gel101@gel.ulaval.ca  --  G1K 7P4                    --
------------------------------------------------------------------



Article: 1988
Subject: Re: FPGA for a 20k gates micro-controller.
From: ree@ix.netcom.com (Brad Ree )
Date: 28 Sep 1995 16:35:04 GMT
Links: << >>  << T >>  << A >>
In <43s65h$5do@athena.ulaval.ca> gel101@gel.ulaval.ca (Vincent Rowley)
writes: 
>
>Hi,
>
>I want to use FPGAs to build a 20k gates micro-controller who can
>run at 40 MHz.
>
>I search informations, like data sheets and data books, from FPGAs
>manufacturers. All web sites, email and postal addresses are
>welcomes.
>
>I also search informations about software tools required to
>implement these manufacturers FPGAs.
>
>If you reply to the group, please reply also to me.
>
>Thanks,
>
>Vincent Rowley
>
>-----------------------------------------------------------------
>--  Vincent Rowley               --  Laboratoire de Vision et  --
>--                               --  Systemes Numeriques       --
>--                               --  Universite Laval          --
>--                               --  Cite Universitaire        --
>--                               --  Quebec, Canada            --
>--  Email: gel101@gel.ulaval.ca  --  G1K 7P4                   --
>-----------------------------------------------------------------
>
>

>From my understanding, you are not looking to implement an exsisting
micro into a FPGA.  Instead, you want to try to implement a micro of
your own design into a 20K gate FPGA.  Also, you are tring to clock
this at 40MHz.

If the above asumptions are true, then the answer is that you can
easily accomplish you goal.  I just got done with a design in which I
implemented a simple 8 bit pipelined processor in under 16K gates.  For
this design, I used Xilinx's slowest 3000 FPGAs, and was able to easily
clock the processor at 16MHz.  Unlike some of the other messages, this
design is a complete processor, not just the execution segment. 
Granted this design could only be clocked at 16MHz, there are several
reasons that I claim that you can run your design at 40MHz.  First, I
implemented my design in multiple XC3042.  This will cause extra delay
between signals, since it has to go through out one IOB, and then into
another IOB.  Second, I did not attempt to speed up the design.  Third,
I did not give the router any extra information which could increase
performance.  Fourth, I used their slowest 3000 family parts.  Fifth, I
did not use their fastest family, the 3100 family.  Thus, I am very
confident that you could clock a processor implemented in FPGAs at
40MHz.
    As noted in another posting, FPGA will always be slower than
dedicated gates.  However, if you are not trying to acheive more than
60MHz, you could easily implement your design in a FPGA.  Also, you
will not have to pay the $10,000 in setup cost of an ASIC.

        Brad



Article: 1989
Subject: Re: FPGA for a 20k gates micro-controller.
From: DGVR59A@prodigy.com (Cahill schmitz Cahill)
Date: 29 Sep 1995 00:16:48 GMT
Links: << >>  << T >>  << A >>
I heard that Altera's new Flex 10k family will be well suited to 
implementing a core micro controller.  They supposedly implemented one 
which was then used to control a very old Apple computer running at 8 MHz.
  The EAB (embedded array block) is a complex function generator useful 
to genereate complex functions very effectively (ie. 4x4 multiplier).  
The total implementation was about 10K gates.  They used a HDL to 
describe the functions of the machine instructions which were then 
synthsized and compiled into the device.

Best of Luck in your search.



Article: 1990
Subject: *** NEED HELP ON 'Cadence: The Good, The Bad, and The Ugly' ***
From: jcooley@world.std.com (John Cooley)
Date: Fri, 29 Sep 1995 00:43:36 GMT
Links: << >>  << T >>  << A >>
      !!!     "It's not a BUG,                         jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                               (508) 429-4357
    (  >  )
     \ - /        "USE/DA Report Card on Cadence Design Systems"
     _] [_                           - or -
                   "Cadence: The Good, The Bad, and The Ugly"

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222


HELP!  As the president of the Users Society for Electronic Design Automation 
(USE/DA) I foolishly signed up to do a detailed report card on Cadence at 
their user's group meeting next week in Boston, Mass.  What I need from you, 
as a Cadence user, is to tell me exactly how you feel about various aspects 
of doing business with Cadence.  ALL CUSTOMER INPUT WILL BE USED ANONYMOUSLY.
(That is, I'll report *what* customers think but not exactly *who* said it.)

My goal is to provide a balanced report card that contains not only where 
Cadence has messed up, but also where they're doing a good job.  I'm an ASIC 
designer so I'd like to ask that you be as specific as possible in what you 
say.  If you love/hate specific things Cadences does/offers, I want to hear 
the specifics.  Feel free to respond on anything, but to get you in an 
evaluation frame of mind, I'll ask:

Please Report Your Primary Interest In Cadence Tools (ASIC design, PCB 
design, Analog IC design, RTL simulation, Full Custom Design, etc):_________

  1.)  What tools do you specifically use (by name)?:

  2.)  What does your company make/sell?

  3.)  Where are you? (City, State, Country)?


 -----------------------------------------------------------------------------

  1.) What do you think of Cadence's on-line & hard copy documentation?  Is it 
  usually very helpful & complete, out-to-lunch, or what? 

  2.) What do you think of Cadence's hotline?  What's the typical turnaround 
  you get for your questions?  Do you feel that you get access to 
  knowlegable experts or new college graduates most of the time?  What do 
  you think of their "We'll call you back" way of running the hotline?  
  How many times have you had to use it in a typical month?

  3.) What do you think of Cadence's local support in your area?  Are they 
  around after your company bought the tool?  Are they helpful?

  4.) What do you think of Cadence's electronic connectivity?  How about 
  SourceLink? Their WWW page?  "comp.cad.cadence" ?

  5.) What do you think about Cadence Spectrum Services?  Has your company 
  lost employees to this?  Have they solved your problems?  Do you like
  Cadence offering such services?

  6.) What do you think about Cadence training?  Have you used there classes?
  Were they very helpful, a complete waste of time or somewhere in 
  between?  Please be specific.

  7.) How do you feel about the Cadence sales force?  Do they talk to you or 
  are they only interested in your VP of Engineering?  Do they help you 
  through business problems year round or only when there a potential 
  sale in the works?  Going from GREAT to HORRIBLE please rank them 
  equal to (choose one)

      - "Ghandi has serious competition compared to my Cadence saleman!" (or)
      - "I want to base my whole life philosophy around you." friends (or)
      - "Please!, Marry my daughter!" good friends (or)
      - Helpful friends (or)
      - Helpful business acqaintances (or)
      - Helpful Deparment store cashiers (or)
      - Indifferent Department store cashiers (or)
      - New Car salesmen (or)
      - Door-to-Door vacuum cleaner salesmen (or)
      - Used Car salesmen (or)
      - Con artists just a few steps ahead of the law (or)
      - Congressmen and/or convicted con-artists 

  8.) What's the most POSTIVE Cadence related experience you've had?  If you 
  were made "Joe-Costello-for-a-day," what would you NOT change about Cadence?

  9.) What's the most NEGATIVE Cadence related experience you've had?  If you
  were made "Joe-Costello-for-a-day," what would you change about Cadence?

 10.) What specifically do you techinally like about their tools?  What's their
  best tool?  What's their worst tool?  Why?  (Give details.)

 11.) Do Cadence's point tools play nice with other Cadence point tools?  Do
  Cadence point tools play nice with non-Cadence tools?  (Give specifics.)

 12.) Overall, how you rank Cadence compared to other EDA companies you've 
  dealt with?  Far better, far worst, about average?

Again, my asking these questions is to get you to tell me what you think 
about Cadence as a whole and concerning specific products & services they
offer.  No names nor sources will be used in reporting the general user 
views of Cadence.  Thank you for your time!  :^)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1991
Subject: Re: Xilinx Flash FPGA ??
From: peter@xilinx.com (Peter Alfke)
Date: 29 Sep 1995 00:45:15 GMT
Links: << >>  << T >>  << A >>
In article <44e440$48q@srv5.esiee.fr>, NICOLAS TRIBIE <tribien@esiee.fr> wrote:

> Can I find a Xilinx 4XXX FPGA with a Flash EPROM ( or an EEPROM ) instead 
> of a SRAM ? 
> 
>  I need to have all the I/O ports free for my application.

Any Xilinx XC4000 as well as any other SRAM-based FPGA from any
manufacturer must receive configuration data from the outside. Master
Serial or Slave Serial configuration modes involve only a single I/O pin (
DIN ), and even that pin can easily be used as a Data pin during normal
operation. ( The clocking pin, CCLK, is a permanently dedicated pin that
can never be used as I/O.)
So you can have all the I/O pins available for your applications, even
with configuration stored in an external SPROM.

What is it you are concerned about?

Peter Alfke
Xilinx Applications


Article: 1992
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: jcooley@world.std.com (John Cooley)
Date: Fri, 29 Sep 1995 00:55:04 GMT
Links: << >>  << T >>  << A >>
In article <44coqq$100@news.Belgium.EU.net>, Jan Decaluwe  <jand> wrote:
>Let's be specific (as this is hopefully not just a coffee shop discussion). 
>The original topic of this thread was "abstract" typing, i.e. using integers, 
>booleans and enum types instead of std_logic types. This is one of the methods 
>to raise the abstraction level, with *tremendous* advantages in terms of code 
>clarity, maintainability and reusability. On the other hand, using these types 
>has no disadvantage in terms of RTL synthesis results (Synopsys DC). 
>If something has only advantages and no disadvantages, one should obviously
>do it.

OK, Jan, since I've been accused of the most unforgivable crime of "Deceptive
Anologies", before the authorities come to take me away to serve hard time,
I'd like to ask: "Are you saying that the VHDL contestants were at a
disadvantage *because* they were brutally forced to use std_logic in
designing a simple 9-bit up/down counter instead of using 'integer'
and 'boolean' data types?"

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1993
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: verschue@eb.ele.tue.nl (Ad Verschueren)
Date: 29 Sep 1995 11:04:56 GMT
Links: << >>  << T >>  << A >>
In article <Pine.SUN.3.91.950928100918.16350D-100000@switha>,
Jonathan AH Hogg  <jonathan@dcs.gla.ac.uk> wrote:
>On 27 Sep 1995, Robert Tjarnstrom wrote:
>
>> If low number of code lines is essential then everybody should be using functional 
>> languages. There you have a significant reduction of code lines. However, we do not 
>> see many applications coded in functional languages. There must be a reason for that. 
>> Anyone has an idea why?? Poor performance ??
>
>indeed we are in the process of producing an HDL toolset written entirely
>in the lazy functional language Haskell. poor performance is a label that
>is acquired early and is very difficult to shake off.
>

  Hear, hear! (but as an aside): our hardware and system simulation tools
  are written in Smalltalk, but that's not the reason I posted this message,
  see below...

>> Tools are clearly better on logic minimization and should of course be used for that.
>> However, I have not seen any tool good at making architectural trade-offs and solutions.
>
>it's still early days yet for hardware synthesis. no-one really
>understands what an HDL should look like. an HDL that's based on a
>software language is not a good starting point in my opinion. designing
>software and designing hardware are two different paradigms. since when 
>did gate arrays have `for' loops? software is based on control flow, 
>hardware is based on data flow.
>
>we need to develop new tools and ways of working, not rubbish the whole 
>concept and go back to rubbing stick diagrams together...
>

  That's it: 'new ways of working'. Our tools combine graphical means for
  stucture definition with textual means for behaviour description - but
  that's old stuff.

  The new stuff is that the textual languages are specifically tailored
  to the behaviour they are meant to describe, i.e. separate languages
  for state machine states or combinatorial operations (*not* logic, we
  do not want to design at *gate* level - let that stuff be done by a
  silicon compiler!). To show off a littlebit, the following expression
  describes a rotating priority encoder:

    nextLine := "Index of highest priority input line, current line index
                 if none is active..."
      ((inputLines ror: currentLine) "Barrel rotator..."
         msone "Read: Most Significant ONE, actual priority encoder..."
           width: currentLine width) + currentLine
               "Counteract the barrel rotator to calculate nextLine..."

  This can be converted into VHDL automatically (it kinda explodes!),
  after which a silicon compiler can sythesize it into optimal logic.
  Note that the number of bits is not given here, it works as long as
  the number of bits in currentLine and nextLine is equal and the number
  of bits in inputLine = 2**(number of bits in currentLine).

  The most innovative part of our tools is that there is no separation
  between designing and simulating - you can't even turn simulation off.
  Designers get immediate feedback and make fewer mistakes, 'what if'
  questions are answered in minutes instead of hours/days.

  We are not only working on hardware design tools, but also on system-level
  design tools, take a look at:

    http://www.eb.ele.tue.nl/proj/idassfly.html

>:-jonathan
>
>-- 
>Jonathan AH Hogg, Computing Science, The University, Glasgow G12 8QQ, Scotland.
>jonathan@dcs.gla.ac.uk http://www.dcs.gla.ac.uk/~jonathan (+44)141 3398855x2069
>

CYA, Ad

-- 
--(dr.ir.) Ad (A.C.) Verschueren-----------------------VERSCHUE@EB.ELE.TUE.NL--
  Eindhoven University of Technology   Digital Information Processing Systems
  Smail: Room EH 10.26 ---- P.O. Box 513 ---- 5600 MB  Eindhoven, Netherlands
  Voice: +31-40-473404   FAX: +31-40-448375   [corner for rent, apply within]


Article: 1994
Subject: Altera Sim. with Leapfrog
From: Martin.Radetzki@arbi.informatik.uni-oldenburg.de (Martin Radetzki)
Date: Fri, 29 Sep 1995 11:28:38 GMT
Links: << >>  << T >>  << A >>
Hi,

we use the Synopsys Design Analyzer together with the technology
libraries provided by Altera for VHDL synthesis targeting Altera
Flex8000 FPGAs. Up to now we have used the Synopsys VHDL Simulator
for simulation of the synthesized netlist. We are trying to
integrate the Cadence Leapfrog simulator into our design flow
because it promises to be much faster.

Unfortunately, the simulation models of the Altera netlist primitives
which are supplied together with version 5.2 of the MaxPlus2 software,
are in Synopsys-specific "encrypted VHDL" (e.g. flex8000_FTGS.vhd.E)
and can not be compiled with Leapfrog. If you know any workaround,
please contact me via email. We have no support from Altera
because our department got their software for free in a university
program.

Thank you in advance,
Martin.

--
Martin Radetzki
Department of Computer Science
University of Oldenburg
email: martin.radetzki@informatik.uni-oldenburg.de
 


Article: 1995
Subject: Altera EPX880QC132-10 Availability?
From: jrw@ipg.umds.ac.uk (J.Walliker)
Date: 29 Sep 1995 15:39:30 +0100
Links: << >>  << T >>  << A >>

This device does not yet appear to be available in the UK.
Is it possible to buy them from USA or elsewhere with 
a short lead time?  I could probably manage with the -12
if this made a difference.

Quantity: 25

John Walliker



Article: 1996
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: torbenm@diku.dk (Torben AEgidius Mogensen)
Date: 29 Sep 1995 14:52:19 GMT
Links: << >>  << T >>  << A >>
ekatjr@eua.ericsson.se (Robert Tjarnstrom) writes:

>If low number of code lines is essential then everybody should be using functional 
>languages. There you have a significant reduction of code lines. However, we do not 
>see many applications coded in functional languages. There must be a reason for that. 
>Anyone has an idea why?? Poor performance ??

The reason few "real" applications are written in functional languages
(here I don't count Common LISP as a functional language, otherwise
the number would be much higher) is mainly tradition. It takes a long
time for new language paradigms to simmer down from academia to the
"real world". The reasons for this is manifold: companies tend to stay
with the languages that they have always used, unless theer is a very
good reason not to. And if they change to a new (very different)
language, their employees need retraining to use it.

Functional languages (even lazy functional languages) are now quite
efficient, so there is no overriding performance reason not to use
them. In fact, it has been argued that using a functional language
allows you to better focus on efficient algorithms instead of just
getting the damn thing to work.

The telecommunications company L.M. Ericsson have developed their own
functional language Erlang, which they use to write communications
software. They have stated that a reason why they don't use Erlang
more than they do, is the lack of programmers with functional language
experience.

As for hardware description, there are people who argue that
functional langauges are well suited for this. The language Ruby (and
its descendant T-Ruby) is based on the functional language paradigm.
One of the stated advantages of this approach is the ability to do
quite powerful correctness preserving transformations within the
language. Though Ruby is functional/relational, the primitives and
combining forms chosen for it are intuitive for hardware designers,
making it natural to use.

	Torben Mogensen (torbenm@diku.dk)


Article: 1997
Subject: Re: cheap (free) fpga design software
From: moby@kcbbs.gen.nz (Mike Diack)
Date: 29 Sep 95 19:46:30 GMT
Links: << >>  << T >>  << A >>
In message <<4470fc$8an@mailman.xilinx>> "Steven K. Knapp, Xilinx, Inc." <stevek> writes:
> While I don't know of any 'free' development software for the
> XC3000,
> I can certainly recommend a low-cost system.
> 
> If you do not have either OrCAD or VIEWlogic, Xilinx also sells an
> integrated VIEWlogic system that includes the schematic editor and
> simulator.  This is called a DS-VLS-BAS-PC1 and sells for less than
> US$3,000.
> 
I suppose "low cost" is open to interpretation, and for some, $US3000 IS
a trivial sum (after all, the cost of OrCAD or Viewlogic must otherwise
be added to the $1k packages), but for the rest of us, the "entry level"
costs of trying Xilinx has always put it out of the ballpark.

> NOTE:  Stay tuned for upcoming announcements on low-cost software
>        solutions from Xilinx.

Is this going to be "Pentagon toilet seat" low cost or real world low
cost ?
cheers
Mike


Article: 1998
Subject: Re: Xilinx Flash FPGA ??
From: yjhou@Qualcomm.com (Y. Jason Hou)
Date: Fri, 29 Sep 1995 13:42:32 -0700
Links: << >>  << T >>  << A >>
In article <44e440$48q@srv5.esiee.fr>, NICOLAS TRIBIE <tribien@esiee.fr> wrote:

> Can I find a Xilinx 4XXX FPGA with a Flash EPROM ( or an EEPROM ) instead 
> of a SRAM ? 
> 
>  I need to have all the I/O ports free for my application.
> 

What's story on Zycad's GateField chips?  They announced FPGA chips
with flash eprom capability long time ago.  Has anyone used them?
Any comment on their devices?


Y. Jason Hou,
Qualcomm Inc.,
yjhou@qualcomm.com


Article: 1999
Subject: AT&T ORCA usable gate count?
From: Chelman Wong <chelman@hal.com>
Date: 29 Sep 1995 21:36:22 GMT
Links: << >>  << T >>  << A >>
Can anyone tell me how the usable gate count
for the AT&T ORCA's is calculated?

And what is the general rule of thumb as to
how many gates/cells and I/O's are really
usable in a design?

Thank you.





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