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Messages from 2400

Article: 2400
Subject: Re: Lattice GAL16VP8 -is it real ?
From: devb@lys.vnet.net (David Van den Bout)
Date: 28 Nov 1995 19:30:58 -0500
Links: << >>  << T >>  << A >>
In article <1995Nov28.225208.454@decus.org.nz>,
 <granville@decus.org.nz> wrote:
>We were told of a LATTICE GAL16VP8, which is rumoured to have HYSTERESIS
>but the LATTICE rep in Sydney seems to prefer hibernation to selling.
>We have Phoned / Faxed / Phoned, and still are none the wiser.
> 
> Does this part exist ?

My 1994 Lattice data book lists this device.

>
> What is it worth ?

??? This is probably a question for a philosophy major.
As to what it might COST, it looks like a device that should
cost a couple of bucks in quantity.

>
> Is it std pinout ( AMD had/dropped a 16V8HD, that was non-std )

The pinout doesn't look standard.  It comes in a 20-pin DIP with
VCC on pin 5 and GND on pin 15 to reduce the inductance of the
power inputs.  Also comes in a 20-pin PLCC

> What else is there, with hysteresis ?

There's the GAL20VP8.  Comes in a 24-pin DIP with VCC/GND on pins
6/18.  Also comes in a 28-pin PLCC.

-- 
|| Dave Van den Bout  --  XESS Corp. ||
|| 2608 Sweetgum Dr., Apex, NC 27502 ||
|| (919) 387-0076 FAX:(919) 387-1302 ||
|| devb@xess.com       devb@vnet.net ||


Article: 2401
Subject: subscribe
From: SHAR@shams.eun.eg
Date: Wed, 29 Nov 1995 10:12:06 GMT
Links: << >>  << T >>  << A >>
subscribe


Article: 2402
Subject: Opinions on Cadence FPGA designer
From: benedett@iago.dsi.unimo.it (Arrigo Benedetti)
Date: 29 Nov 1995 17:26:20 GMT
Links: << >>  << T >>  << A >>

We are considering Cadence as a vendor for a complete high level synthesis
system targeted to Xilinx FPGA's, as an alternative to Viewlogic.
For this reason I would like to hear impressions from people using
Composer/Concept for design entry, Synergy for design synthesis,
Leapfrog for behavioural VHDL simulation and FPGA Designer for FPGA
optimization.

Thanks in advance (I'll post a summary if there is interest),

-Arrigo Benedetti
--
Arrigo Benedetti                          e-mail: benedett@dsi.unimo.it
University of Modena                           abenedetti@deis.unibo.it
address: Via Vivaldi, 70 41100 MODENA - ITALY
phone: (home) + 39 59 224929 (office) +39 59 304057 (fax) +39 59 220727
http://deis12.cineca.it/~benedett/   <-- under construction !


Article: 2403
Subject: Re: Xilinx XACT Windows Version
From: dstarr@world.std.com (David J Starr)
Date: Thu, 30 Nov 1995 01:54:11 GMT
Links: << >>  << T >>  << A >>
ecla@world.std.com (alain arnaud) writes:

>Joe Samson (samson@ptd10c.erim.org) wrote:
>: >I have trouble installing XAct for Windows. The problem is that the dongle 
>: >can't be found by the software. Any idea??


>	This problem is due to the new parallel port modes (EPP, ECP, 
>	bidirectional, compatible and unidirectional). The key licensing
>	software is very sensitive to that set-up, you should set-up
>	the parallel port in BIOS set-up to either compatible or 
>	unidirectional.

>	Another solution is to install an "old" parallel port card,
>	what I mean by that is an XT or AT vintage card, that will also
>	do the trick.

>	I am one of the first external beta testers for XACT 6 (for windows)
>	and encoutered this problem the first time I installed the software
>	on a Gateway P5-120 and a Thinkpad 755cx. On the Gateway, hit F1 at 
>	reset, go into peripheral config and change the parallel port mode to
>	compatible. On a Thinkpad, same procedure but select unidirectional.
>	Other PCs have similar set-ups.

>	For more info or help pn XACT 6.0, feel free to email me 
>	at arnaud@ecla.com

>	--Alain
 Gee. I'm so glad to hear that  the really user friendly XACT 6 still can't
find its dongle.  I just live for moments when I have to spend half a day 
getting the Xylinx dongle to work.  I'll shift vendors at the drop of a 
hat to get away from dongles and XACT.
.



Article: 2404
Subject: Re: Xilinx XACT Windows Version
From: ecla@world.std.com (alain arnaud)
Date: Thu, 30 Nov 1995 14:51:21 GMT
Links: << >>  << T >>  << A >>
David J Starr (dstarr@world.std.com) wrote:

:  Gee. I'm so glad to hear that  the really user friendly XACT 6 still can't
: find its dongle.  I just live for moments when I have to spend half a day 
: getting the Xylinx dongle to work.  I'll shift vendors at the drop of a 
: hat to get away from dongles and XACT.

	Have you tried XACT 6? 

	The dongle problem was only an early beta issue. It has been
	fixed. XACT 6 has a Windows GUI, it is much more user friendly
	than the DOS version, the addition of the floorplanner is extremely
	helpful. There's a very nicely done online tutorial.

	I have seen novice users being productive in less than a day.


	--Alain


Article: 2405
Subject: Re: NeoCAD and AT&T vs. Xilinx
From: Eric Dellinger <ericd@aimnet.com>
Date: 30 Nov 1995 16:32:27 GMT
Links: << >>  << T >>  << A >>
zuk@ll.mit.edu (W. S. Zuk) wrote:

>Which "new FPGA families" will you support?
>
>That is, Xilinx families only, or also non-Xilinx families?
>
>Will you support AT&T Orca?

Xilinx will support its own families. Even if we wanted to support
a competitor's part, we couldn't.  AT&T has no intention of sharing
the details of its technology with Xilinx (rightfully so).

I am personally still a proponent of third-party software support
for FPGAs, perhaps even a public domain system.  If NeoCAD could
do it, why not Cadence?

==eric 



Article: 2406
Subject: Re: Xilinx XACT Windows Version
From: dstarr@world.std.com (David J Starr)
Date: Fri, 1 Dec 1995 03:46:43 GMT
Links: << >>  << T >>  << A >>
Has XACT 6 been released yet?   Can us 5.1 users get an upgrade for free?
for a little bit of money?  for lotta bread?  
David J. Starr



Article: 2407
Subject: INDUSTRY GADFLY: The Fall(ing) VIUF '95
From: jcooley@world.std.com (John Cooley)
Date: Fri, 1 Dec 1995 08:22:05 GMT
Links: << >>  << T >>  << A >>
  [ Occassionally I'll be putting on the Internet articles I've written for 
    the U.S. trade pubs (after they've been published) because:

    - I've received very positive responses while doing this from engineers
      who can't get these pubs yet want the news (namely the Europeans, the 
      Japanese, the Austrailians, & the academics greatly appreciated it.)

    - The Internet lets me explore ideas thoroughly because there's no space
      limitation in publishing.  (Trade Pubs usually limit article sizes.)

    - Most importantly, I know I don't know everything.  I want to encourage
      my fellow engineers to tell me if I'm right/wrong/somewhere-in-between
      and *WHY*.  (It helps in future articles -- write me!)

    (As always, please indicate what parts of your reply are not publishable
     otherwise I default to it being *completely* publishable.)   - John ]


      !!!     "It's not a BUG,                          jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                                (508) 429-4357
    (  >  )
     \ - /    
     _] [_          INDUSTRY GADFLY: "The Fall(ing) VIUF '95"

                               by John Cooley

        Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222


Sparce Attendance
-----------------

After attending the Fall meeting of the VHDL International Users Forum (VIUF)
last week in Boston, it was painfully obvious that the six year old VIUF was
in trouble.  I can now verify the rumors that VIUF was having serious
problems attracting attendees after I personally counted, at the height of
the conference, only 156 people watching the 11:00 AM Exective Panel plus an
additional 23 others I found either milling around in the hallway or setting
up demos in the exhibit room.  This count matched similar private reports
that I had heard concerning the last 4 or so VIUF's.  (To put it in
perspective, VIUF's linguistic arch-rival, the International Verilog
Conference (IVC) went in three years from 213 attendees in 1992 to a record
510 attendees at this last March's IVC.)

I'd rather not waste your time interpreting why VIUF is hurting but will warn
you that it may not be because the VHDL language itself has failed to catch
on in the U.S. market.  That is, it's possible that VIUF may be severely
stunted because it meets every six months while IVC meets just once a year.
(Hopefully this will change with co-locating the two conferences next year.)


Tutorials
---------

Out of the Sunday tutorials, quite a few users gave positive comments on Joe
Pick's (from Synopsys) VHDL coding and VHDL synthesis tutorials.  (Because I
teach synthesis as a business, I was more interested in Steve Ives' and Elise
Campbell's [both from Top Down Design] tutorial on memory modeling with VHDL
because some of it was new to me.)  A number of engineers commented it was
interesting to see Janick Bergeron's (from Qualis) Verilog/VHDL and
VHDL/Verilog tutorials at an obstensively pro-VHDL conference.


The Papers
----------

>From the VIUF proceedings, I was quite interested in a paper presented by
four Raytheon engineers that had actual metrics accompanying a discussion
about enhancing design productivity using i-Logix tools and the mysterious
Synopsys Behavioral Compiler.  (The mystery is because users have been
having a hard time getting detailed non-Synopsys opinions on Behavioral
Compiler.)

                     Manual RTL Approach     Behavioral Compiler Approach
                    ---------------------    ----------------------------
 Design Methodology   RTL VHDL Top-Down          Behavioral Top-Down
      Lines of VHDL        23.8K                       4.6K
         Gate Count         90K                      about 50K
    Simulation Time    450 mins/frame              19 mins/frame
    Detailed Design    3360 man-hours             1512 man-hours
    Design Duration       4 months                   3 months

  fig. 1)  Raytheon metrics comparing RTL vs. Behavioral design approaches.


The Empty Exhibit Hall
----------------------

Most of the time the 18 vendor exhibit hall was a bowling alley completely
free of customers.  It was such a ghost town, even the EDA salesmen
themselves eventually ran out of industry gossip and sports stories to share
because they had been so recycled with those in the room.  (It even got to
the point where Fred Stones of Summit Design announced the birth of his son
from ten days earlier just to have a new story.  Micheal Andrew Stones, 7 lbs
14 oz.)  More than once when I walked into a vendor's booth I would be met
by a suddenly rejoicing tech/sales staff because it meant that they'd finally
get to give at least one demo that day!

In the Cadence booth I found the salesdroids bubbling over what they were
reading in the EuroDAC '95 proceedings.  What we both saw looking over the
proceedings was a no-nonsense user-driven benchmark done by an engineer at
Siemens (Eugen Rohm) that used large and realistic test models (like 8051's
and "KOM", a 41160 lines of code telecom ASIC) showing Leapfrog 2.1 kicked
butt!  My kudos to the Cadence Leapfrog R&D team.  Job well done.

           Synopsys      IKOS   Model Tech  Vantage    Cadence      Zycad
 DESIGN   V3.2 / V3.0a   V1.41     V4.2      V5.0    Leapfrog 2.1  ViP 2.1
 -------------------------------------------------------------------------
  VSK      2.1 /  1.3     1.0       2.0       1.1        1.0          *
  8051      *  /  4.4     3.9       2.5       4.6        1.0          *
  LCD      1.1 /  3.5     2.7       1.7       3.1        1.0         0.3
  BADGE     *  /  8.0    16.9       4.5       3.6        1.0          *
  DIVI     6.3 / 17.9     8.1       5.7       7.0        1.0         4.8
  INV1000  2.7 /  4.3     1.7       1.3       1.6        1.0         0.3
  KOM      4.6 / 12.3     6.0       4.8       4.6        1.0          *
  SIG      3.6 / 31.7      *        2.6       5.2        1.0         0.4
  SPARC    1.0 / 11.8     1.8       2.2       3.3        1.3         0.3
 -------------------------------------------------------------------------

  fig. 2) Siemens VHDL benchmark simulation run times normalized to the
          fastest software simulator.  ("*" - design could not be simulated.)


The Gossip & News
-----------------

SpeedSim's CEO, Don McInnis, was pleased to be beta-ing a Verilog front-end
reader to his SpeedSim/3 cycle-based simulator.  (He plans to be working on a
VHDL front-end reader sometime later.)  By design, SpeedSim/3 accelerates
gate models.  Originally you had to use Synopsys to get to gates quickly for
SpeedSim/3 to work.  By adding front-end readers, SpeedSim/3 loses its
dependence on Synopsys.

While ViewLogic was demo-ing their Verilog/VHDL co-simulator, what was more
interesting was my first look their cycle-based simulator, Ultraspec.

The i-Logix people were very tired going shuttle crazy because VIUF scheduled
on the exact same days that i-Logix scheduled their user's group meeting.

My Exemplar contacts were quite pleased with their recent 3.1 release, code
named the "ORCA release," because they added look-up table optimization to
support AT&T's ORCA FPGA's (which had the added side-effect of helping how
Exemplar synthesizes some Xilinx FPGA's.)

One of the more esoteric products I saw was VitalGen, a tool that generates
VITAL 3.0 complient libraries, from the VHDL Technology Group.  Their CEO,
Bill Billowitch, was very active in creating the VITAL spec, so I'm sure
VitalGen will do its job well -- yet this $15,000 highly specialized software
will probably sell only about 30 to 50 copies because only the ASIC vendors
themselves would be interested in creating VITAL libraries.

The one new vendor face I saw at VIUF was Sand Microelectronics, a company
peddling a PCI performance analyzer and protocol/timing checker called "PPA."

By and far, the most interesting product I saw at the Boston VIUF was a
clever software concept made into a very, very useful hardware designer's
tool.  This $12,000 tool from VEDA Design Automation is called VHDLCover.
VHDLCover determines if a set of functional test vectors you have exersizes
every part of your source code or not.  It checks all the possible branches
plus all the possible conditions used to select branches plus all the
permutations of paths going through your source code.  It's also useful
for checking state machines plus some race conditions and hazzards.  (The
Verilog version is coming out in December.)  I was very impressed.  Either
phone (408) 496-4516 or e-mail "allenbaugh@usveda.com" for more info.

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3881 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2408
Subject: Industry Trends
From: steve@gcatohm.demon.co.uk (Steve Jones)
Date: Fri, 01 Dec 1995 08:34:52 GMT
Links: << >>  << T >>  << A >>
On 23 Nov 1995 00:08:19 GMT, Jack Sandell <J.Sandell@CQU.Edu.Au>
wrote:

>
>I see that someone else has my problem.   Due to the lack of finance I am only able 
>to teach 20 on-campus students how to design using FPGAs.   I need a sub-set of the 
>Xilinx 2064 or 3020 so as to post them to hundreds of off-campus students who 
>are using a 386 or better.  
>
>Rowland Hill introduced the postage stamp so that the average person could afford to 
>send letters.   Look at the postal industry today.
>
>How about some cheap, student introductory versions able to be purchased with a text 
>book similar to MicroLogic etc.
>
Exactly the same here. I need 'free' simple to use tools for my
students, to be able to teach them the basics of PLDs and FPGAs.
Anyone have a list of sites offering these?

Steve Jones                   steve@gcatohm.demon.co.uk
Gloscat, Electronics
Glos. College of Arts & Technology, UK
{All opinions are my own}



Article: 2409
Subject: Re: NeoCAD and AT&T vs. Xilinx
From: David Pashley <david@fpga.demon.co.uk>
Date: Fri, 01 Dec 95 16:52:44 GMT
Links: << >>  << T >>  << A >>
In article <49kmar$19p@news2.aimnet.com>
           ericd@aimnet.com "Eric Dellinger" writes:

"Xilinx will support its own families. Even if we wanted to support
"a competitor's part, we couldn't.  AT&T has no intention of sharing
"the details of its technology with Xilinx (rightfully so).
"
"I am personally still a proponent of third-party software support
"for FPGAs, perhaps even a public domain system.  If NeoCAD could
"do it, why not Cadence?
"

Many have tried and fallen by the wayside - it seems that it's just 
not an easy thing to do.

Still, for anyone that does try, the prospect of it being worth an 
eight figure sum for Xilinx to stop them would be attractive...;-) 

I think that the current trend towards standardisation in design 
capture (LPM libraries for schematics and LPM macrogenerators 
instead of proprietary hard macros) is a positive step.

Users want (and will get) a completely vendor-independent design 
environment, and the place and route should be just a low-cost or 
free back end fitter, with no need to learn detailed architecture-
specific tricks. 

The maturing market will ultimately work against vendors' attempts 
to lock users in to their architecture by making them buy expensive 
place and route tools. The vendors know this, and will eventually 
drop the price rather than lose market share.

 
-- David Pashley              



Article: 2410
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: cburton@chch.planet.org.nz (Chris Burton)
Date: 1 Dec 1995 19:59:14 GMT
Links: << >>  << T >>  << A >>
The best designers are experienced designers. The tools and the techniques 
just help you achieve results. Consider embedded software design. Most 
managers have pushed moving from assembler to C for obviously good reasons, 
except the one reason "We can then bring in people with just C experience, who 
are much easier to find, and they will be able to do the job". I've heard that 
such people are really good at writing "functional requirements" specs for new 
product development because of their obviously superior generic abilities, and 
their top-down OOA and OOD will ensure the products success. Crap. Has anyone 
noticed that people like that start suggesting things like....

1) The design should use an embedded '386, have 1M DRAM, and run windows '95.

2) Can you solder these peices of wire for me, it's not my job as a software 
designer to work as a team.

3) Lets impliment a much more efficient key board scanning algorithm...one 
that constantly polls the key board in the background because it fits into my 
design methodology.

4) We need to run this MPU at 4 times the speed.

5) I've used a novel approach to the keyboard design. When you turn the 
product 'OFF' the MPU continues polling the ON button.

People might laugh but these sort of things can happen...in my application it 
was a handportable radio. These things were suggested to me...they would have 
killed the product. Decoupling the design from the hardware tends to ignore 
physical realities. Imagine designing a PCB without any knowledge of the shape 
the the mechanical box. Then theres always the issue of cost, and how to 
reduce it. For years I've scrapped and struggled to save every cent out of 
designs that have saved millions for the company, and have ensured a 
competitive product.

An experienced designer does middle out design. He spends a bit of time above 
and below, he re-works the design when it doesn't fit, he might backtrack 
occasionally on the approach. This might not appear as efficient as "TOP-Down" 
design practice by the novices out there, but I would any day bet a weeks 
salary that such an individual will beat a binary head Mellor-Mellon any day. 
An experienced designer knows the critical paths in the design, and those that 
could have the biggest impact if incorrect and concentrates upon them. In many 
applications, this means implement and test. For example...I DEFY ANYONE TO 
TELL ME THAT THEY CAN DESIGN STABLE HIGH POWER CLASS C RF TRANSMITTERS that 
work under extremes of temperature, VSWR, and supply voltage over wide 
bandwidths without  playing with the hardware from the outset. The best 
technique is to sit there with your prototype, with Jomega, Touchstone or 
whatever simulation package you have and dick around with both simultaneously. 
Then you put a VCO next to it, and both the VCO and the transmitter will need 
an undefined amount of redesign.

The ASIC guy without experience looks at the gate count and goes "Yippee", 
when I tweek this parameter, then gate count halves. But the multiplier 
shouldn't be a shift and add, I reply, or blimey, why is this chip so current 
hungry and why do I need ten times the clock frequency? Also you get..."we 
could impliment a DDS to do the 70kHz Saw tooth generator for the PWM 
design" (when two or three components would do it for less current, and at a 
fraction of the price) I've heard some disturbing crap from people pushing 
synthesis as the answer to everything. Some of the innovative circuits I've 
seen have been simple, and made fundimental improvements to the whole design 
because the designer could see the whole picture, including the gates. 
Synthesis allows the idiot to write marginal software, but it allows the 
experienced designer to design excellent hardware. Synthesis is the answer to 
everything...so says the software designer.

I'm getting into mixed signal ASICs now, and I'm a proud tinkerer. Try to stop 
me playing with the hardware...thats my canvas, and my designs will indeed be 
elegant and beautiful to behold after lots of iterations and mistakes. I'll 
model things as best I can, but I know a will not account for every effect 
inside and outside the chip. 

Digital Softcock Dudes....your days are numbered...asynchronous mixed signal 
multi-level logic RF/DSP/Analogue/MPU high voltage power mosfet 
monolithic designs for battery applications will arise to torment your 
inexperienced souls. HA, I laugh at your impending doom!


Article: 2411
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: cburton@chch.planet.org.nz (Chris Burton)
Date: 1 Dec 1995 20:46:15 GMT
Links: << >>  << T >>  << A >>
In article <44b8mv$4lp@euas20.eua.ericsson.se>,
   ekatjr@eua.ericsson.se (Robert Tjarnstrom) wrote:
>In article <Pine.SUN.3.91.950926102636.12680L-100000@switha>, Jonathan AH 
Hogg <jonathan@dcs.gla.ac.uk> writes:
>>
>>or you use a high-level language designed for real-time systems. one that 
>>allows you to specify the architecture of the system (such as the size 
>>and shape of device registers), respond to interrupts in a controlled 
>>manner, manage concurrency with deadlines, do exception handling, and 
>>produce memory and type-safe programs. you cannot write any seriously 
>>sized system in assembler and be sure of its operation.

It comes down to design methodologies more I think. People have been taught to 
write structured C, but not assembler. Many companies have been using 
assembler for years, and are no better off because of their design 
methodologies.They concentrate on moving to C for portability, and speed of 
code writing reasons, but if you start really looking at it, it's because the 
assembler designs of the companies past are poorly designed, undefined and bug 
ridden because nobody really knows how they work...being undocumented. I've 
written a considerable amount of DSP code, and made extensive use of macros, 
which are incredibly flexible. My macros can become a defined library, as can 
software modules. They can be re-used easily if they are defined in some 
manual somewhere, and comply with some extremely simple rules. Soon the 
code looks like a high level language, with the difference that the 
language is optimised to your application. Whats more, I can hire some PLEB 
student over the holidays to knock up the modules targeted for a different 
platform, or maybe get a cowboy to write a re-targeter. It's definition and 
education that was missing. I wouldn't suggest anyone starting from scratch on 
new software designs to use assembler if the design is complex...use a high 
level language. What I'm saying is that with the amount of assembler companies 
have written in the past, they should find it pretty bloody easy by now, 
should be able to utilise in-house proven tested modules to speed up and 
increase design security but no...the boffins were all inexperienced hardware 
designer cowboys and cowgirls and couldn't be bothered doing things right.

>>
>If you have sifficient time available you could use any language I guess. The 
>problems show up when you do not meet the deadlines. You can follow two 
paths.
>A. you make an analysis resulting in an implementation you can show will 
work, then 
>you code in assembler. B. You implement in a high-level language. Then you 
start an iteration of re-coding and re-verifying. If you are lucky you will 
finally meet the 
>deadlines. I do not find the latter path advantageous, but rather 
frustrating. You 
>have given away control of what you are doing.
>
>What you can do following path B is to lower performance of the product so 
you do not  
>have to iterate too much, which I guess is the common solution. That may also 
be the 
>right way to go if customer satisfaction can be fulfilled.

The customer is the thing many people lose sight of. 

>
>(We are indeed moving away from the original issue of making architectural 
decision
>in hardware design).
>
>>it has been shown that a programmer produces approximately seven lines of 
>>working tested code a day, in _any_ language. if you use a rich language 
>>then you can get a lot more for those seven lines than if you use 
>>assembler.

I've always wondered how software designers keep there job. Maybe this is 
where all the bugs come from...we have ten fingers not seven.

>>
>If low number of code lines is essential then everybody should be using 
functional 
>languages. There you have a significant reduction of code lines. However, we 
do not 
>see many applications coded in functional languages. There must be a reason 
for that. 
>Anyone has an idea why?? Poor performance ??

the lowest number of code lines is machine code hex with no carriage returns. 
I prefer binary people (people that say yes and no) to the DC people who only 
say "yes".

>
>>assembler is something one resorts to, not chooses. for a long time a lot 

True...but if you are given the choice of redesigning the whole software 
package, and some of the hardware and you have to tell your boss it's 
going to take longer and cost more in order to implement high level language, 
or you can re-write three lines of code and be finnished with it, some people 
might chose option two.

>
>Certainly, if I can solve a problem using, for instance, ML instead of 
assembler
>I do it. (Actually, it was a long time ago since I used assembler myself).
>
>>
>>just like compilers, synthesisers are steadily improving. we are still at 
>>the beginning of understanding how to design hardware systems using 
>>abstract specifications. but as hardware/software co-design becomes more 
>>and more important, so will hardware/software co-synthesis. just as in 
>>computing you must realise that in the future ASICs will not be designed 
>>by people who know all about transistor models, but by people who can 
>>analyse a problem and specify it in an HDL.
>>

This is crap. Some designs will be like this...especially low spec'ed VLSI 
designs. I want to here from ANYONE WHO HAS USED A SYNTHESISABLE 68000 or 
similar core, and implimented the synthesised solution in a product in a high 
speed design. Whenever you push the limits you get back to basics.

Many people refer to ASIC synthesis as HIGH level...this is fine UNLESS YOU 
ARE HAVING TO WRITE THE CORE THAT THE DESIGN HAS TO FUNCTION ON BEFORE YOU CAN 
WRITE THE ALGORITHMS THEMSELVES this is worse than assembler...at least with 
assembler you an MPU for things to run on.

>
>Tools are clearly better on logic minimization and should of course be used 
for that.

Agree.

>However, I have not seen any tool good at making architectural trade-offs and 
solutions.

YEP, and you wont either.


Article: 2412
Subject: Atmel Web Site
From: Scott Evans <scott@atmel.com>
Date: Fri, 01 Dec 1995 17:36:41 -0800
Links: << >>  << T >>  << A >>
Just wanted to announce that the Atmel home page is now available:

http://www.atmel.com


Article: 2413
Subject: Re: PC VHDL synth for FPGA?
From: Maurice Moore <100524.16@CompuServe.COM>
Date: 2 Dec 1995 09:01:57 GMT
Links: << >>  << T >>  << A >>
>From Maurice Moore, Gyldan Associates, UK.

Altera supply a PC based VHDL compiler for their FPGA's. I am just 
starting to use it and so as yet I have no firm opinion on its 
cost/performance. 

100524.16@compuserve.com


Article: 2414
Subject: Re: Xilinx XACT Windows Version
From: Baskaran Kasimani <jothi@singnet.com.sg>
Date: 2 Dec 1995 12:06:50 GMT
Links: << >>  << T >>  << A >>
There is a bug in the dongle detection program.

They have a patch disk with version 6.X which need to be installed after installing the 
software but prior to running the software for the first time. Otherwise it will screw up the 
things. Send a email to Xilinx and they will assist you.

jothi@singnet.com.sg




Article: 2415
Subject: Re: Xilinx XACT Windows Version
From: Baskaran Kasimani <jothi@singnet.com.sg>
Date: 2 Dec 1995 12:09:18 GMT
Links: << >>  << T >>  << A >>

If you have maintenance contract they give you a free upgrade. We paid US$ 2600+ for 
reinstating our contract as it expired without our knowledge. It is definitely worth is as the 
routing is very good. Our earlier design did not fit well in the 4003, and we were using the 
4005. Now the 6.0 is able to route the same circuitry for the 4003. 

jothi@singnet.com.sg




Article: 2416
Subject: Re: Industry Trends
From: devb@lys.vnet.net (David Van den Bout)
Date: 2 Dec 1995 09:14:59 -0500
Links: << >>  << T >>  << A >>
In article <817807032.25657@gcatohm.demon.co.uk>,
Steve Jones <steve@gcatohm.demon.co.uk> wrote:
>On 23 Nov 1995 00:08:19 GMT, Jack Sandell <J.Sandell@CQU.Edu.Au>
>wrote:
>
>Exactly the same here. I need 'free' simple to use tools for my
>students, to be able to teach them the basics of PLDs and FPGAs.
>Anyone have a list of sites offering these?
>

XESS Corp. makes a kit that includes a textbook of lab exercises
and a PC-based FPGA prototyping board with software.  Price is $165.95.  
You can check it out at http://www.xess.com.  You will also find some
FPGA tutorials there.

Marketing mode off.

Good luck.


-- 
|| Dave Van den Bout  --  XESS Corp. ||
|| 2608 Sweetgum Dr., Apex, NC 27502 ||
|| (919) 387-0076 FAX:(919) 387-1302 ||
|| devb@xess.com       devb@vnet.net ||


Article: 2417
Subject: Free C hardware synthesizer available
From: Christian.Iseli@di.epfl.ch (Christian Iseli)
Date: 02 Dec 1995 15:39:58 +0100
Links: << >>  << T >>  << A >>
Hi folks,

As a part of a larger project, I have developed a C++ to netlist
compiler. The main goal is to be able to emulate the generated
hardware by compiling the source code with a regular C++ compiler.
The targeted hardware is mainly FPGA chips.

I actually compiled code all the way into Xilinx chips. And they
run. I think this compiler might be of some interest to other
researchers, so I decided to make it freely available under a GPL type
of licensing.

At the current time, the compiler:
  - is written in C++. Can be compiled by g++ 2.7.2
  - needs the LEDA 3.3 library (available by anonymous ftp).
  - will directly generate ViewLogic WIR files and the associated
    symbols. It should be easy to add some code to have it generate
    netlists of different format.

The target (FPGA) architecture is described directly in the source
code, preferably in an included file. Thus it should be extremely easy
to generate netlists for different FPGA architectures. A partial
description of the XC4000 and XC6200 families is provided in the sources.

This is still beta quality code. The documentation is very sparse.

How to get it:
  ftp://lslsun5.epfl.ch/pub/nlc-0.9.tar.gz
then look at the README file for terse explanations on how to build...

I'll also put a compiled binary version for sparc, Solaris 2.4 (sorry,
this is all I have access to...), file nlc-0.9.bin.gz

There is a Majordomo mailing list for discussion about nlc. To be
added to the list, send a message containing the line
subscribe nlc
to majordomo@lslsun.epfl.ch. The subject is irrelevant.

If some folk manage to compile nlc for some other platform, they can upload
the binary on lslsun5 and tell the list...

I'm in the process of writing my PhD thesis at the moment... There is a
chapter on this compiler. I'll make it available as well in the file
nlc-chapter.ps.gz on the same server.

Take care,
					Christian Iseli
-- 

					Christian Iseli
					LSL-DI-EPFL
					Lausanne, Switzerland


Article: 2418
Subject: New ALDEC tools for XACT 6.0
From: Manoj Chaubal <manoj_chaubal@psilongbeach.com>
Date: 2 Dec 1995 21:00:38 GMT
Links: << >>  << T >>  << A >>
Have anybody used new ALDEC tools for Xilinx FPGAs?  They are supposed to 
integrate with XACT 6.0 very well.  The tools consist of schematic entry, 
functional/timing simulation, and simulation waveform generator etc.




Article: 2419
Subject: Re: NeoCAD and AT&T vs. Xilinx
From: ian@PROBLEM_WITH_INEWS_GATEWAY_FILE (Ian McEwen)
Date: Sat, 2 Dec 1995 21:45:07 GMT
Links: << >>  << T >>  << A >>
Eric Dellinger (ericd@aimnet.com) wrote:
: zuk@ll.mit.edu (W. S. Zuk) wrote:

: >Which "new FPGA families" will you support?
: >
: >That is, Xilinx families only, or also non-Xilinx families?
: >
: >Will you support AT&T Orca?

: Xilinx will support its own families. Even if we wanted to support
: a competitor's part, we couldn't.  AT&T has no intention of sharing
: the details of its technology with Xilinx (rightfully so).

This does not sound like the Eric Dellinger I once knew, the one who
helped found NeoCAD, the one who reverse-engineered the bitstream
and fusemap formats of FPGA parts like Xilinx and Actel, without any
support from these companies.  If Eric and the other founders had
thought this way, NeoCAD would never have become more than idle 
thoughts.

Eric's explanation has the rhetoric of an official company line, but
the truth is, when Xilinx purchased NeoCAD, it took that company's
ideal of *vendor* independence out behind the shed, and put a bullet
in its head.  Xilinx will likely retain the *device* independent part
of NeoCAD in order to try to support the boatload of new parts they
are developing.

Although the vendor independent FPGA solution which was NeoCAD is
dead, and no alternative appears forthcoming, at least the successful
techniques which NeoCAD developed are not lost.  Both AT&T and
Xilinx will provide product offerings based upon the software
foundation created at NeoCAD.  Customers of both companies may still
benefit from NeoCAD's efforts.

-- Ian

(Opinions expressed are my own, not my employer's, past or present)



Article: 2420
Subject: Re: NeoCAD and AT&T vs. Xilinx
From: lazzaro@snap.CS.Berkeley.EDU (John Lazzaro)
Date: 2 Dec 1995 22:16:24 GMT
Links: << >>  << T >>  << A >>
In article <DIzB38.Fyn@nntpa.cb.att.com>,
Ian McEwen <ian@PROBLEM_WITH_INEWS_GATEWAY_FILE> wrote:
>Although the vendor independent FPGA solution which was NeoCAD is
>dead, and no alternative appears forthcoming, at least the successful
>techniques which NeoCAD developed are not lost. 

I see a parallel with the airline industry here: PSA delighted the
intra-California shuttle customer base for years, until USAir bought
them and changed the nature of the shuttle service. Within a few
years, Southwest invaded the intra-CA market and re-implemented large
parts of the PSA strategy, and soon captured 50% of the shuttle
market. If the idea of vendor-independent FPGA solutions still has
customer resonance, someone will replay the NeoCAD story in the same
way, and reap the same financial rewards.
-- 
-------------------------------------------------------------------------------
John Lazzaro                My Home Page: http://http.cs.berkeley.edu/~lazzaro
lazzaro@cs.berkeley.edu     Chipmunk CAD: http://www.pcmp.caltech.edu/chipmunk/
-------------------------------------------------------------------------------


Article: 2421
Subject: Re: Atmel Web Site
From: hobart@rain.org (Kirk Hobart)
Date: Sun, 03 Dec 1995 02:18:38 GMT
Links: << >>  << T >>  << A >>
Scott Evans <scott@atmel.com> wrote:
>Just wanted to announce that the Atmel home page is now available:
>http://www.atmel.com

I just tried it and Netscape said "Server does not have DNS entry."

Maybe it takes a while for domain names to propagate through the net
_________________________________________________________
Kirk Hobart   Santa Barbara, California   hobart@rain.org


Article: 2422
Subject: Re: Xilinx XACT Windows Version
From: "Steven K. Knapp, Xilinx, Inc." <stevek>
Date: 3 Dec 1995 21:04:12 GMT
Links: << >>  << T >>  << A >>
If you run into any "dongle" or key problems with Xilinx software,
please contact our Technical Support Hotline at 1-800-255-7778 or
via E-mail at 'hotline@xilinx.com'.

We believe this to only affect a small number of machines, but as
a fellow engineer, I know that it is frustrating if you have one
of those machines.

-- Steve Knapp
   Xilinx, Inc.



Article: 2423
Subject: Re: PC VHDL synth for FPGA?
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Mon, 04 Dec 95 04:44:42 GMT
Links: << >>  << T >>  << A >>
We used Altera VHDL synthesizer; it worked ok, as I recall.
However, it has restrictions on type conversion functions (you aren't allowed 
any), so you must code everything using just the standard types, as I recall.

Their generation of back-annotated VHDL netlists was bang-on with the 
simulations we ran in the Altera simulator, using their AHDL netlist, so I 
think that's pretty solid.

The tools generally seemed to be pretty robust, in general.

Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2424
Subject: Re: NeoCAD and AT&T vs. Xilinx
From: Darren Wedgwood <Darren>
Date: Mon, 04 Dec 1995 09:51:14 GMT
Links: << >>  << T >>  << A >>
On the subject of NeoCAD being swallowed by Xilinx, John Cooley wrote;

> I heard the same thing about AT&T hiring a number of the NeoCAD developers
> away from the Xilinx purchase. This gives AT&T a way out of their reliance
> on NeoCAD problem... but I wonder what Motorola FPGA is doing to solve this
> same problem.


The Motorola situation here always differed to AT&T in two ways ;
	- Motorola silicon was not yet ready for market and hence
	  the problem was not as urgent
	- there was always a twin track approach to software for the Motorola
	  MPA1000 series FPGA; NeoCAD, following the vendor independant route
	  and the August Design System from Pilkington Micro-electronics Ltd.

As the developers of the Motorola FPGA architecture, Pilkington are in the
unique position of being able to offer tools which were used in (and developed
along-side) the FPGA architecture development. 

The August Design System was used as a benchmark of performance which NeoCAD
needed to match for the MPA1000 series. NeoCAD only achieved this goal be
producing similar performance to August for a single member of the family, the
8000 gate MPA1036.

The August Design System has always been the only software solution which fully
supports all members of the Motorola MPA1000 series of FPGAs.

The August Design System is fully endorsed by Motorola for use with the MPA1000
series and is available as FREEWARE from our web site, URL -

	http://www.pmel.com/

	email	info@pmel.com

The August Design System includes full on-line documentation in the form of
Windows help files which cover August; the FPGA architecture, the libraries
and various design style and troubleshooting issues.



Darren Wedgwood
Pilkington Micro-electronics Limited





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