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Messages from 2450

Article: 2450
Subject: FBI Raids "Avant!" ("ArcSys") For Alleged Cadence Source Code Theft
From: jcooley@world.std.com (John Cooley)
Date: Wed, 6 Dec 1995 19:04:55 GMT
Links: << >>  << T >>  << A >>
My friends in Silicon Valley have just reported that their local
newspaper reports that the FBI in conjunction with the San Jose police
department just raided "Avant!" (formerly "ArcSys") for allegedly 
stealing Cadence source code via ex-Cadence employee named "Mitsuru Igusa."

The article outlines that Igusa, as a Cadence employee, allegedly e-mailed
Cadence proprietary source code to his home e-mail account and then worked
for "Avant!" as a consultant offering them the source code.

Avant!'s CEO, Gerry Hsu, is an ex-Cadence employee who left to join ArcSys
(which changed names to "Avant!" when ArcSys merged with ISS) and has had 
an openly antagonistic relationship with its business rival Cadence.  (The 
most public display of this rivalary was when Gerry Hsu and Joe Costello
openly sparred with each other at last year's DAC Executive Panel on various
issues from market leadership to "wasting time in endless meetings.")

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2451
Subject: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
From: jgriffit@nyx10.cs.du.edu (Jonathan Griffitts)
Date: 6 Dec 1995 13:15:23 -0700
Links: << >>  << T >>  << A >>
Charles.Y.Hitchcock@dartmouth.edu (Charles Y. Hitchcock) writes:


>                                                       Also, has
>anyone have good/bad experiences using Xilinx-ABEL for entire chip
>designs?

>Charlie

I've used X-ABEL for parts of several 4000 family chip designs.
Unless something has improved recently, it CANNOT be used for entire
chip designs for the FPGA families (2000, 3000, 4000) at least --
there are no facilities for specifying pinouts and IOBs.

I found that X-ABEL worked pretty well for control logic but not very
well for datapath.  So I wound up building data paths and pinouts
using XBLOX and control state machines in ABEL, integrating the lot in
a top-level schematic drawing.  It was somewhat clumsy, but it worked. 

Over this past year, I've abandoned the schematic and ABEL based
approach, and am now using Verilog to specify entire chips (all 4000
family, so far), using Exemplar synthesis software.  It works fairly
well except that Exemplar is also weak for datapath synthesis (this
has improved with the latest "Galileo" release).  However Exemplar
does allow me to plug in external XNF file macros, so when I need to
optimize I've been plugging in XBLOX components that way and getting
pretty good results.  Still clumsy, but not as bad as the schematics.

With the Verilog approach I've been getting approx. 40 MHz operation
using XC4000-3 speed grade and 85% or greater utilization of function
generators.  That's a little better density than I got using the older
approach but the comparison may not be fair because of other factors. 
-- 
			   --JCG
AnyWare Engineering, Boulder CO
303 442-0556  (voice or FAX)


Article: 2452
Subject: Re: REPOST: Design Contest Write-up ( was "Jury Verdict + Test Benches" )
From: cburton@chch.planet.org.nz (Chris Burton)
Date: 7 Dec 1995 06:11:37 GMT
Links: << >>  << T >>  << A >>
In article <1995Sep25.090210@btmp09.be>,
   jdla@btmp09.be (jos de laender sh144 7461) wrote:
>In article <43ugb7$amg@euas20.eua.ericsson.se>, ekatjr@eua.ericsson.se
>(Robert Tjarnstrom) writes:
>|> In article <43fgn7$45f@news.Belgium.EU.net>, Jan Decaluwe <jand>
>writes:
>|> >jcooley@world.std.com (John Cooley) wrote:
>|> >
>|> >
>|> >>I personally tend to see hardware when I design hardware, 
>|> >
>|> >This argument is widely used against design methodologies that rely
>|> >on higher levels of abstration. I believe it is misleading. It is
>the .......
>|> 
>|> ..... I would say that it is necessary to see hardware architecture when
>you design. 
>|> Otherwise, you are incapable of making acceptable design solutions.
>Performance and
>|> product properties are determined by choise of algorithm,
>architecture (at many 
>|> levels) and technology. Power dissipation/consumption is a physical
>activity, and 
>|> in order to fulfil power requirements I would say it is necessary to
>see HW while 
>|> designing.
>|> 
>|> Prediction on power dissipation must be made for all architectural
>decisions and in 
>|> order to make such prediction you must see hardware. If not you may
>end up with drastic
>|> violation on important properties. (A cellular telephone with a talk
>time of 5 min
>|> would probably be hopless to sell even for Microsoft :-).
>|> 
>|> Robert Tjarnstrom
>|> 
>|> 
>|> 
>
Hi Robert,

I agree with you. In the perfect world you could decouple hardware from 
software. You could say that repetitive cycles on buses won't cause periodic 
interference signals that will create birdie like signal on the received 
carrier...that performing programming synth chips before phase locked loops 
have stabilised is O.K. That the battery has infinite life and that the unit 
can cost an infinite amount of money, doesn't have to meet hard deadlines, or 
respond to lots of asynchronous events that can interact in substantially 
different ways dependant upon the hardware topology. That DSP really isn't 
that difficult, and the listeners perceived audio quality is never going to be 
degraded by inappropriate scaling or anti-aliase filtering. You never have to 
sit back and think hey...this job could be done with a single external gate, 
and it saves so much hassle, or maybe I should add some analogue ALC and do a 
mixed analogue digital ALC. 

You could imagine the world as a linear system...weather forecast always 
predicting the weather, electrons always flowing in the same direction...sex 
always occurring on demand. 

Unfortunately we awake from inexperienced designer heaven and find the 
monsterous hell of reality awaits. 

If it's not in the requirements it's the requirements that are at 
fault...right?

Look behind every statement about high level abstract design and you find a 
designer thoroughly useless when the shite hits the fan...and the requirements 
don't cut it or they change...(Whoops no more room on the ASIC...should have 
written it in the requirements). If I could smack Slayer or  Mello'n' every 
time some useless dickwad OOA (requirements) designer suggested it wasn't his 
problem because the requirements were wrong they'd be little blood puddles on 
the sidewalk of forgotten street. Just because you know a technique that 
doesn't mean your a good system designer.

Good designers see more than the thing they immediately work with. They can 
spot the problems in the product long before they become entrenched reality. 
They do middle out design (even though it might not immediately be apparent), 
save mega bucks, lots of unrequired design effort and get plenty of patents 
for their company for useful things. They're the dude you want on your side 
when the soldering iron and little clips come out. They're the ones that you 
want on your side when the boss wonders why the products late.

Tools and technique don't replace experience...this is what it's really about.


Article: 2453
Subject: VHDL Editor for Windows PC, Suggestions?
From: you@ewd.dreo.dnd.ca (Larry Ryan)
Date: 7 Dec 1995 15:50:20 GMT
Links: << >>  << T >>  << A >>
Hi:
	I am just beginning to enter the VHDL synthesis field. I would 
like to get a couple of suggestions for a VHDL editor for use on a Windows 
PC. I will be writing code for FPGAs at this point but may expand to ASICs 
in the future. No synthesis tool has yet been chosen but it most likely 
won't be vendor specific. The simulation tool will be Model Technology's 
V-System/VHDL for Windows.

	Please email suggestions. I would also like the location of the 
FAQ.


Regards

Larry Ryan

Practice Random Acts of Kindness and Senseless Acts of Beauty



Article: 2454
Subject: Synario and 22V10 problems
From: cmasgras@magnus.acs.ohio-state.edu (Cristian P. Masgras)
Date: Thu, 7 Dec 1995 17:54:49 GMT
Links: << >>  << T >>  << A >>
I'm using Synario schematic capture to do a design for a GAL22V10 an dI am 
using tri-state buffers on the output.  Synario is assigning an output pin for 
the FF output and one for the tri-state buffer output ( I am trying to control 
the output enable OE fr each FF from one input pin).  Is this a problem with 
Scynario ??
any suggestions ??
thanks in advance
cpm


Article: 2455
Subject: Re: Median filter
From: Tim Sheen <eng407@aberdeen.ac.uk>
Date: Thu, 07 Dec 1995 11:27:43 -0800
Links: << >>  << T >>  << A >>
Knut Tvete wrote:
> 
> Hey,
> 
> I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a
> maximum processing rate of 10 Mhz.  Is there any comercially available
> component for this task or any proposed solutions for implementation in
> an FPGA (Xilinx)?
> 
> Knut Tvete
> 
> Senior Scientist
> Norwegian Defence Research Establishment
> 
> email: knut.tvete@ffi.no

   I have designed a median filter for the XC3195
and implimented a simple version of it,
5x5 taking about 40% of the FPGA resource,
and operating at about 100x the speed of a software solution.
all the sorting was done on the FPGA, but
data was fed to it by a transputer.


              Tim..


Article: 2456
Subject: Re: (no subject)
From: Mark Byers <mark.s.byers@aero.org>
Date: 7 Dec 1995 22:52:17 GMT
Links: << >>  << T >>  << A >>
I do not appreciate your advertising in this forum. I assume that you know better, and it 
tempts me to relate my (somewhat dated) opinion of CUPL -- which would NOT generate sales.

Mark Byers



Article: 2457
Subject: subscribe
From: gburnore@databasix.com
Date: Fri, 8 Dec 1995 00:56:54 GMT
Links: << >>  << T >>  << A >>
subscribe comp-arch-fpga@super.org gburnore@databasix.com
 


Article: 2458
Subject: subscribe
From: gburnore@netcom.com
Date: Fri, 8 Dec 1995 01:53:48 GMT
Links: << >>  << T >>  << A >>
subscribe comp-arch-fpga@super.org gburnore@netcom.com
 


Article: 2459
Subject: Re: Xilinx 5200 vs. 3000, & Xilinx-ABEL?
From: biggs@qcktrn.com ( Tom Biggs )
Date: 8 Dec 1995 02:47:53 GMT
Links: << >>  << T >>  << A >>

In article jfv@bbcnews.rd.bbc.co.uk, rtr@rd.bbc.co.uk (Richard Russell) writes:
> George Noten (garyk@svpal.svpal.org) wrote:
> 
> : The biggest problem of XABEL is that you cannot use it as a standalone
> : design - there is no way to describe IO blocks and internal tristate
> : buffers in XABEL.  You will have to pull them out of your .abl file
> : and use some kind of schematic entry.
> 
> This isn't true: Xilinx document #15778 describes how to do it.  I'd quote
> from it here, but Xilinx specifically prohibits the document's "dissemination
> or distribution" !  I suggest you ask them for a copy.
> 
> Richard.

Actually Xabel 5.2 (which was just released) lets you do IO blocks for an FPGA.
We just got this release, so I haven't tried it yet.

   -tom















Article: 2460
Subject: Help on boards using FPGA devices for hareware realisation
From: Gary Miller <garym>
Date: 8 Dec 1995 04:16:57 GMT
Links: << >>  << T >>  << A >>
I am a member of the VLSI and Systems Technology Laboratory at the University
of New South Wales, working on the research and development of hardware and 
software  Co-design, and in particular on the prototyping of the Co-design 
systems.

We are looking for a reconfigurable co-processor board incorporating FPGA
devices, which would enable us to realise the hardware part of our designs and 
then to run the software code, on the host computer system, in conjunction 
with the board.

If any one could suggest a board, preferably using Xilinx devices and that has
decent software support, that would be worth looking into.

At the moment I'm investigating Giga Operations' Spectrum boards, has anyone
had any experience with then, that could give me feedback.

Gary Miller
VaST Lab
University of New South Wales, Australia



Article: 2461
Subject: Where is the FAQ?
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Fri, 08 Dec 95 15:21:05 GMT
Links: << >>  << T >>  << A >>
 

Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2462
Subject: Re: Synario and 22V10 problems
From: Tom Bowns <bowns@data-io.com>
Date: Fri, 8 Dec 1995 16:39:51 GMT
Links: << >>  << T >>  << A >>
Cristian -

If you would zip up your design and send it to dsa@data-io.com, they'll 
take care of it.

I've already spoken with them about it, and I'm sure we can find a 
solution.

-Tom Bowns
Synario Systems Integration Engineering
Data I/O Corp.




Article: 2463
Subject: FPGA Synthesis/Simulation
From: Scott Kroeger <Scott.Kroeger@mei.com>
Date: Fri, 08 Dec 1995 12:29:47 -0600
Links: << >>  << T >>  << A >>
I've been doing Xilinx design via schematic (DesignWorks) for some 
time. Now I'm looking into HDL synthesis/simulation and other logic 
architectures (Actel, Altera, gate array) for the future.  
Intergraph's VeriBest toolchain has been recommended by some.

I've followed the topical literature on Verilog vs. VHDL and read 
books on both.  I'm leaning towards Verilog for ease of use, but 
would appreciate opinions from people who have produced designs 
using either HDL.

Has anybody had luck using a single front end for more than one FPGA 
vendor?

Has anybody had experience with VeriBest?

Any recommendations for other tools in the mid-to-low price market?

E-mail responses direct unless you think others will benefit from 
your comments.  (I don't want to burden the group with the banter 
that often results from soliciting opinion).

Sorry if this was the wrong place to ask or if my question is too 
broad.

Thanks in advance,

Scott Kroeger
Marquette Electronics
(scott.kroeger@mei.com)


Article: 2464
Subject: Re: Median filter
From: a182629@ibasee3.dseg.ti.com (Ralph Watson)
Date: 8 Dec 1995 18:36:43 GMT
Links: << >>  << T >>  << A >>
Knut Tvete (ktv@ffi.no) wrote:
: Hey,

: I am looking for a 5x5 (or 3x3) median filter with 8 bits input and a
: maximum processing rate of 10 Mhz.  Is there any comercially available
: component for this task or any proposed solutions for implementation in
: an FPGA (Xilinx)?


: Knut Tvete

: Senior Scientist
: Norwegian Defence Research Establishment

: email: knut.tvete@ffi.no




Harris Semiconductor has a commercial device that I am currently using which is a 3x3 Convolver 
all it requires is a processor interface to write coefficients to it 

The Part no. is HSP48908. You might find it more convienient to do this than create your own 
special part. O  f course it all depends on how many bits you want to convolve. 



- Ralph Watson   
  Email: rwwatson@ti.com 
  Systems Group: Texas Instruments 


Article: 2465
Subject: Re: FPGA Synthesis/Simulation
From: ejessen@ix.netcom.com (Erik Jessen)
Date: Fri, 08 Dec 95 21:58:08 GMT
Links: << >>  << T >>  << A >>
I've designed in both; I like VHDL; it's a bit more structured, and has some
things I like.  Verilog is less typing.  For an FPGA-size design, it will be
mainly a matter of taste, and which tools are available for which language.
I'd go for the best tools: you'll spend a lot more time debugging wrong tools, 
than you will spend time coding in the "wrong" language.  Typing is a pretty 
small part of the overall process.

>
>Has anybody had luck using a single front end for more than one FPGA 
>vendor?

We were pretty happy with Exemplar synthesizing VHDL into Xilinx and Altera.

>Has anybody had experience with VeriBest?
Never used.

>Any recommendations for other tools in the mid-to-low price market?

Modeltech is a great PC-based simulator for VHDL.

>E-mail responses direct unless you think others will benefit from 
>your comments.  (I don't want to burden the group with the banter 
>that often results from soliciting opinion).

Erik Jessen
Com-Solutions, Inc.
(619) 942-9790
The views expressed here are purely my own.


Article: 2466
Subject: Re: Xilinx vs Altera with Verilog/VHDL
From: tgoodloe@adtran.com (Tony Goodloe)
Date: 8 Dec 1995 22:27:51 GMT
Links: << >>  << T >>  << A >>
In article <4a4hot$bv2@mozz.unh.edu>, pss1@hopper.unh.edu (Paul S Secinaro) says:

>The XC5000 is supposed to have some sort of new routing structure in
>the I/O ring to reduce pinout problems.  Don't know much about it,
>though.
>

The VersaRing (don't we all love marketing) allows any of the I/Os 
to routed around the periphary of the chip to get to the logic it 
needs to.

tony


Article: 2467
Subject: Re: CRC-32 implementation
From: schimmel@gandalf.ca (Fred Schimmel)
Date: 8 Dec 1995 17:39:52 -0500
Links: << >>  << T >>  << A >>

>In article <49d6mo$ju2@bmerhc5e.bnr.ca>,
>   crm182c@bmers2da.bnr.ca (Hing-Fai Lee) wrote:
>>In article <ssikdar.21.00006806@best.com>, Som Sikdar <ssikdar@best.com> 
>wrote:
>>>
>>>Is there any VHDL/Verilog source available in the public domain for 
>byte-wise 

>>
>>Parallel CRC computation was a favorite topic in Computer Design from the
>>late 60s to early 70s. Check it out in your local library. Good Luck.
>>Hing-Fai



>Please check an excellent aricle about generalized solutions to Parallel CRC 
>computing in : IEEE Micro of Octobel 1990 : "Parallel CRC Generation" by Guido 
>Albertengo & Riccardo Sisto, pages 63-71. Some understanding of Z transforms 
>is required. But, it gives you a generic solution

>Alex Koegel
>DSPC Israel

Some other references include:

"Handbook of Computer Communications Standards", Local Network Standards,
Volume 2  by William Stallings

and

"C Programmers Guide to NetBIOS"

The second book contains C code for computing CRCs of various kinds, including
CRC-32. Using this code, you can derive the exclusive-or tree needed for the 
diagram below:

                     ---------
                     |       |      ---------
  Input Byte   =====>|  XOR  |      |       |
  (parallel)         |       |=====>|  CRC  |
                     |  tree |      |       |======>  CRC-32 out
               =====>|       |      |  reg  |   |     (parallel)
               |     |       |      |       |   |
               |     ---------      ---------   |
               |                                |
               ==================================

Of course, you need to also provide controls for initalizing the register to
All-1s (pre-conditioning), complenting result and append to frame (transmit
post-conditioning, and compare for good frame residue (receive post-condition).

The proper "magic number" for the residue is 0xDEBB20E3.

The depth of the exclusive-or tree is about 8 (If I remember). This may limit
the maximum clock rate you can achieve per byte to the CRC accumulator.
Good Luck!
-- 
Fred Schimmel     (609)461-8100  ext. 5060  |    email: schimmel@gandalf.ca
Gandalf Systems Corporation                 |------------------------------- 
501 Delran Parkway                          |      Objects in mirror are
Delran  NJ  08075    USA                    |     closer than they appear!


Article: 2468
Subject: Re: CRC-32 implementation
From: Ray Andraka <randraka@ids.net>
Date: 9 Dec 1995 01:30:31 GMT
Links: << >>  << T >>  << A >>
> The depth of the exclusive-or tree is about 8 (If I remember). This may limit
> the maximum clock rate you can achieve per byte to the CRC accumulator.

I missed the first part of this thread, so I do not know if you are 
intending to use an FPGA to realize your parallel CRC32.  If you are,
you may find that a bit or digit serial solution attains better 
performance with less logic. This is due to the prop delays associated
with the routing and logic cells.  The serial solution to CRC is 
extremely compact and should run darn close to the maximum toggle freq
of the FPGA.  Of course all this presupposes the ability to get ahold
of a suitable multiple of your data clock! Look for my presentation at
Design Supercon '96 on building high performance bit serial processors
in FPGAs.

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
email randraka@ids.net
 
The Andraka Consulting Group is a digital hardware design firm specializing 
in high performance FPGA designs.  Services include complete design, development, 
simulation, and integration of these devices and the surrounding circuits.  We 
also evaluate,troubleshoot, and improve existing designs. Please call or write 
for a free brochure.



Article: 2469
Subject: Lattice ISP download cable?
From: 100416.151@compuserve.com (Brian Drummond)
Date: Mon, 11 Dec 1995 13:15:27 GMT
Links: << >>  << T >>  << A >>
Hello,

Can anyone supply me with the circuit diagram, or the list of
connections for the PC printer port download cable, supplied with the
Lattice ISP starter kit?

Please e-mail because my newsfeed is a bit unreliable.

TIA - Brian Drummond.




Article: 2470
Subject: Re: Help on boards using FPGA devices for hareware realisation
From: Mark Cartlidge <mic@sundance.com>
Date: Mon, 11 Dec 95 14:04:14 PDT
Links: << >>  << T >>  << A >>

In article <4a8e7p$hm2@mirv.unsw.edu.au>, <garym@smta.demon.co.uk> writes:

> I am a member of the VLSI and Systems Technology Laboratory at the 
University
> of New South Wales, working on the research and development of hardware and 
> software  Co-design, and in particular on the prototyping of the Co-design 
> systems.
> 
> We are looking for a reconfigurable co-processor board incorporating FPGA
> devices, which would enable us to realise the hardware part of our designs 
and 
> then to run the software code, on the host computer system, in conjunction 
> with the board.
> 
> If any one could suggest a board, preferably using Xilinx devices and that 
has
> decent software support, that would be worth looking into.
> 
> At the moment I'm investigating Giga Operations' Spectrum boards, has anyone
> had any experience with then, that could give me feedback.
> 
> Gary Miller
> VaST Lab
> University of New South Wales, Australia
> 
> 

Take a look at our SMT219 product on our web pages.

If you have questions let me know.

Mark Cartlidge

          Sundance Multiprocessor Technology Ltd.
4 Market Square, Amersham, Bucks, HP7 0DQ, United Kingdom
      
OFFICE:    Tel: +44-1444-881898     Fax: +44-1444-881786
HQ:        Tel: +44-1494-431203     Fax: +44-1494-793168
mic@smta.demon.co.uk : sales@sundance.com : mic@sundance.com
          www: http://www.sundance.com/



Article: 2471
Subject: CRC-32 implementation
From: schimmel@gandalf.ca (Fred Schimmel)
Date: 11 Dec 1995 16:11:31 -0500
Links: << >>  << T >>  << A >>
alexk@dspis.co.il (Alex Koegel) writes:

>In article <49d6mo$ju2@bmerhc5e.bnr.ca>,
>   crm182c@bmers2da.bnr.ca (Hing-Fai Lee) wrote:
>>In article <ssikdar.21.00006806@best.com>, Som Sikdar <ssikdar@best.com> 
>wrote:
>>>
>>>Is there any VHDL/Verilog source available in the public domain for 
>byte-wise 

>>
>>Parallel CRC computation was a favorite topic in Computer Design from the
>>late 60s to early 70s. Check it out in your local library. Good Luck.
>>Hing-Fai



>Please check an excellent aricle about generalized solutions to Parallel CRC 
>computing in : IEEE Micro of Octobel 1990 : "Parallel CRC Generation" by Guido 
>Albertengo & Riccardo Sisto, pages 63-71. Some understanding of Z transforms 
>is required. But, it gives you a generic solution

>Alex Koegel
>DSPC Israel

Some other references include:

"Handbook of Computer Communications Standards", Local Network Standards,
Volume 2  by William Stallings

and

"C Programmers Guide to NetBIOS"

The second book contains C code for computing CRCs of various kinds, including
CRC-32. Using this code, you can derive the exclusive-or tree needed for the 
diagram below:

                     ---------
                     |       |      ---------
  Input Byte   =====>|  XOR  |      |       |
  (parallel)         |       |=====>|  CRC  |
                     |  tree |      |       |======>  CRC-32 out
               =====>|       |      |  reg  |   |     (parallel)
               |     |       |      |       |   |
               |     ---------      ---------   |
               |                                |
               ==================================

Of course, you need to also provide controls for initalizing the register to
All-1s (pre-conditioning), complenting result and append to frame (transmit
post-conditioning, and compare for good frame residue (receive post-condition).

The proper "magic number" for the residue is 0xDEBB20E3.

The depth of the exclusive-or tree is about 8 (If I remember). This may limit
the maximum clock rate you can achieve per byte to the CRC accumulator.
Good Luck!
-- 
Fred Schimmel     (609)461-8100  ext. 5060  |    email: schimmel@gandalf.ca
Gandalf Systems Corporation                 |------------------------------- 
501 Delran Parkway                          |      Objects in mirror are
Delran  NJ  08075    USA                    |     closer than they appear!


Article: 2472
Subject: PALASM under OS/2???
From: david@opq.se@
Date: 12 Dec 1995 07:36:26 GMT
Links: << >>  << T >>  << A >>
Hi!

Is anyone running PALASM under OS/2?
If so what settings are you using?
I have some problems in getting PALASM to run properly under the OS/2 platform.

Please mail me your idea's, I have seldom time to look in these newsgroups!

Regards

David Olsson


Article: 2473
Subject: **** YIKES! Need Help On Synopsys Report Card! ****
From: jcooley@world.std.com (John Cooley)
Date: Tue, 12 Dec 1995 08:58:12 GMT
Links: << >>  << T >>  << A >>
      !!!     "It's not a BUG,                         jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                               (508) 429-4357
    (  >  )
     \ - /         "YIKES!  Need Help On Synopsys Report Card"
     _] [_ 

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222


HELP!  As the president of the Users Society for Electronic Design Automation 
(USE/DA) I foolishly signed up to do a detailed report card on Mentor Graphics
a while ago. I'm the same guy who did the same survey on Cadence for their
user's group meeting.  I got some interesting results but don't want to
release them until this Synopsys survey is done so they don't influence each 
other.  What I need from you, as a Synopsys user, is to tell me exactly how 
you feel about various aspects of doing business with Synopsys.  To keep 
things fair I'm going to only take responses customers send that come to me 
within three days of my publishing this questionaire -- just like what I did 
for the Cadence & Mentor surveys.  ALL CUSTOMER INPUT WILL BE USED ANONYMOUSLY.
(That is, I'll report *what* customers think but not exactly *who* said it.)

My goal is to provide a balanced report card that contains not only where 
Synopsys has messed up, but also where they're doing a good job.  I'm an ASIC 
designer so I'd like to ask that you be as specific as possible in what you 
say.  If you love/hate specific things Synopsys does/offers, I want to hear 
the specifics.  Feel free to respond on anything, but to get you in an 
evaluation frame of mind, I'll ask:

Please Report Your Primary Interest In Synopsys Tools (ASIC design, ECL,
Low Power IC design, RTL simulation, FPGA, etc):_________

  1.)  What tools do you specifically use (by name)?:

  2.)  What does your company make/sell?

  3.)  Where are you? (City, State, Country)?


 -----------------------------------------------------------------------------

  1.) What do you think of Synopsys's on-line & hard copy documentation?  Is
      it usually very helpful & complete, out-to-lunch, or what? 

  2.) What do you think of Synopsys's hotline?  What's the typical turnaround 
      you get for your questions?  Do you feel that you get access to 
      knowlegable experts or new college graduates most of the time?  What do 
      you think of their "We'll call you back" way of running the hotline?  
      How many times have you had to use it in a typical month?

  3.) What do you think of Synopsys's local support in your area?  Are they 
      around after your company bought the tool?  Are they helpful?

  4.) What do you think of Synopsys's electronic connectivity?  How about their
      WWW page?  "ESNUG" ?

  5.) What do you think about Synopsys Consulting Services?  Has your company 
      lost employees to this?  Have they solved your problems?  Do you like
      Synopsys offering such services that might mean doing design for your 
      company?

  6.) What do you think about Synopsys training?  Have you used their classes?
      Were they very helpful, a complete waste of time or somewhere in 
      between?  Please be specific.

  7.) How do you feel about the Synopsys sales force?  Do they talk to you or 
      are they only interested in your VP of Engineering?  Do they help you 
      through business problems year round or only when there a potential 
      sale in the works?  Going from GREAT to HORRIBLE please rank them 
      equal to (choose one)

      - "Ghandi has serious competition compared to my Synopsys saleman!" (or)
      - "I want to base my whole life philosophy around you." friends (or)
      - "Please!, Marry my daughter!" good friends (or)
      - Helpful friends (or)
      - Helpful business acqaintances (or)
      - Helpful Deparment store cashiers (or)
      - Indifferent Department store cashiers (or)
      - New Car salesmen (or)
      - Door-to-Door vacuum cleaner salesmen (or)
      - Used Car salesmen (or)
      - Con artists just a few steps ahead of the law (or)
      - Congressmen and/or convicted con-artists 

  8.) What's the most POSTIVE Synopsys related experience you've had?  If you 
  were made "Aart-De-Geus-for-a-day," what would you NOT change about Synopsys?

  9.) What's the most NEGATIVE Synopsys related experience you've had?  If you
  were made "Aart-De-Geus-for-a-day," what would you change about Synopsys?

 10.) What specifically do you techinally like about their tools?  What's their
      best tool?  What's their worst tool?  Why?  (Give details.)

 11.) Do Synopsys's point tools play nice with other Synopsys point tools?  Do
      Synopsys point tools play nice with non-Synopsys tools? (Give specifics.)

 12.) Overall, how you rank Synopsys compared to other EDA companies you've 
      dealt with?  Far better, far worst, about average?

Again, my asking these questions is to get you to tell me what you think 
about Synopsys as a whole and concerning specific products & services they
offer.  No names nor sources will be used in reporting the general user 
views of Synopsys.  Thank you for your time!  :^)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3713 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2474
Subject: Re: Synario and 22V10 problems
From: cmasgras@magnus.acs.ohio-state.edu (Cristian P. Masgras)
Date: Tue, 12 Dec 1995 12:37:42 GMT
Links: << >>  << T >>  << A >>
>If your software is doing that, you are probably using more than one product
>term for the OE. If you look at the block diagram for the 22V10, you'll notice
>that the OE wiring, only accepts a single product term. Try simplifying the
>equation for the OE. Take advantage of dummy terms, if you can find any.
>Frank

thanks for your suggestion ... it was a very simple solution, I did not have 
to change my design !
I called the people at Data I/O and they were very prompt 
in their response.  It was a simple 2 file patch that fixed the problem.  They 
emailed the 2 files and I got it fixed the same day.

thanks
cpm




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