Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 2500

Article: 2500
Subject: Re: Floor Planning for Xilinx
From: Phil Sailer <sailer@lss1038>
Date: Tue, 19 Dec 1995 17:27:09 -0500
Links: << >>  << T >>  << A >>
On Mon, 18 Dec 1995, Maya Reuveni wrote:

> My question is about floor planning for Xilinx X4013.
> I am working on a large design to be mapped into a
> Xilinx XC4013 device. The design consists of 4 main
> blocks; utilization is 55%; and target speed is 33 Mhz!
> 
> Does anyone have any tips for the grafical floor planner?
> 
> ANY responce  will be appreciated.

i don't have direct experience with the xilinx floorplanner yet (i'll be
targeting an xc4013e in the near future), but what i've heard from the
engineers here who have used the xilinx graphical floorplanner, is that it
is really only useful for highly structured designs (i.e., those in which
the functionality is broken up into smaller, logical chunks, which are
assembled into a hierarchy, and have nice names attached to them, etc. --
you know what i'm talking about). 

so, if your design is not already well structured, maybe you should
consider doing that first, before getting into floorplanning, if time
permits.  otherwise, the floorplanner will not buy you much at all. 

phil

._._._._._._._._._._._._._._._._._._._._._._._._._._._._._._.
  Phil Sailer  --  EMC Corporation  --  508.435.1000, x4477


Article: 2501
Subject: Bit Stream Parser
From: swood@melpar.esys.com (S.G. Wood, Jr.)
Date: Wed, 20 Dec 95 03:49:59 GMT
Links: << >>  << T >>  << A >>
I have an ORCA FPGA (2C15) that is configured in the asynchronous peripheral 
mode.  I'm interested in different methods for getting the *.bit 
information to the peripheral FPGA.  One method is to parse the *.bit file 
into an array, and then use the stored array data as input to the FPGA.  If 
anyone has already succeeded in doing this I would be interested in the 
program/code.  

-Simon


Article: 2502
Subject: Re: UART in PLD
From: ecp@focus-systems.on.ca (Eric Pearson)
Date: Wed, 20 Dec 1995 16:50:32 GMT
Links: << >>  << T >>  << A >>
In article <chuck.1169690217A@news.connectnet.com>,
Charles P. Ohrbom <chuck@aeroastro.com> wrote:
>I need to implement a UA(R)T, i.e. the transmitt portion only, in an Actel
>PLD.  I will use a pin on a MC68332 as the UAR(T) receiver.  Does anyone
>have a design they could pass along?
>
>Chuck Ohrbom
>AeroAstro
>chuck@aeroastro.com

The 1991 version of the Actel handbook had a design for a UART in the
application notes. I seem to remeber the transmitter as being the
simpler of the two sections (just shift the data out with start/stop
bits added at the correct rate).

Eric
http://www.sentex.net/~eric

-- 
Eric Pearson -- Focus Systems -- Waterloo, Ontario
     ecp@focus-systems.on.ca  (519) 746-4918
    "We Engineer Innovative Imaging Solutions"


Article: 2503
Subject: VLSI DESIGN AND TEST Short Course at Georgia Tech
From: Greg Stenzoski <greg.stenzoski@conted.gatech.edu>
Date: 20 Dec 1995 19:47:30 GMT
Links: << >>  << T >>  << A >>

PRESS RELEASE

                                                    For Immediate Release
                                                    December 12, 1995


                        UPCOMING SHORT COURSE
                        ^^^^^^^^^^^^^^^^^^^^^

                         VLSI DESIGN AND TEST
                   Georgia Institute of Technology 

                          March 18-22, 1996

The Georgia Institute of Technology (Atlanta, GA) is offering a continuing
education short course in the area of very large-scale integrated (VLSI)
circuit design.  The lectures focus on the custom and semicustom design,
verification, testing, and packaging of digital and mixed-signal integrated
circuits.  A design-intensive laboratory experience provides participants
with hands-on experience designing and verifying a complete mixed-signal
VLSI chip. 

For more information:

  World-Wide Web:  http://www.ee.gatech.edu/academic/conted/VLSI/

  Registration or brochure: conted@gatech.edu OR 404-894-2547
                            AND ALSO http://www.conted.gatech.edu

  Course content/requirements: steve.deweerth@ece.gatech.edu


Article: 2504
Subject: Altera related Qs.
From: jan.maris@ping.be (Jan Maris)
Date: Wed, 20 Dec 1995 20:07:49 GMT
Links: << >>  << T >>  << A >>
I have several questions related to the use of Altera components.

1) clock enable
In a previous thread, the use of clock "gating" in Xilinx XC40xx LCA
was under discussion, pointing out towards the use of the dedicated
Clock Enable terminal of a CLB/IOB, which is of course very useful and
easy to use. 
My question is now related to the same for Altera-EPLD EPM7000 family.
In the data sheet it is clearly shown that the basic register
structure has a clock enable signal. Which input of which symbol of
which library must be considered to use this clock enabling? I have a
synchronous work around, but that needs more resources.

2) Has anyone used the XNF interface writer of the MAX2Plus tool
chain. What about AHDL. Common libraries and target independent
inputs?

TIA.

Regards,
Jan.    
--
__________________________

Jan Maris
Zaventem, Belgium.
jan.maris@ping.be


Article: 2505
Subject: Career value: VHDL or Verilog?
From: eric@wolf359.exile.org (Eric Edwards)
Date: Thu, 21 Dec 1995 06:44:53 GMT
Links: << >>  << T >>  << A >>
I am fishing for trends here...

In an effort to kick start my engineering career into existance, I intend
to learn one of these HDLs soon.  The question is, which one?  Industry
seems not to hire generalists so it seems best to put the energy into one
rather that divide among both.  Which HDL would provide the greatest benefit
for someone trying to break into logic design?

----
Eric Edwards is, and will always be: eric@exile.org
Remember the home hobbyist computer: Born 1975, died April 29, 1994



Article: 2506
Subject: Re: Looking for OpenABEL
From: h-miya@lsi.tmg.nec.co.jp (Hiroshi Miyauchi)
Date: 21 Dec 1995 09:18:41 GMT
Links: << >>  << T >>  << A >>
Hi, 

Years ago, I've ever got one, about 100 pages document, from 
their local distributor:

  OPEN-ABEL Technical Specification
  P/N:971-1134-001

I think sign up on the "OPEN-ABEL Registration Card" is required.
How about contacting to your local distributor, or DATA-I/O product
marketing division directly?


I hope this helps.


In article <JPA.95Dec14111640@hobbes.inesc.pt>
  jpa@hobbes.inesc.pt (Jose'Pedro Abreu) writes:

> I am looking for some pointers regarding OpenABEL. I have the ABEL
> manuals from DATA-IO but there little referrence to OpenABEL.
>
> I've checked the www site from DATA-IO but I couldn't find anything.

---
H.Miyauchi
--


Article: 2507
Subject: Re: UART in PLD
From: hp@kbbs.org (Holger Petersen)
Date: Thu, 21 Dec 1995 14:01:16 GMT
Links: << >>  << T >>  << A >>
chuck@aeroastro.com (Charles P. Ohrbom) writes:

>Hello,

>I need to implement a UA(R)T, i.e. the transmitt portion only, in an Actel
>PLD.

The german PC-Magacien "C'T" had an article in 1988 #3 Page 155 for both
direction.
The simplest transmit-part uses 2 HCT 165-Chips [shift-registers] and a
clock-generator:

                      D7 D6     D5 D4 D3 D2 D1 D0     Strobe
+5V -*--*--*--*--*--*--*  |  |      |  |  |  |  |  |          |
     |  |  |  |  |  |  |  |  |      |  |  |  |  |  |  M  +5V  |
     |  |  |  |  |  |  |  |  |      |  |  |  |  |  |  |  |    |
     |  |  |  |  |  |  |  |  |      |  |  |  |  |  |  |  |    |
     |  A  B  C  D  E  F  G  H      A  B  C  D  E  F  G  H    |
     |                                                        |
     |                                                        v
     *--Ser IN              Out --- Ser in             Out ------------->
                                                              ^
                                                              |
         Clock   Inh   Load            Clock   Inh  Load      |
           |      |      |               |      |     |       |
           |      M      v               |      M     |       |
Osz.-------*-----------------------------*            |       |
                         ^                            |       |
                         |                            |       |
                         *----------------------------*-------*
                
I hope you can decifer my ASCIi-Painting...

Seasons greetings, Holger


Article: 2508
Subject: Re: UART in PLD
From: kgold@watson.ibm.com (Ken Goldman)
Date: 21 Dec 1995 15:19:00 GMT
Links: << >>  << T >>  << A >>
ecp@focus-systems.on.ca (Eric Pearson) writes:
> Charles P. Ohrbom <chuck@aeroastro.com> wrote:
> >I need to implement a UA(R)T, i.e. the transmitt portion only, in an Actel
> >PLD.  I will use a pin on a MC68332 as the UAR(T) receiver.  Does anyone
> >have a design they could pass along?
> >
> The 1991 version of the Actel handbook had a design for a UART in the
> application notes. I seem to remeber the transmitter as being the
> simpler of the two sections (just shift the data out with start/stop
> bits added at the correct rate).
> 

A bit off subject, since the poster wanted a transmitter:

Yes the transmitter is easier, since the receiver needs a small
state machine to detect the start bit and then start sampling in the
middle of the bit.

But the transmitter needs a bit counter, and there's an old trick
to eliminate the counter for the receiver.  Preset the receive
shift register to ones.  When the first zero (the start bit) gets
shifted out, you're done.

-- 
Ken Goldman   kgold@watson.ibm.com


Article: 2509
Subject: Re: Altera related Qs.
From: "Dave Daurelio" <daurelio@mojo.kodak.com>
Date: Thu, 21 Dec 95 11:15:48 EST
Links: << >>  << T >>  << A >>
In answer to your question about clock enables in Altera devices - Altera
has a number of device primitives in their library which provide a clock
enable. The most common of these is the "DFFE" primitive, which provides a D
input, clock (rising-edge triggered), active-low preset and clear, and an
active-high clock enable. There is also a "TFFE" ("T" flip-flop with enable),
as well as JKFFE types. If you are using the MAX+PLUSII software, you can
consult the on-line help for info on all the available primitives.
One additional comment is in order: The 7000 series parts do indeed have
clock enables as shown on the data sheets. If you use a primitive with clock
enable in your design, and target the design for an Altera device which does
not directly support clock-enables, the MAX+PLUSII compiler will
automatically synthesize the logic necessary to provide the correct behavior.
I can't answer #2, because I have not used the XNF writer before.

Article: 2510
Subject: FPGA'96 Adv. Program
From: cong@rabbit.cs.ucla.edu (Dr. Jason Cong)
Date: 21 Dec 1995 09:15:13 -0800
Links: << >>  << T >>  << A >>
******   Most up-to-date on-line symposium program is available at   *********
****** http://www.cs.washington.edu/research/projects/lis/www/fpga96 *********

			FPGA `96 Advance Program
			------------------------

1996 ACM/SIGDA Fourth International Symposium on Field-Programmable Gate Arrays

			     February 11-13, 1996
		Monterey Beach Hotel, Monterey, California, USA

Sponsored by ACM SIGDA, and Xilinx, Inc., Altera Corp. and Actel Corp.

Over the past ten years FPGAs have revolutionized the way many systems are 
designed by providing a low-cost, fast-turnaround implementation alternative. 
This is an exciting time in an exciting field that is still expanding as new 
technologies appear, new architectures are proposed, and new CAD tools are 
developed to address problems specific to FPGAs. This Symposium focuses on the 
architectural and algorithmic issues that FPGA architects and CAD designers 
face today and in the future. This is a forum where researchers from industry 
and university present and debate the latest ideas in FPGA design and 
application.

The technical program consists of papers concerning both the practical 
and theoretical aspects of FPGA architecture, CAD algorithms for using 
and testing FPGAs, and applications. The Symposium will be of interest 
to those developing FPGA architectures, both at the chip and board level, 
and those developing CAD algorithms for FPGAs. The Symposium is not of direct 
interest to immediate users of FPGAs.

General Chair: 	Jonathan Rose, University of Toronto
Program Chair: 	Carl Ebeling, University of Washington
Publicity Chair: 	Jason Cong, UCLA
Local Chair: 	Pak Chan, UC Santa Cruz
Finance Chair: 	Steve Trimberger, Xilinx

 Program Committee
Michael Butts, Quickturn
Pak K. Chan, UCSC
Paul Chow, U. Toronto
Jason Cong, UCLA
Ewald Detjens, Mentor
Carl Ebeling, U. Washington
Gareth Jones, Pilkington
Dwight Hill, Synopsys
Brad Hutchings, BYU
Sinan Kaptanoglu, Actel
Jonathan Rose, U. Toronto
Richard Rudell, Synopsys
Rob Rutenbar, CMU
Takayasu Sakurai, Toshiba
Martine Schlag, UCSC
Tim Southgate, Altera
Steve Trimberger, Xilinx
Nam-Sung Woo, ATT

Program Sunday February 11, 1996

6:00pm	Registration

7:00pm	Welcoming Reception, 
	Monterey Beach Hotel, Monterey

Monday February 12, 1996

7:30am	Continental Breakfast/Registration

8:20am	Opening Remarks

Session 1: Novel FPGA Architectures 

Chair: Jonathan Rose, University of Toronto

8:30am	Hybrid FPGA Architecture, 
	A. Kaviani and S. Brown, University of Toronto

8:50am	Plasma:	 An FPGA for Million Gate Systems, 
	V.R. Amerson, R. Carter, W. Culbertson, 
	P. Kuekes, G. Snider, L. Albertson, HP Labs

9:10am	Flexible FPGA Architecture Realized of General 
	Purpose Sea of Gates, K. Azegami, S. Kashi-
	wakura, K. Yamashita, Fujitsu Laboratories

Posters: Novel FPGA Architectures

9:30-10:30am Coffee & Posters	

Session 2: Logic Module Design

Chair: Richard Rudell, Synopsys

10:30am Using BDDs to Design ULMs for FPGAs, 
	Z. Zilic and Z.G. Vranesic, University of Toronto

10:50am Series-Parallel Functions and FPGA Logic 
	Module Design, 
	S. Thakur, D.F. Wong, University of Texas, Austin

11:10am Combined Spectral Techniques for Boolean 
	Matching, E. Schubert, W. Rosenstiel, University 
	of Tuebingen

Posters: Logic Module Design 11:30-12:00

LUNCH 12:00 - 1:30

Session 3: Performance Issues

Chair: Steve Trimberger, Xilinx

1:30pm  The Wave Pipeline Effect on LUT-Based FPGA 
	Architectures, E.I. Boemo, S. Lopez-Buedo, 
	J.M. Meneses, Universidad Politecnica de Madrid

1:50pm  Timing Optimization for Hierarchical Field-
	Programmable Gate Arrays, 
	V.C. Chan, D.M. Lewis, University of Toronto

2:10pm  Technology Mapping of Sequential Circuits for 
	LUT-Based FPGAs for Performance, 
	P. Pan, C.L. Liu, Clarkson University

Posters: Performance Issues

2:30-3:30pm Coffee & Posters

Session 4: Theoretical Issues in Routing Architectures

Chair: Jason Cong, UCLA

3:30pm  A Method for Generating Random Circuits and 
	Its Application to Routability Measurement, 
	J. Darnauer and W.W-M. Dai, University of 
	California, Santa Cruz

3:50pm  Entropy, Counting, and Programmable 
	Interconnect, A. DeHon, MIT

4:10pm  Universal Switch Modules for FPGA Design, 
	Y-W. Chang, D.F. Wong, C.K. Wong, University of 
	Texas, Austin

Posters: Theoretical Issues in Routing Architectures

4:30-6:00pm Free time/Posters

Dinner 6:00-7:30pm

7:30-9:00pm  PANEL 
	     FPGAs vs. Gate Arrays and Processors: Who Will Win?

The FPGA industry has enjoyed rapid growth in the past ten 
years in terms of chip density and speed as well as ASIC 
market share. In the same period, however, we have also 
observed significant advances in all sectors of the semi-
conductor industry -- state-of-the-art gate arrays have a 
capacity of over 10 million transistors and enable the 
`system-on-a-chip'. Design automation tools have made 
semi-custom designs much faster and easier to achieve while 
yielding both high density and high performance. High-end 
microprocessors have reached over 250 Mhz and can satisfy 
the needs of many real-time control and DSP/multi-media 
applications. New rapid prototyping technologies, such as 
laser-programmed gate arrays, have emerged for high-speed 
high-density prototyping.

Given such a dynamic industry undergoing exponential 
growth, it is interesting to ask where FPGAs will stand five 
or ten years from now in the wide spectrum of design 
technologies. Will its share of the ASIC market continue to 
increase, or will it become more of a niche technology? It is 
likely that the relative importance of these technologies will 
change drastically over the next five to ten years.

This panel comprises technology experts in the competing 
areas of FPGAs, gate arrays, processors and other 
technologies. They will focus on the technological and 
economic issues that give one implementation medium an 
advantage over others and discuss how new technologies and 
architectural developments may change the competitive 
balance. They will discuss the past, present and future of the 
technological forces driving the industry and debate where 
those forces are likely to take us in the future.

Tuesday February 13, 1996

Session 5a: Field-Programmable Analog Arrays

Chair: Paul Chow, University of Toronto

8:30am  Design and Implementation of a Field- 
	Programmable Analogue Array, A. Bratt and 
	I. Macbeth, Pilkington Microelectronics

8:50am  The EPAC Architecture: An Expert Cell
	Approach to Field-Programmable Analog 
	Arrays, H.W. Klein, IMP

Posters: Field-Programmable Analog Arrays

9:10-9:40am Coffee & Posters

Session 5b: Testing

Chair: Martine Schlag, UC Santa Cruz

9:40am  Diagnosing Programmable Interconnect Systems 
	for FPGAs, D. Ashen and F. Lombardi, 
	Texas A&M University

10:10am Evaluation of FPGA Resources for Built-In Self-
	Test of Programmable Logic Blocks, 
	C. Stroud, P. Chen, S. Konala, M. Abramovici, 
	University of Kentucky

Posters: Testing

10:30-11:00am Coffee & Posters

Session 6: The Future of Fuse and SRAM FPGA Technologies

Chair: Tim Southgate, Altera

11:00am Two invited speakers will present the state of the 
	art in (anti-)fuse and SRAM technologies and 
	discuss the impact of recent developments in 
	these technologies on future architectures.

Posters: FPGA Vendors 11:40-12:00 

LUNCH 12:00 - 1:30

Session 7: Applications

Chair: Dwight Hill, Synopsys

1:30pm  DPGA Utilization and Application, 
	A. DeHon, MIT

1:50pm  Integrating Software with Run-Time Re-
	configured Hardware, M.J. Wirthlin and B.L. 
	Hutchings, Brigham Young University

2:10pm  Computing the Discrete Fourier Transform on 
	Virtual Systolic Arrays, 
	C. Dick, La Trobe University

Posters: Applications

2:30-3:30pm Coffee & Posters 

Session 8: Design Systems

Chair: Pak Chan, UC Santa Cruz

3:30pm	RASP: A General Logic Synthesis System for 
	SRAM-based FPGAs, J. Cong, J. Peck, UCLA, and 
	Eugene Ding, AT&T Bell Laboratories.

3:50pm  Emerald - An Architecture-Driven Tool Compiler 
	for FPGAs, D. Cronquist and L. McMurchie, 
	University of Washington

4:10pm  Structured Design Implementation - A Strategy 
	for Implementing Regular Datapaths on FPGAs, 
	A. Koch, Technical University, Braunschweig

Posters: Design Systems 4:30-5:00

5:00pm Symposium Ends.

		Hotel Information
		-----------------

The Symposium will be held at the Monterey Beach Hotel, 
2600 Sand Dunes Dr., Monterey, CA 93940, USA. The 
phone number for room reservations is 1-800-242-8627 or 
+1-408-394-3321 (Fax +1-408-393-1912). Reservations 
must be made before January 6, 1996. Identify yourself 
with the group Association for Computing Machinery 
FPGA `96 Symposium to receive the special Symposium 
rates, which are $75 for single or double Gardenview and 
$105 for single/double Oceanview. Parking is free. Check-
in time 4pm.

Directions to Hotel: From San Jose (a 1.5 hour trip) or 
San Francisco Airport (2.5 hrs) take HWY 101 South to 
HWY 156 West to HWY 1 South. On HWY 1 South, take 
Seaside/Del Rey Oaks exit. The hotel is at this exit, on the 
ocean side.

You can also fly directly to the Monterey Airport, which is 
served by United, American and other airlines with at least 
8 flights per day.

FPGA `96 REGISTRATION 
---------------------

The Symposium registration fee includes a copy of the symposium proceedings, 
a reception on Sunday evening, February 11, coffee breaks, lunch on both days, 
and dinner Monday evening, February 12.


First Name:___________________________________________
Last Name:____________________________________________
Company/Institution___________________________________
Address:______________________________________________

City:___________________State:________________________
Postal Code:_______________Country:____________________

Email:__________________________________________________
Phone:_______________________Fax:_______________________


ACM Member #____________
Circle Fee:   Before January 25, 1996  	After January 25, 1996 

ACM/SIGDA Member  	US $320    		US $390

*Non-Member 		US $420 		US $490

Student 		US $90			US $90 
(does not include reception or banquet, available for $20 and $35 respectively)

*If you are not an ACM/SIGDA member we are giving you the opportunity to 
join by paying your first year's dues out of your conference non-member 
registration fee -- a US$100 value. Forms will be available at on-site 
registration.

Guest Reception Tickets #Tickets______x US $20 ______
Guest Banquet Tickets #Tickets______x US $35 ______

Total Fees:____________________(Make checks payable to ACM/FPGA'96)

Payment Form (Circle One): AMEX   MASTERCARD  VISA   CHECK

Credit Card#:____________________________________
Exp. Date:_______________________________________
Signature:_______________________________________

Send Registration with payment to:

 FPGA `96 - Colleen Matteis, 
 553 Monroe St., 
 Santa Clara, CA. 95050, 
 USA. 

 Phone: +1(408)296-6883 Fax: +1(408)985-8274.

For registration information contact Colleen Matteis, 
e-mail: sigda@nextwave.com, or cmatteis@aol.com. 
Cancellation must be in writing, and received by Colleen Matteis 
before January 24,1996.



Article: 2511
Subject: Lattice Products
From: gwise@ibm.net
Date: 21 Dec 1995 18:21:12 GMT
Links: << >>  << T >>  << A >>
Can anyone recommend some  reading material to bring me up to speed on
programmable logic devices. Specially useful would be any 3'rd party material
on the subject using the Lattice Semiconductor's products. I am real new to
programmable logic (abt 3 weeks). I'm using the Lattice ispLSI 1000 and 2000
families. Mainly so that I don't have to buy a programmer. Any recommendations
on free or shareware software especially simulation software would be appreciated.
Thanks.

George..


Article: 2512
Subject: Re-progromable VXI module
From: Dan Blow <blow>
Date: 21 Dec 1995 19:21:29 GMT
Links: << >>  << T >>  << A >>
I have a need for a "C" size VXI module that contains  a couple of
re-progarmable FPGA modules.  Does anyone know of a device such as this.

Module needs to have the VXI communication interface and the circuitry to
accept the design personalazation data and program the local FPGA's.  The
majority of the FPGA I/O pins needs to commited to connectors on the front of
the VXI module.



Article: 2513
Subject: Re: Career value: VHDL or Verilog?
From: mac@verilog.com (Michael McNamara)
Date: 21 Dec 1995 12:04:29 -0800
Links: << >>  << T >>  << A >>

In article <Bb5Px*T-1@wolf359.exile.org> eric@wolf359.exile.org (Eric Edwards) writes:
   I am fishing for trends here...

   In an effort to kick start my engineering career into existance, I intend
   to learn one of these HDLs soon.  The question is, which one?  Industry
   seems not to hire generalists so it seems best to put the energy into one
   rather that divide among both.  Which HDL would provide the greatest benefit
   for someone trying to break into logic design?


You will get no agreement from me that industry does not hire
generalists.  With trends, as you mention, changing so often,
generalists are oh so important.

The choice of HDL is not the issue.  Learn them both, they will both
be around a long time.

The real important thing to learn in logic design is what you are
trying to create.  View the HDL as the medium, and your goal is to get
across a message.  You want to create a easily verifiable,
synthesizable description of hardware, which will run at high clock
speeds while implementing complex protocols.

Focusing on Verilog vesus VHDL is like an artist focusing on the
decision between using watercolor and oil paints.  What the artist
should be considering is making delightful depictions of interesting
scenes that catch the viewers interest.

You should seek to set up in yourself the ability to be proficient in
any and all the tools the design shop in which you want to work will
be using.  Bringing proficiency in some existing tools is useful.
Better is to bring the ability to critically evaluate the tools in
use, and the capability to create a masterpiece in whatever medium
your might have at your disposal.

	Michael McNamara.
-- 
Michael McNamara
Verilog-HDL Consulting Services, Inc.


Article: 2514
Subject: Re: Floor Planning for Xilinx
From: ddecker@usa.pipeline.com(mush)
Date: 22 Dec 1995 07:03:20 GMT
Links: << >>  << T >>  << A >>
Stephen L. Wasson of HighGate Design, Inc. Saratoga, CA is my idea of a
florplaning GURU. 
He lectures at Xilinx Advanced Seminars and at various conferences. He will
be speaking at SuperCon 96. His papers on this subject are usually
available by calling him and asking for them. I notice he has a new article
in the Jan 96, Integrated System Design. 
 
He floor plans before designing the circuit so that his design will best
take best advantage of that part of the chip where it must reside to be
optimal. 
 
I would recommend that you read as many of Stephen's articles as you can
scrounge, and then use the new floor planner in the 6.0 Xilinx tools to
implement Stephen's philosophies. 
 
There is also an animated tutorial on floor planing that comes with the new
Xilinx tools. 
 
Dave Decker 
Diablo Research Corp. 
ddecker@diablores.com  
ddecker@usa.pipeline.com 
 
-- 
mush 



Article: 2515
Subject: Re: [q][Reverse Engineering Protection]
From: rdd@access1.digex.net (R. D. Davis)
Date: 22 Dec 1995 12:01:20 -0500
Links: << >>  << T >>  << A >>
In article <DI6H3x.5Lz@world.std.com>,
John Cooley <jcooley@world.std.com> wrote:
>Jyri Hamalainen <jyrih@cat.co.za> wrote:
>>Does anyone here know anything about protecting ASIC's from reverse 
>>engineering? OR logic camourflaging? With modern technologies such as 
>>electron beam induced current imaging and Charge induced voltage 
>>alteration (Scania Labs), I suppose there are no more solutions to 
>>protecting ones investment?

This isn't protecting one's investment, it's cheating the purchaser
of ones products by making them unrepairable.  Built in obsolescence
is what this amounts to. 

>Jyri, one clever idea for protecting designs in chips I heard of was
>using Xilinx FPGA's that were programmed once at the factory with a
>small battery attached after programing.  (That is, the power-up
>program for the Xilinx part was NOT included in the PCB.)  What this
>did was make the circuit unreversable but still functional.

Such designs should only be used for top-secret military type
equipment, never for equipment sold for commercial or consumer use.
Anyone who designs such equipment for commercial or cosumer use is a
creep and an idiot.  My reasoning is that after some number of years,
someone who PAID for this equipment may wish to cotinue using it, and
may want to try to repair it.  

-- 
R. D. Davis  *  http://www.access.digex.net/~rdd    \Computer preservationist. 
Home: +1 410 744-7964 * Eccentrics have more fun! :-)\Unwanted systems gladly
Unconventional Computer Consulting & PERQ Software,   \disassembled, removed 
divs. of Transpower Industries, Inc. +1 410 744-4900   \for free and preserved.


Article: 2516
Subject: Re: Gated Clock Problem in Xilinx FPGA Implementation
From: <joebird>
Date: 22 Dec 1995 17:46:43 GMT
Links: << >>  << T >>  << A >>
To implement a clock enable in Verilog, do the following :

always @ (posedge clk or posedge reset)
begin
  if (reset)
    q <= 1'b0;  // or q <= 1'b1; (for preset)
  else if (clken)
    q <= d;
  else
    q <= q;
end

The begin/end and the last else condition are redundant, but cleaner
to read.

-Joe



Article: 2517
Subject: Re: Career value: VHDL or Verilog?
From: weigand@ssnet.com (Steve Weigand)
Date: 22 Dec 1995 22:33:16 -0500
Links: << >>  << T >>  << A >>
In article <Bb5Px*T-1@wolf359.exile.org>,
Eric Edwards <eric@wolf359.exile.org> wrote:
>I am fishing for trends here...
>
>In an effort to kick start my engineering career into existance, I intend
>to learn one of these HDLs soon.  The question is, which one?  Industry
>seems not to hire generalists so it seems best to put the energy into one
>rather that divide among both.  Which HDL would provide the greatest benefit
>for someone trying to break into logic design?

Actually,  I think they both are suitably similar to simply say that if
you learn one,  you've learned the other.  On your resume,  just put down,
"VHDL/Verilog HDL".  

I've seen more job wanted ads that say "VHDL" than "Verilog HDL",  so 
it looks like VHDL is a bit more popular.   I could be wrong,  though.


Ciao for now,
  - Steve Weigand
    (weigand@marlin.ssnet.com)



Article: 2518
Subject: Re: [q][Reverse Engineering Protection]
From: chubbard@oneworld.owt.com (Charles W. Hubbard)
Date: Sat, 23 Dec 1995 19:57:09 GMT
Links: << >>  << T >>  << A >>

> Such designs should only be used for top-secret military type
> equipment, never for equipment sold for commercial or consumer use.
> Anyone who designs such equipment for commercial or cosumer use is a
> creep and an idiot.  My reasoning is that after some number of years,
> someone who PAID for this equipment may wish to cotinue using it, and
> may want to try to repair it.  

Huh?

I don't follow your argument at all.  How does implementing  some form
of protection against reverse-engineering stops an owner from
repairing the equipment which contains the protected chip?  After all,
ASICs are custom, single chips.  Nobody is going to "repair" a bad
ASIC.  If you suspect you have a bad one the only thing you can do is
replace the chip.  To do that you need to go to the chip manufacturer
to get a new one.  How is this any different if the manufacturer tries
to take steps to guard his chip against reverse engineering?

C.

==========================================================================
Charlie Hubbard                   | As the great philosopher Bingo once
chubbard@oneworld.owt.com         | said, "I have seen the future and
http://www.owt.com/users/chubbard | Java is its name-o."
==========================================================================



Article: 2519
Subject: Re: [q][Reverse Engineering Protection]
From: dfraser@Direct.CA (Dan Fraser)
Date: 23 Dec 1995 23:27:51 GMT
Links: << >>  << T >>  << A >>
Do what you may. It will only slow down the reverse engineering but
never stop it. The only thing you can do it to keep putting out great
products, obsoleting your own stuff every 2 years. 


Article: 2520
Subject: Re: [q][Reverse Engineering Protection]
From: frodo4@ix.netcom.com(John Souders )
Date: 24 Dec 1995 07:22:08 GMT
Links: << >>  << T >>  << A >>
In <4beo90$b8c@access1.digex.net> rdd@access1.digex.net (R. D. Davis)
writes: 
>
>In article <DI6H3x.5Lz@world.std.com>,
>John Cooley <jcooley@world.std.com> wrote:
>>Jyri Hamalainen <jyrih@cat.co.za> wrote:
>>>Does anyone here know anything about protecting ASIC's from reverse 
>>>engineering? OR logic camourflaging? With modern technologies such
as 
>>>electron beam induced current imaging and Charge induced voltage 
>>>alteration (Scania Labs), I suppose there are no more solutions to 
>>>protecting ones investment?
>
>Anyone who designs such equipment for commercial or cosumer use is a
>creep and an idiot.
You may have not have noticed that the question referred to ASICS,
which by their very nature, cannot easily be replaced by off the shelf
stuff. 
They are custom parts. (application specific integraded circuits)
Typically a lot of time and money goes into designing these parts. 


Article: 2521
Subject: Xiling 4025E routing info
From: milne@cv.com (Ewan D. Milne)
Date: 26 Dec 1995 18:18:03 GMT
Links: << >>  << T >>  << A >>
Can anyone give me a quick synopsis of the number of each type
of routing connection (single length, double length, longlines)
present in each row and column of the 4025E device?  I am trying
to determine if a large datapath design will fit.  The entire
design will be manually placed, but has a very regular structure.

The only information I have found so far is that there are 8
single length lines per row/column and 6 longlines.  However I
have come across a note that states that only some of the horizontal
longlines have TBUFs.  The design would require 4 such lines per
row.  I would like to verify this and obtain more specific information.

Also, has anyone had any experience with implementing small
multiplier arrays in the 4000E series devices?  I know that it
is possible, but the question is whether the resulting performance
is good enough to be worth a larger device size.

Thanks in advance for any information or stories.

----------------------------------------------------------------
Ewan D. Milne / Computervision Corporation  (milne@petra.cv.com)


Article: 2522
Subject: Re: Xiling 4025E routing info
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 27 Dec 1995 04:27:18 GMT
Links: << >>  << T >>  << A >>
In article <4bpe8r$bd7@hettar.cv.com> milne@cv.com (Ewan D. Milne) writes:
>Can anyone give me a quick synopsis of the number of each type
>of routing connection (single length, double length, longlines)
>present in each row and column of the 4025E device?  I am trying
>to determine if a large datapath design will fit.  The entire
>design will be manually placed, but has a very regular structure.
>
>The only information I have found so far is that there are 8
>single length lines per row/column and 6 longlines.  However I
>have come across a note that states that only some of the horizontal
>longlines have TBUFs.  The design would require 4 such lines per
>row.  I would like to verify this and obtain more specific information.
>
>Also, has anyone had any experience with implementing small
>multiplier arrays in the 4000E series devices?  I know that it
>is possible, but the question is whether the resulting performance
>is good enough to be worth a larger device size.
>
>Thanks in advance for any information or stories.
>
>----------------------------------------------------------------
>Ewan D. Milne / Computervision Corporation  (milne@petra.cv.com)

The 4025E has the same routing resources as the 4025, and on a per tile
basis, it is the same as the 4003, 4003H, 4005, 4005H, 4006, 4008, 4010,
4010D, 4013, 4013D, and all of their 'e' series equivalents, where
appropriate.  All of these devices have 8 global clock nets, 8 locals per
channel (horizontal and vertical), 4 doubles per channel ( H and V), and 6
long lines (H and V). Only 2 of the horizontal longlines per row have
tbufs on them, and everything in the arcitecture is biassed to be used as
2 bits per row, with datapath elements being vertical structures, and the
datapath bus running orthogonal to these structures (i.e. using the
horizontal longlines for distributing bi-directional data). 

The E series has a few extra pips between the global lines and the CLBs, 
but not enough to have a serious effect. There are also some minor
routing changes inside the CLB, plus of course the dual port sync RAM 
capability. E series is also available in speed grades that are 
significantly faster than what's available in XC4000 devices.

If you really need 4 bidirectional bits per row, then this is not going 
to work for you. Although....  The tbuf lines can be split in the middle, 
allowing the lines on the left and right side of the chip to be 
independent. There are some cases where this can be quite useful.

As always, the success of fast complex datapaths in the larger devices is
very dependent on the quality of the floorplan.

If you write about the design you are doing (in a lot more detail), then 
I could make some recomendations.

I have built over 100 small multipliers in XC4000E in a bunch of designs. 
They were quite specific to an application, and could hardly be called
'general purpose'. They were all "multiply number (8 to 14 bits) by a
constant", with some interesting constraints on what the constants could
be. Some of these multipliers generated outputs 24 bits wide. All ran at 
about 33MHz in various 4006E-3, 4008E-3, and 4010E-3. All included a 
register on the output.

Although not very 'macho', I prefer to stay away from the bragging-rights
devices like the 4025(E), and do my designs in a pair of 4010(E) or
4013(E) devices. It is easier to route, the designs run faster, it forces
me to do the partitioning, and it is cheaper.

Hope some of this is of help  :-)

	Philip Freidin





Article: 2523
Subject: Re: [q][Reverse Engineering Protection]
From: rob-l@superlink.net (Rob-L)
Date: 27 Dec 1995 07:39:43 GMT
Links: << >>  << T >>  << A >>
R. D. Davis (rdd@access1.digex.net) wrote:
: This isn't protecting one's investment, it's cheating the purchaser
: of ones products by making them unrepairable.
[snip]
: My reasoning is that after some number of years, someone who PAID for
: this equipment may wish to cotinue using it, and may want to try to
: repair it.

When someone buys something, they should expect proper operation for some 
time, but not forever.  If it can be repaired, great, but it can provide 
value even if it fails later on.  That's not cheating the purchaser.

With electronic components/assemblies, the manufacturer has configured 
some materials for you, in order to perform some function you desire.  
You pay them for the product, and you get that function for at least the 
warranty period or some reasonable time for the type of device.

So you make a protected chip, and make it to last some number of hours 
minimum.  If it fails before then, it gets replaced free.  If it lasts 
beyond its expected lifetime, that's free use of a product, which is a 
benefit to the purchaser.  If a product is not used as intended and it 
fails, or if it's tampered with and self-destructs, the purchaser eats 
the loss.  That's the way it's always been.


Article: 2524
Subject: Re: [q][Reverse Engineering Protection]
From: hbaker@netcom.com (Henry Baker)
Date: Wed, 27 Dec 1995 16:28:15 GMT
Links: << >>  << T >>  << A >>
In article <4bqt7v$q99@earth.superlink.net>, rob-l@superlink.net (Rob-L) wrote:

> With electronic components/assemblies, the manufacturer has configured 
> some materials for you, in order to perform some function you desire.  
> You pay them for the product, and you get that function for at least the 
> warranty period or some reasonable time for the type of device.
> 
> So you make a protected chip, and make it to last some number of hours 
> minimum.  If it fails before then, it gets replaced free.  If it lasts 
> beyond its expected lifetime, that's free use of a product, which is a 
> benefit to the purchaser.  If a product is not used as intended and it 
> fails, or if it's tampered with and self-destructs, the purchaser eats 
> the loss.  That's the way it's always been.

OK -- I just want to clarify one thing.  If the reverse-engineered-protected
chip includes a clock that registers the number of cycles that the chip has been
used, at which point it shuts itself down, never to work again, then this
chip is the ideal to which your organization aspires??

-- 
www/ftp directory:
ftp://ftp.netcom.com/pub/hb/hbaker/home.html




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search