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Messages from 2675

Article: 2675
Subject: HowTo access a SRAM with a XC4000
From: Philipp Georg <pg@mpik-tueb.mpg.de>
Date: Tue, 23 Jan 1996 11:22:12 +0100
Links: << >>  << T >>  << A >>
I'm trying to interface a CCD-Chip to a microcontroller using
a XC4000. To store the incoming pixeldata I need to R/W a SRAM with the
FPGA. What I would like to know is if this is in general possible and
wich problems could arise in such a design. Also, if someone tried
something similar before, and could provide some sample code written in
ABEL I would be really glad - Thanx.

Philipp Georg
-- 
Max-Planck-Institut
fuer biologische Kybernetik 
E-Mail: pg@mpik-tueb.mpg.de
http://www.mpik-tueb.mpg.de/


Article: 2676
Subject: AT&T Orca vs Xilinx
From: kurt@emphasys.de (Volker Kurt Kamp)
Date: Tue, 23 Jan 1996 15:10:45 +0100
Links: << >>  << T >>  << A >>
Hi,
has anyone expirience with AT&T ORCA FPGAs ?
For some designs we think about switching from Xilinx to ORCA.
Thanks in advance for any information and comparison of the tools.
Kurt.

-- 
 _/_/_/_/_/_/_/
             _/   Volker Kurt Kamp (kurt@emphasys.de)
 _/_/_/_/_/  _/
         _/  _/   EMPHASYS Informationstechnik GmbH
 _/_/_/  _/  _/   Alt-Moabit 94 - 10559 Berlin - Germany - Europe
     _/  _/  _/   Tel: +49.30.399883  FAX: +49.30.3922836
 _/  _/  _/  _/


Article: 2677
Subject: Re: PLD JDEC Files
From: "Dave Daurelio" <daurelio@mojo.kodak.com>
Date: Tue, 23 Jan 96 12:25:45 EST
Links: << >>  << T >>  << A >>
I know that Altera has a utilty called "pld2eqn" that will take a jedec file
and produce logic equations in their native AHDL format. It will also allow
you to combine several different jedec files into one altera equation file.
Even if you don't use their design tools, the equation syntax is pretty
straightforward and should allow you to figure out what's going on. The utility
should be on their web site (www.altera.com). I think there's a link there
to their ftp server where the files are located. You might have to search
through their files because I think the utility program is part of an
application note.
The other possibility is: If you have ABEL from DATA I/O, I think they
include a utility called "jed2eqn" which does the same thing.

Article: 2678
Subject: FPGAs for Newbie?
From: peb@trsvr.tr.unisys.com (Pete Becker)
Date: Tue, 23 Jan 1996 18:12:51 GMT
Links: << >>  << T >>  << A >>
I've used Cypress's WARP2 to synthesize JEDEC files for PLD's from VHDL.  I've 
never worked with FPGA's at all before, but want to start implementing my 
logic in them.  Considering the price/performance/ease-of-use trade-off, I 
need advice about the following:

1) What is a good chip family to start with?
2) What is a good VHDL synthesis package to start with?

I need all tools to run under Windows'95 (or perhaps Linux).

Thanx in advance.

=================================================
Disclaimer: My comments are not necessarily the
opinion of my employer, myself, or anyone else.
-------------------------------------------------
  Peter Becker
  peb@trsvr.tr.unisys.com
=================================================


Article: 2679
Subject: Re: XILINX XACT 6.0.0 Tools flaky
From: tliehe@rainbow.rmii.com (Tom Liehe)
Date: 23 Jan 1996 18:23:11 GMT
Links: << >>  << T >>  << A >>
Gavin Melville (gavin@cypher.co.nz) wrote:
: Hi All,

: I am using the windows based XACT (step) tools, and have found them to
: be a little "flaky", with occasional lockups and crashes -- in
: particular the Design Editor (V5.2.0).

[ snip ]

: Has anyone else, in particular anyone who depends on these tools found
: Ver 6.0.0 to be flaky ?

I've been using 6.0.0 for just over a month and I agree it leaves a lot
to be desired.  I've experienced crashes using the Design Editor also,
but I don't use it very much and it seems the rest of the tools run without
crashing.  But they are SLO-O-OW!  I don't think Xilinx bothered to hire
anyone who really knew how to write a Windows program - and they must
have done all their testing on the fastest Pentiums around.  My 486DX2/66
with 32 MB RAM takes forever to load Design Manager and I think APR and
PPR both run significantly slower than they did under DOS.  Our local
FAE supposedly knows some Windows tuning tricks to make things run better
but he hasn't returned my calls yet.

OTOH, I like not having to deal with xmake or my own batch files - the
'flow engine' is a welcome improvement, and I hope to get some good
usage out of the new floorplanner with some new designs coming up.

I'm sure Xilinx would consider these complaints to be minor.  But I've
got one major complaint that they aren't going to be able to just
brush under the rug:  This thing is still just a shell for DOS based
tools using Phar Lap to manage memory!  This means that, for example,
makebits on a XC5210 still requires 32MB of physical RAM.  And I just
found out that processing a 4025E requires 64MB of physical RAM!  Wouldn't
these requirements go away if they used actual Windows memory management?

I'm looking into using ORCA 2C26's instead...
--
Tom Liehe
(will design FPGAs for food)


Article: 2680
Subject: Re: AT&T Orca vs Xilinx
From: tliehe@rainbow.rmii.com (Tom Liehe)
Date: 23 Jan 1996 18:36:27 GMT
Links: << >>  << T >>  << A >>
Volker Kurt Kamp (kurt@emphasys.de) wrote:
: Hi,
: has anyone expirience with AT&T ORCA FPGAs ?
: For some designs we think about switching from Xilinx to ORCA.
: Thanks in advance for any information and comparison of the tools.
: Kurt.

As I wrote in the 'XACT 6.0.0 flaky' thread, I am about to start
looking at ORCA 2C26 parts becasue Xilinx tools require 64MB RAM
to do a 4025E.  I've got the demo (90 day) software and will install
it today.  They only require 30MB for a 2C26.  So I'll post what I
find out, but would like to hear from others on what they think
about AT&T's tools, parts, and prices as compared to Xilinx.
--
Tom Liehe
(will design FPGAs for food)


Article: 2681
Subject: In Search of Graphical VHDL Code Generators for FPGA Design
From: Lance Gin <c43lyg@dso.hac.com>
Date: 23 Jan 1996 23:40:32 GMT
Links: << >>  << T >>  << A >>
I'm looking for opinions and feedback regarding any of the VHDL code
generators commercially available, such as those from Escalade, iLogix,
Mentor, R-Active, Speed Electronic, Summit Design, Vista Tech, and
"Shrink Wrap" vendors like Data IO and Viewlogic

We're trying to build a design environment, primarily targetting Xilinx,
that will allow us to mix schematics and generated VHDL. Initial designs
would have some FSM's and run 2K-12K gates. The ability to accommodate
VHDL newbies and incrementally gain VHDL experience is a plus.

Any comments you might like to share concerning your experiences/opinions/ideas
would be greatly appreciated, posted in public or private. Thanks,

____________________________________________________________________________

Lance Gin                                              "off the keyboad
Delco Systems - GM/Hughes Electronics                   over the bridge,
OFC: 805.961.7737  FAX: 805.961.7329                    through the gateway,
C43LYG@dso.hac.com                                      nothing but NET!"
____________________________________________________________________________




Article: 2682
Subject: Revision Figure of Merit?
From: tak@core.rose.hp.com (Tom Keaveny)
Date: Wed, 24 Jan 1996 03:15:52 GMT
Links: << >>  << T >>  << A >>
Has anyone ever done a study on the various CPLD/FPGA topologies for their
ability to tolerate design revision once pins have been locked?  
It would be useful to know at what utilization level (whether it is pins,
cells, or routing elements) different architectures get bogged down.

I know that various vendors claim "utopia" as far as dealing with design
changes, but my experience has been that reality is far from that.

The benchmarks that I have seen only address initial fit and speed, and
not supportability or capacity for revision.

Pointers are appreciated...
==
tom keaveny
Hewlett Packard Co.


Article: 2683
Subject: Multipliers? How many different arch?
From: frosty@tbc2.tbcnet.com (Joseph Gottlieb)
Date: 24 Jan 1996 03:22:13 GMT
Links: << >>  << T >>  << A >>
Can some one direct me to a source that covers all the digital
multipliers that one can implement. Parallel, Fast, Serial... I am
looking for material on a specific type that uses booths algorithm and I
can not find any printed material on it. Thanks

-Joseph Gottlieb
Northern Illinois University
e1131@eiger.ceet.niu.edu


Article: 2684
Subject: Re: In Search of Graphical VHDL Code Generators for FPGA Design
From: Brian Childs <brian@vizef.demon.co.uk>
Date: Wed, 24 Jan 1996 10:50:14 +0000
Links: << >>  << T >>  << A >>
In article <4e3rlg$ii1@hacgate2.hac.com>, Lance Gin <c43lyg@dso.hac.com>
writes
>I'm looking for opinions and feedback regarding any of the VHDL code
>generators commercially available, such as those from Escalade, iLogix,
>Mentor, R-Active, Speed Electronic, Summit Design, Vista Tech, and
>"Shrink Wrap" vendors like Data IO and Viewlogic
>
>We're trying to build a design environment, primarily targetting Xilinx,
>that will allow us to mix schematics and generated VHDL. Initial designs
>would have some FSM's and run 2K-12K gates. The ability to accommodate
>VHDL newbies and incrementally gain VHDL experience is a plus.
>
>Any comments you might like to share concerning your experiences/opinions/ideas
>would be greatly appreciated, posted in public or private. Thanks,
>
>____________________________________________________________________________
>
>Lance Gin                                              "off the keyboad
>Delco Systems - GM/Hughes Electronics                   over the bridge,
>OFC: 805.961.7737  FAX: 805.961.7329                    through the gateway,
>C43LYG@dso.hac.com                                      nothing but NET!"
>____________________________________________________________________________
>
>

You should also take a look at FlowHDL from Knowledge Based Silicon 803-
779-2504. It's lower cost (at least 2:1), easy to use, produces the
smallest synthsised implementation and readable code.

If your looking for points to evaluate against I would sugest some of
the following:-

1. Look closely at the code produced. You cannot get away from debuging
the machine generated code. If it is not readable you will have a
problem.

2. Make sure you synthesise the generated code. Sounds obvious but many
people I've talked to have skipped this step (top save time). The tools
I am familiar with produce *very* different gate counts, in some cases
as much as 3:1.

3. Ease of use. Obvious again. Some of the more 'pretty' tools look
great when demo'd but you need to spend some time to become as familiar
with the tool as the person giving the demo. This learning curve is
typically required for each project. The amount of time, during a design
cycle, spent using these tools is typically less than 1/3. During the
remainging 2/3 you will forget a lot...

These are just a few key pointers. If you would like some more send me a
private mail.

I have to state a vested interest here, as our company represents
flowHDL in the UK, *BUT* I feel the things to look out for, listed
above, are not biased. I'll leave you to be the judge.

Happy evaluating...

-- 
Brian Childs - VIZEF Limited


Article: 2685
Subject: Re: Multipliers? How many different arch?
From: Russell Petersen <russp>
Date: 24 Jan 1996 15:44:27 GMT
Links: << >>  << T >>  << A >>
One good reference is:

	Multiplier Policies for Digital Signal Processing by Gin-Kou Ma and Fred J.
Taylor published in IEEE ASSP Magazine, Jan 1990.


-- 
Russell J. Petersen            *****     *****
Hewlett Packard ICBD           ***  /_  __ ***  email: russp@valhalla.fc.hp.com
3404 E. Harmony Rd.            **  / / /_/  **  Phone: (970) 229-7007 
Ft. Collins, CO 80525          ***    /    ***  fax:   (970) 229-6580
                               *****     *****



Article: 2686
Subject: FPGA'96 Adv. Registration Deadline is tomorrow (1/25/96)
From: cong@rabbit.cs.ucla.edu (Dr. Jason Cong)
Date: 24 Jan 1996 08:21:13 -0800
Links: << >>  << T >>  << A >>
FPGA'96 Adv. Registration Deadline is tomorrow (1/25/96).
Register now and save $70 in registration fee.   
Enclosed is an updated advance program.

Jason Cong
FPGA'96 publicity chair

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

			FPGA `96 Advance Program
			------------------------

1996 ACM/SIGDA Fourth International Symposium on Field-Programmable Gate Arrays

			     February 11-13, 1996
		Monterey Beach Hotel, Monterey, California, USA

Sponsored by ACM SIGDA, and Xilinx, Inc., Altera Corp. and Actel Corp.

    http://www.cs.washington.edu/research/projects/lis/www/fpga96

Over the past ten years FPGAs have revolutionized the way many systems are 
designed by providing a low-cost, fast-turnaround implementation alternative. 
This is an exciting time in an exciting field that is still expanding as new 
technologies appear, new architectures are proposed, and new CAD tools are 
developed to address problems specific to FPGAs. This Symposium focuses on the 
architectural and algorithmic issues that FPGA architects and CAD designers 
face today and in the future. This is a forum where researchers from industry 
and university present and debate the latest ideas in FPGA design and 
application.

The technical program consists of papers concerning both the practical 
and theoretical aspects of FPGA architecture, CAD algorithms for using 
and testing FPGAs, and applications. The Symposium will be of interest 
to those developing FPGA architectures, both at the chip and board level, 
and those developing CAD algorithms for FPGAs. The Symposium is not of direct 
interest to immediate users of FPGAs.

General Chair: 	Jonathan Rose, University of Toronto
Program Chair: 	Carl Ebeling, University of Washington
Publicity Chair: 	Jason Cong, UCLA
Local Chair: 	Pak Chan, UC Santa Cruz
Finance Chair: 	Steve Trimberger, Xilinx

 Program Committee
Michael Butts, Quickturn
Pak K. Chan, UCSC
Paul Chow, U. Toronto
Jason Cong, UCLA
Ewald Detjens, Mentor
Carl Ebeling, U. Washington
Gareth Jones, Pilkington
Dwight Hill, Synopsys
Brad Hutchings, BYU
Sinan Kaptanoglu, Actel
Jonathan Rose, U. Toronto
Richard Rudell, Synopsys
Rob Rutenbar, CMU
Takayasu Sakurai, Toshiba
Martine Schlag, UCSC
Tim Southgate, Altera
Steve Trimberger, Xilinx
Nam-Sung Woo, ATT

Program Sunday February 11, 1996

6:00pm	Registration

7:00pm	Welcoming Reception, 
	Monterey Beach Hotel, Monterey

Monday February 12, 1996

7:30am	Continental Breakfast/Registration

8:20am	Opening Remarks

Session 1: Novel FPGA Architectures 

Chair: Jonathan Rose, University of Toronto

8:30am	Hybrid FPGA Architecture, 
	A. Kaviani and S. Brown, University of Toronto

8:50am	Plasma:	 An FPGA for Million Gate Systems, 
	V.R. Amerson, R. Carter, W. Culbertson, 
	P. Kuekes, G. Snider, L. Albertson, HP Labs

9:10am	Flexible FPGA Architecture Realized of General 
	Purpose Sea of Gates, K. Azegami, S. Kashi-
	wakura, K. Yamashita, Fujitsu Laboratories

Posters: Novel FPGA Architectures

9:30-10:30am Coffee & Posters	

Session 2: Logic Module Design

Chair: Richard Rudell, Synopsys

10:30am Using BDDs to Design ULMs for FPGAs, 
	Z. Zilic and Z.G. Vranesic, University of Toronto

10:50am Series-Parallel Functions and FPGA Logic 
	Module Design, 
	S. Thakur, D.F. Wong, University of Texas, Austin

11:10am Combined Spectral Techniques for Boolean 
	Matching, E. Schubert, W. Rosenstiel, University 
	of Tuebingen

Posters: Logic Module Design 11:30-12:00

LUNCH 12:00 - 1:30

Session 3: Performance Issues

Chair: Steve Trimberger, Xilinx

1:30pm  The Wave Pipeline Effect on LUT-Based FPGA 
	Architectures, E.I. Boemo, S. Lopez-Buedo, 
	J.M. Meneses, Universidad Politecnica de Madrid

1:50pm  Timing Optimization for Hierarchical Field-
	Programmable Gate Arrays, 
	V.C. Chan, D.M. Lewis, University of Toronto

2:10pm  Technology Mapping of Sequential Circuits for 
	LUT-Based FPGAs for Performance, 
	P. Pan, C.L. Liu, Clarkson University

Posters: Performance Issues

2:30-3:30pm Coffee & Posters

Session 4: Theoretical Issues in Routing Architectures

Chair: Jason Cong, UCLA

3:30pm  A Method for Generating Random Circuits and 
	Its Application to Routability Measurement, 
	J. Darnauer and W.W-M. Dai, University of 
	California, Santa Cruz

3:50pm  Entropy, Counting, and Programmable 
	Interconnect, A. DeHon, MIT

4:10pm  Universal Switch Modules for FPGA Design, 
	Y-W. Chang, D.F. Wong, C.K. Wong, University of 
	Texas, Austin

Posters: Theoretical Issues in Routing Architectures

4:30-6:00pm Free time/Posters

Dinner 6:00-7:30pm

7:30-9:00pm  PANEL : FPGAs vs. Gate Arrays and Processors: Who Will Win?

Panelists:
	Abbas El Gamal, Stanford
	Bill Carter, Chief Technical Officer, Xilinx
	Jim Hively, VP ASIC Products, LSI Logic
	Michael Ayukawa, Senior Technical Advisor, Chip Express
	Gary Smith, Principal Analyst, Dataquest

The FPGA industry has enjoyed rapid growth in the past ten 
years in terms of chip density and speed as well as ASIC 
market share. In the same period, however, we have also 
observed significant advances in all sectors of the semi-
conductor industry -- state-of-the-art gate arrays have a 
capacity of over 10 million transistors and enable the 
`system-on-a-chip'. Design automation tools have made 
semi-custom designs much faster and easier to achieve while 
yielding both high density and high performance. High-end 
microprocessors have reached over 250 Mhz and can satisfy 
the needs of many real-time control and DSP/multi-media 
applications. New rapid prototyping technologies, such as 
laser-programmed gate arrays, have emerged for high-speed 
high-density prototyping.

Given such a dynamic industry undergoing exponential 
growth, it is interesting to ask where FPGAs will stand five 
or ten years from now in the wide spectrum of design 
technologies. Will its share of the ASIC market continue to 
increase, or will it become more of a niche technology? It is 
likely that the relative importance of these technologies will 
change drastically over the next five to ten years.

This panel comprises technology experts in the competing 
areas of FPGAs, gate arrays, processors and other 
technologies. They will focus on the technological and 
economic issues that give one implementation medium an 
advantage over others and discuss how new technologies and 
architectural developments may change the competitive 
balance. They will discuss the past, present and future of the 
technological forces driving the industry and debate where 
those forces are likely to take us in the future.

Tuesday February 13, 1996

Session 5a: Field-Programmable Analog Arrays

Chair: Paul Chow, University of Toronto

8:30am  Design and Implementation of a Field- 
	Programmable Analogue Array, A. Bratt and 
	I. Macbeth, Pilkington Microelectronics

8:50am  The EPAC Architecture: An Expert Cell
	Approach to Field-Programmable Analog 
	Arrays, H.W. Klein, IMP

Posters: Field-Programmable Analog Arrays

9:10-9:40am Coffee & Posters

Session 5b: Testing

Chair: Martine Schlag, UC Santa Cruz

9:40am  Diagnosing Programmable Interconnect Systems 
	for FPGAs, D. Ashen and F. Lombardi, 
	Texas A&M University

10:10am Evaluation of FPGA Resources for Built-In Self-
	Test of Programmable Logic Blocks, 
	C. Stroud, P. Chen, S. Konala, M. Abramovici, 
	University of Kentucky

Posters: Testing

10:30-11:00am Coffee & Posters

Session 6: The Future of Fuse and SRAM FPGA Technologies

Chair: Tim Southgate, Altera

11:00am 
	John McCollumn, ACTEL
11:20am
	Bill Carter, Xilinx

	Two invited speakers will present the state of the 
	art in (anti-)fuse and SRAM technologies and 
	discuss the impact of recent developments in 
	these technologies on future architectures.

Posters: FPGA Vendors 11:40-12:00 

LUNCH 12:00 - 1:30

Session 7: Applications

Chair: Dwight Hill, Synopsys

1:30pm  DPGA Utilization and Application, 
	A. DeHon, MIT

1:50pm  Integrating Software with Run-Time Re-
	configured Hardware, M.J. Wirthlin and B.L. 
	Hutchings, Brigham Young University

2:10pm  Computing the Discrete Fourier Transform on 
	Virtual Systolic Arrays, 
	C. Dick, La Trobe University

Posters: Applications

2:30-3:30pm Coffee & Posters 

Session 8: Design Systems

Chair: Pak Chan, UC Santa Cruz

3:30pm	RASP: A General Logic Synthesis System for 
	SRAM-based FPGAs, J. Cong and J. Peck, UCLA

3:50pm  Emerald - An Architecture-Driven Tool Compiler 
	for FPGAs, D. Cronquist and L. McMurchie, 
	University of Washington

4:10pm  Structured Design Implementation - A Strategy 
	for Implementing Regular Datapaths on FPGAs, 
	A. Koch, Technical University, Braunschweig

Posters: Design Systems 4:30-5:00

5:00pm Symposium Ends.

		Hotel Information
		-----------------

The Symposium will be held at the Monterey Beach Hotel, 
2600 Sand Dunes Dr., Monterey, CA 93940, USA. The 
phone number for room reservations is 1-800-242-8627 or 
+1-408-394-3321 (Fax +1-408-393-1912). Reservations 
must be made before January 6, 1996. Identify yourself 
with the group Association for Computing Machinery 
FPGA `96 Symposium to receive the special Symposium 
rates, which are $75 for single or double Gardenview and 
$105 for single/double Oceanview. Parking is free. Check-
in time 4pm.

Directions to Hotel: From San Jose (a 1.5 hour trip) or 
San Francisco Airport (2.5 hrs) take HWY 101 South to 
HWY 156 West to HWY 1 South. On HWY 1 South, take 
Seaside/Del Rey Oaks exit. The hotel is at this exit, on the 
ocean side.

You can also fly directly to the Monterey Airport, which is 
served by United, American and other airlines with at least 
8 flights per day.

FPGA `96 REGISTRATION 
---------------------

The Symposium registration fee includes a copy of the symposium proceedings, 
a reception on Sunday evening, February 11, coffee breaks, lunch on both days, 
and dinner Monday evening, February 12.


First Name:___________________________________________
Last Name:____________________________________________
Company/Institution___________________________________
Address:______________________________________________

City:___________________State:________________________
Postal Code:_______________Country:____________________

Email:__________________________________________________
Phone:_______________________Fax:_______________________


ACM Member #____________
Circle Fee:   Before January 25, 1996  	After January 25, 1996 

ACM/SIGDA Member  	US $320    		US $390

*Non-Member 		US $420 		US $490

Student 		US $90			US $90 
(does not include reception or banquet, available for $20 and $35 respectively)

*If you are not an ACM/SIGDA member we are giving you the opportunity to 
join by paying your first year's dues out of your conference non-member 
registration fee -- a US$100 value. Forms will be available at on-site 
registration.

Guest Reception Tickets #Tickets______x US $20 ______
Guest Banquet Tickets #Tickets______x US $35 ______

Total Fees:____________________(Make checks payable to ACM/FPGA'96)

Payment Form (Circle One): AMEX   MASTERCARD  VISA   CHECK

Credit Card#:____________________________________
Exp. Date:_______________________________________
Signature:_______________________________________

Send Registration with payment to:

 FPGA `96 - Colleen Matteis, 
 553 Monroe St., 
 Santa Clara, CA. 95050, 
 USA. 

 Phone: +1(408)296-6883 Fax: +1(408)985-8274.

For registration information contact Colleen Matteis, 
e-mail: sigda@nextwave.com, or cmatteis@aol.com. 
Cancellation must be in writing, and received by Colleen Matteis 
before January 24,1996.



Article: 2687
Subject: any altera library sites
From: Howard Del Fava <delfava@seo.com>
Date: Wed, 24 Jan 96 10:26:24 PDT
Links: << >>  << T >>  << A >>

Does anybody know of an ftb or web site 
for altera maxplus libraries?
Please Email me at
delfava@seo.com



Article: 2688
Subject: IVC-96 Hotel/Conference Registration Deadlines Fast Approaching
From: skmurphy@netcom.com (Sean Murphy)
Date: Wed, 24 Jan 1996 18:41:32 GMT
Links: << >>  << T >>  << A >>
   The IVC-96 WWW Site (http://www.e2w3.com/iccad/) Has the Complete
   Program, Conference Registration, Tutorial Registration, and Hotel 
   Reservation Forms On-Line. Hotel Registration is due Friday Jan 26,
   Conference Advance Registration closes Friday Feb 2.

The fifth annual International Verilog HDL (IVC-96) conference is for
designers, ASIC vendors, CAD tool developers, university students, and
researchers. IVC-96 provides an international forum for exchanging
information about Verilog HDL, the language itself and its use, and the
design methodologies that have been developed for different design and
support environments.

IVC-96 will be held Monday, Febraury 26 through Wednesday, February 28, at
the Westin Hotel in Santa Clara, California.  This year, the conference is
co-locating with the VHDL International User Forum (VIUF) and provides
designers and EDA vendors a single HDL event to attend. Furthermore, this
year the conference will celebrate the official standardization of the
Verilog HDL by IEEE. The Conference is sponsored by Open Verilog
International and the IEEE Computer Society.
   
______________________________________________________________________________
Sean Murphy, President, Leader-Murphy, Inc. (skmurphy@netcom.com 408 252-9676)
WWW-Enabled Applications and Methodology Consulting: "Knowledge, Refined from
Information Derived from Data, is the Fundamental Asset of the Enterprise"
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Article: 2689
Subject: Re: HowTo access a SRAM with a XC4000
From: fmicale@motown.ge.com (Francesco Micale, X4438)
Date: 24 Jan 1996 18:41:32 GMT
Links: << >>  << T >>  << A >>
Why not use a dual ported RAM? It would be MUCH less expensive.
-f




Article: 2690
Subject: Qn on XC3030 and XC3164 'Divide By Two'
From: pac1@waikato.ac.nz
Date: 25 Jan 96 08:47:11 +1300
Links: << >>  << T >>  << A >>

Qn on XC3030 and XC3164 Problems/Tricks:

As part of FPGA designs in the past I've made simple divide by two cells using
flipflops with the XC3030. As expected they work - not much to it.

Now I'm using a XC3164 and can't even get a divided by two cell working.  I can
do other things like take the inputed signal and AND gate it with another input
then send it to an output pin - this works OK.  But when I try to just divide
it by two (I've tried a couple of ways to do this including using a macro
C2BP.mac) it won't work.

I'm using Xact5.1 and enter my design directly to the LCA.

Should I do something different with the XC3164 to what I did with the XC3030?

regards, Peter Cossey




Article: 2691
Subject: Re: Revision Figure of Merit?
From: "Steve Knapp (Xilinx, Inc.)" <stevek>
Date: 24 Jan 1996 21:14:35 GMT
Links: << >>  << T >>  << A >>
You may want to look at:

Khalid, Mohammed A.S. and Rose, Jonathan, "The Effect of Fixed I/O Pin
Positioning on the Routability and Speed of FPGAs," in PROCEEDING OF THE
CANADIAN WORKSHIP ON FIELD-PROGRAMMABLE DEVICES (FPD'95), 1995, pages
94 through 102.

In a quick summary, the study showed that 100% of the XC4000-based designs
routed to a fixed pinout.  The competing device failed to route in 21% of
the cases.

The XC4000 family has additional interconnect around the I/O ring to support
fixed pinout.  The XC5200 and XC4000EX families add even more-extensive routing
called VersaRing.  While neither offers an absolute 100% guaranteed pin
locking,
it does provide much more flexibility than others currently available.

The Xilinx CPLD products have 100% interconnect.  Everything is connected to
everything else within the device.  This helps pin locking significantly.

-- Steve Knapp

tak@core.rose.hp.com (Tom Keaveny) wrote:
>Has anyone ever done a study on the various CPLD/FPGA topologies for their
>ability to tolerate design revision once pins have been locked?  
>It would be useful to know at what utilization level (whether it is pins,
>cells, or routing elements) different architectures get bogged down.
>
>I know that various vendors claim "utopia" as far as dealing with design
>changes, but my experience has been that reality is far from that.
>
>The benchmarks that I have seen only address initial fit and speed, and
>not supportability or capacity for revision.
>
>Pointers are appreciated...
>==
>tom keaveny
>Hewlett Packard Co.

-- 
=====================================================================
   _
  / /\/  Steven K. Knapp               E-mail:  stevek@xilinx.com 
  \ \    Corporate Applications Mgr.      Tel:  1-408-879-5172 
  / /    Xilinx, Inc.                     Fax:  1-408-879-4442
  \_\/\  2100 Logic Drive                 Web:  http://www.xilinx.com
         San Jose, CA 95124

=====================================================================



Article: 2692
Subject: Re: Multipliers? How many different arch?
From: wdbishop@dictator.uwaterloo.ca (Bill Bishop)
Date: Wed, 24 Jan 1996 21:21:04 GMT
Links: << >>  << T >>  << A >>
A good introductory reference is the text, Computer Arithmetic Algorithms
written by Israel Koren and published by Prentice Hall.

The ISBN is 0-13-151952-2

The book has 2 chapters devoted specifically to Sequential Algorithms 
for Multiplication and High-Speed Multiplication Algorithms.  Included
is a discussion of Booth's Algorithm among several others.  Diagrams
of possible implementations are also given.

Bill. 
-----------------------------------------------------------------------
William Bishop, B.A.Sc.

EMAIL: wdbishop@dictator.uwaterloo.ca
URL:   http://www.pads.uwaterloo.ca/~wdbishop/
-----------------------------------------------------------------------


Article: 2693
Subject: Re: HowTo access a SRAM with a XC4000
From: "Steve Knapp (Xilinx, Inc.)" <stevek>
Date: 24 Jan 1996 21:30:46 GMT
Links: << >>  << T >>  << A >>
The concept seems feasible.  A few questions though:

1.  How much RAM is required?  General the XC4000E RAM is good for designs
    requiring less than 64 words of memory.  Increasing the word width does not
    significantly increase the amount memory required.

    Some example sizes:  A 32-deep memory of 16-bit words consumes 32 XC4000E
    logic blocks.  A 64-deep memory of 16-bit words consumes 80 logic blocks
    (64 for the RAM, and 16 for bank select and output multiplexing).

2.  Would you prefer a FIFO to a R/W RAM.  Both are possible in XC4000E.

3.  How fast does it need to be?

You should use the newer XC4000E family instead of the older XC4000.  Both are
pin compatible.  However, the XC4000E has edge-triggered (synchronous) RAM.
The actual write operation happens on a clock edge, just like a register.  This
simplifies overall system timing.  The XC4000 only supported level-sensitive
RAM, which required more careful design.

Also, the XC4000E supports both single-port and dual-port RAM.  Both are useful
for building FIFOs.  Dual-port helps to build very high performance FIFOs, with
simultaneous access to both read and write data.

I have not used ABEL for RAM-based design.  Generally, it's best to mix in
some schematics for special features like RAM, etc.  The Xilinx software allows
you to mix schematics and ABEL in the same design.

Philipp Georg <pg@mpik-tueb.mpg.de> wrote:
>I'm trying to interface a CCD-Chip to a microcontroller using
>a XC4000. To store the incoming pixeldata I need to R/W a SRAM with the
>FPGA. What I would like to know is if this is in general possible and
>wich problems could arise in such a design. Also, if someone tried
>something similar before, and could provide some sample code written in
>ABEL I would be really glad - Thanx.
>
>Philipp Georg
>-- 
>Max-Planck-Institut
>fuer biologische Kybernetik 
>E-Mail: pg@mpik-tueb.mpg.de
>http://www.mpik-tueb.mpg.de/

-- 
=====================================================================
   _
  / /\/  Steven K. Knapp               E-mail:  stevek@xilinx.com 
  \ \    Corporate Applications Mgr.      Tel:  1-408-879-5172 
  / /    Xilinx, Inc.                     Fax:  1-408-879-4442
  \_\/\  2100 Logic Drive                 Web:  http://www.xilinx.com
         San Jose, CA 95124

=====================================================================



Article: 2694
Subject: Re: Qn on XC3030 and XC3164 'Divide By Two'
From: pac1@waikato.ac.nz
Date: 25 Jan 96 10:49:48 +1300
Links: << >>  << T >>  << A >>



In article <1996Jan25.084711.42119@waikato.ac.nz>, pac1@waikato.ac.nz writes:
> 
> Qn on XC3030 and XC3164 Problems/Tricks:
> 
> As part of FPGA designs in the past I've made simple divide by two cells using
> flipflops with the XC3030. As expected they work - not much to it.
> 
> Now I'm using a XC3164 and can't even get a divided by two cell working.  I can
> do other things like take the inputed signal and AND gate it with another input
> then send it to an output pin - this works OK.  But when I try to just divide
> it by two (I've tried a couple of ways to do this including using a macro
> C2BP.mac) it won't work.
> 
> I'm using Xact5.1 and enter my design directly to the LCA.
> 
> Should I do something different with the XC3164 to what I did with the XC3030?
> 
> 
> 



Let me answer my own question :

The short story is that although Xact did not give me an error message the 
whole lca was not downloaded to the PGA consequently pert of it worked but the
flipflops did not.

Using the MakeBits "AlignedLengthCount" option which sens extra clock cycles to
the PGA it was able to download the whole bitstream and it worked correctly!

Regards, Peter Cossey



Article: 2695
Subject: Re: XILINX XACT 6.0.0 Tools flaky
From: gah@u.washington.edu (G. Herrmannsfeldt)
Date: 24 Jan 1996 22:19:27 GMT
Links: << >>  << T >>  << A >>
Probably the router accesses memory in a pattern that no dynamic
memory system can survive.

If you really want dynamic memory, try it under OS/2 or WinOS/2, which
allocates virtual XMS.  But I don't think you will like it.

For the price of a 4025 you can afford lots of DRAM.

-- glen


Article: 2696
Subject: Logic Designer & Digital Designer Needs
From: Sylvia Reyes <sylvia@toner.com>
Date: 24 Jan 1996 23:43:32 GMT
Links: << >>  << T >>  << A >>
Toner Corporation currently seeking:


Logic Designer, and a Digital Designer for positions in 
California.

Logic Designer

Skills req:  ASIC/DSP/ASSEMBLY:  EXPIRIENCE DESIGNING SEMI 
CUSTOM APPLICATIONS TO IMPLEMENT LOGIC DSEIGN ON CIRCUIT FOR 
TELECOMUNICATIONS INDUSTRY. EXPIRIENCE CODING EMBEDDED 
PROCESSORS.

Term:  Contract/Perm
Rate:  Negotiable
Contact :  Sylvia Reyes
Phone:     714-253-3050
Fax:       714-253-3047
Email:     sylvia@toner.com



Digital Designer

Skills req:  VHDL:  COMPILER DEVELOPER IN A DIGITAL SIMULATION 
ENVIROMENT.  REAL IMPLEMENTATION EXPIRIENCE IN COMPILER DESIGN. 
CURRENTLY DOING PRODUCTION IN A MS WINDOWS ENVIROMENT.



Perametors:  same as above


For more information please call/email Sylvia Reyes at the 
above number/address.



Article: 2697
Subject: VHDL Microcontroller Model
From: agijohnu@aol.com (AGIJohnU)
Date: 25 Jan 1996 00:20:42 -0500
Links: << >>  << T >>  << A >>
     I'm searching for companies that supply synthesizable VHDL models for
off-the-shelf microcontrollers (ie. 8051, 68HC11, 68HC16).  The
microcontroller would be synthesized and integrated into a custom ASIC. 
Any leads/contacts would be appreciated.  Please send email to
john.ukura@guidant.com.  Thanks for the help!


Article: 2698
Subject: Re: XILINX XACT 6.0.0 Tools flaky
From: wdcox@ix.netcom.com(Bill Cox )
Date: 25 Jan 1996 07:52:14 GMT
Links: << >>  << T >>  << A >>
You wrote: 
>
>Probably the router accesses memory in a pattern that no dynamic
>memory system can survive.
>
>If you really want dynamic memory, try it under OS/2 or WinOS/2, which
>allocates virtual XMS.  But I don't think you will like it.
>
>For the price of a 4025 you can afford lots of DRAM.
>
>-- glen

Your theory that poor locality of data access during FPGA place and
route would cause swap file thrashing is well founded.  However, for
reasons I don't fully understand, place and route tools do not thrash
the swap file.

I often run several native Win32s place and route jobs at the same time
under Windows NT, and the disk still doesn't grind.  Also, four jobs
running in parallel only take a little longer than four jobs one at a
time.

I think a proper port to Win32s or Win95 would allow less memory to be
used, at the expense of more disk space.

Bill Cox
cox@qlogic.com


Article: 2699
Subject: Re: HowTo access a SRAM with a XC4000
From: Peter Siegrist <sigi>
Date: 25 Jan 1996 10:17:26 GMT
Links: << >>  << T >>  << A >>
Ja es ist moeglich
Ich steuere mit meine 4010 exteren SRAM 25ns, DUAL_Port_RAM 25ns
und die Interen RAM's ca.20ns
Prob. gibt es nur bei den Internen da aus dem Takt die neg. Flanke fuer RW
generiert werden muss. Pro Clk Read und Write.
Toolchain
VHDL - Synopsis - FPGA Compiler - Xilinx 


Gruessli Peter

-- 
--------------------------------------------------------------------------------
Peter Siegrist         Phone: +41 1 465-3556
Alcatel STR AG           FAX: +41 1 465-3101
Friesenbergstr.75
CH-8055 Zuerich
Switzerland
internet: peter.siegrist@alcatel.ch
X.400: 	C=ch; A=400net; P=alcanet;O=alcatel; OU=strh1;S=siegrist;G=peter





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