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Messages from 3625

Article: 3625
Subject: Re: Problems with ORCA c40 FPGAs
From: wen-king@myri.com (Wen-King Su)
Date: 4 Jul 1996 22:02:17 -0700
Links: << >>  << T >>  << A >>
In a previous article kh@pvimage.com (Kevin Harney) writes:
>
<We have been using c40 ORCAs in an image recognition product, and have
>been having problems with everything from the place place and route tools, 
<to the parts not meeting spec. If you have had either a positive or a negative
>experience with the ATT ORCA chips, please share your story with me.
<I can be reached at:

Orca has always exceeded my expectation in my designs.  If you define the
location of every signal pin in advance, pay close attention to how
registered outputs are grouped.  A group of as many as 4 adjacent pads
are assocated with the same PFU, and there are strict restrictions on the
independence of the registers in each PFU.  If the register modes of a
group of such a group of 4 adjacent pins are not compatible (or even if
they are, but the mapper fails to recognize that because they are not
identical), then mapper will place the registers in different PFUs resulting
in severe delay penality for some signals. Furthermore, even if the modes
match, you may have to use "NOMERGE" at the input of the registers. If the
register is sucked into the PFU block containing the function to its D
input, and that function is too complex to share with the input functions
of the other three registers, then the mapper will place it in separate
PFUs as well. The NOMERGE attribute is to prevent the register from being
sucked into the same logic block as its input function. 
Article: 3626
Subject: RE: Sanity check for 100K gate DSP FPGA project
From: gratz@ite.inf.tu-dresden.de (Achim Gratz)
Date: 5 Jul 1996 09:14:02 +0200
Links: << >>  << T >>  << A >>
>>>>> "Jack" == Jack Ogawa <jacko@Altera.COM> writes:

    Jack> To obtain a copy of a kit, please contact 800-800-3753, hit
    Jack> 0 for the operator, and ask for extension 7144 and request a
    Jack> copy of the DSP design kit.

What do I have to tell our distributor here in Europe to get a kit?
If they don't have it, what would be the non-800 number to call in the
U.S.?


-- 
Achim Gratz.

--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW:    http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 4575 - 325
Article: 3627
Subject: Re: INDUSTRY GADFLY "Why I Hate Wally"
From: artm@eskimo.com (Art Marriott)
Date: Fri, 5 Jul 1996 08:44:48 GMT
Links: << >>  << T >>  << A >>
In article <8r4bNGAoPW2xEwIv@vizef.demon.co.uk> Steven Bird <steve@vizef.demon.co.uk> writes:
>>
>
>I have been 'beaten' over the head (almost literally) by engineering
>managers claiming/stating that if they shipped their electronic products
>with as many bugs as the EDA software they use, they would go out of
>business overnight. Probably true, but this is partly due to a
>fundimental difference between sw/hw. When you look at hardware products
>they tend to follow the theme of identifying a market niche/requirement,
>spec the product and then design and manufacture it and then sell it
>whilst the window is open.

An awful lot of products (maybe even a majority) are a combination of
hardware and software.  I used to work for a medical-products company
where almost all the products used embedded processors.  If a piece
of life support equipment fails and somebody dies, it's simply not
acceptable to say, "Oh, that's a bug.  We'll catch it in the next
release."

The immediate result of an EDA tool not working is, admittedly, not
quite as severe, except of course the poor soul who bought it and
now has to work with it might *wish* he or she was dead.
>
>Software products are *completely* different. Successive generations of
>a software simulator are not re-writes, you take whats there and add new
>functions (benifits, of course, not features). You now have a got a
>tiger by the proverbials (I mean tail!). It is unrealistic for the
>original product architects to be able to predict the future
>requirements of the tool (say 5-10 years out) when laying down the
>architecture. So as time progresses the accomodation of new hardware
>design practices becomes more and more difficult *BUT* starting from
>scratch could involve huge (>50 man years) amounts of time to start with
>new code. 

Fine.  And if said code is re-used and worked over for several years,
unless it was a mess of poorly written, inconprehensible dreck to begin
with, it should be progressively improved and debugged.

>
>As for Frameworks, from a vendors point of view they offer little in
>terms of sales revenue and consume a considerable amount of engineering
>resource. Not a defense, but a reason...

Furthermore, from a user's point of view a fremework can be inconvenient
because it's based on the vendor's notion about how you should be designing.
>

_______________________________________________________________________________
                                       |
        AXENHAMMER SYSTEMS             |        Arthur R. Marriott
      --Applied Technology--           |        artm@eskimo.com
                                       |        (206) 522-8606
                                       |
_______________________________________|_______________________________________

	If we're not supposed to see boobs exposed on television,
		I guess they're going to have to pull the plug on C-SPAN...
_______________________________________________________________________________

Article: 3628
Subject: Re: LCA to Schematic
From: ft63@dial.pipex.com (Peter)
Date: Fri, 05 Jul 1996 12:16:21 GMT
Links: << >>  << T >>  << A >>


>Yes it is. However, if you don't have Viewgen (or even if you do), 
>there's a very neat low-cost product called SmartViewer that brings 
>up your .xnf file in one window, and generates schematics in another 
>as you probe signals or blocks in the .xnf. By clicking on the .xnf, 
>you can ask questions like "show me all the logic between these two 
>points" or "show me everything upstream of this point". It's a 
>useful tool, and also supports PALASM-type input.

Do you mean it can generate a logic schematic from a PALASM file? That
would be very useful. Where is it, and (dare I ask) how much is it?
$5000?? :)

Peter.
Article: 3629
Subject: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
From: baynes@ukpsshp1.serigate.philips.nl (Stephen Baynes)
Date: Fri, 5 Jul 1996 12:28:18 GMT
Links: << >>  << T >>  << A >>
Peter (ft63@dial.pipex.com) wrote:
: How do you do an all-digital ADC??

With switched current circuits you can do it on a pure digital process.
With switched capacitor circuits you can do it on a digital process with
some analog features. [Good resistors and capacitors.]

--
Stephen Baynes                              baynes@ukpsshp1.serigate.philips.nl
Philips Semiconductors Ltd
Southampton                                 My views are my own.
United Kingdom
 Are you using ISO8859-1? Do you see  as copyright,  as division and  as 1/2?
Article: 3630
Subject: Needed: Hardware Design Engineer
From: Tom Brown <tbrown@interlog.com>
Date: Fri, 05 Jul 1996 10:47:21 -0400
Links: << >>  << T >>  << A >>
We search for IT people in Toronto, Ontario, Canada.

We are seeking a Hardware Design Engineer for our client
company located in Toronto.

The candidate will have experience with:

Microprocessor design interface.
FPGA design
PCI and ISA Bus Design

Salary negotiable. CAN$50+

Can someone help us ?

--------------------------------------------
Tom Brown
The Roberts Group   www.interlog.com/~tbrown
tbrown@interlog.com
Article: 3631
Subject: FPGA vs CPLD
From: Marc Palmarini <amphi_t@acica.com>
Date: Fri, 5 Jul 1996 16:40:40 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm currently working on a project wich involves very-high speed clock rate.  Over the 100 MHz.
We're considering CPLD and/or FPGA.  From what I can see, and have been informed by several compagnies.
CPLD offer less complexity, but more speed.  Is this right ???  Also, I'd like to know if anybody
has had to work with different brand of CPLD/FPGA.  We've been looking at two brands, first there is
the CYPRESS line, and then there's the the QuickLogic line (any comment/suggestion).  Are there any other
lines that works at a higher than 100 MHz clock.  Typically our project needs to access RAM (Burst Technique)
with acces to a peripheral (LCD Interface).  Wich will need to be able to calculate an Adress/Data from an
(x,y) pixel position.  That is about all the job for the PCLD/FPGA.  I need at the very least 64 I/O line.

	Thanks in advance for any comments and/or suggestions.

-- 
============================================================
Tel:(418)-871-8977                      Marc Palmarini
Fax:(418)-871-9021                      ATI International
                                        
E-Mail:amphi_t@acica.com
Article: 3632
Subject: Re: LCA to Schematic
From: David Pashley <david@fpga.demon.co.uk>
Date: Fri, 05 Jul 96 17:24:28 GMT
Links: << >>  << T >>  << A >>
In article <31dcd965.1823125@news.dial.pipex.com>
           ft63@dial.pipex.com "Peter" writes:

"
"
">Yes it is. However, if you don't have Viewgen (or even if you do), 
">there's a very neat low-cost product called SmartViewer that brings 
">up your .xnf file in one window, and generates schematics in another 
">as you probe signals or blocks in the .xnf. By clicking on the .xnf, 
">you can ask questions like "show me all the logic between these two 
">points" or "show me everything upstream of this point". It's a 
">useful tool, and also supports PALASM-type input.
"
"Do you mean it can generate a logic schematic from a PALASM file? That
"would be very useful. Where is it, and (dare I ask) how much is it?
"$5000?? :)
"
"Peter.
"
Take a look at http://www.cina.com

David

Article: 3633
Subject: RE: Sanity check for 100K gate DSP FPGA project
From: David Pashley <david@fpga.demon.co.uk>
Date: Fri, 05 Jul 96 17:45:10 GMT
Links: << >>  << T >>  << A >>
It's a shame we're not in comp.lang.vhdl with this thread, because 
this is a salutory example of how you have to sometimes think 
structurally rather than behaviorally to get a good FPGA design. 
Synthesis is not always the answer for large designs.

The implementation of fast arithmetic of this sort in FPGAs requires 
very architecture-specific design, which, as other posters have 
correctly pointed out, is best achieved by using the hand-crafted 
macros offered by the vendors.

The best synthesis tools I've seen will implement a multiplier as a 
full-adder array, automatically using the carry chains in 
architectures such as Xilinx XC4000 or Altera FLEX8K. That's fine 
for a 4-bit multiplier, but the bigger array, the more levels of 
logic, and the slower it goes. If latency isn't a problem, you can 
add pipelining. By the time you get to 16 bits you may want to look 
at a different approach. 

In addition to the advice already posted, Lucent publish a paper on an 
add-pass-shift method that looks promising in their ORCA devices, 
and the Altera FLEX8K apps handbook has a lot of useful stuff 
including Booth multipliers.

The fundamental problem is that you're trying to implement a wide 
function in narrow FPGA logic blocks. In some cases the answer is to 
use CPLD devices which are much better suited to this situation. 

Devices like this (e.g. AMD MACH, Altera MAX) can implement these 
wide arithmetic functions directly from synthesis without much 
problem, although you may be looking at a multiple-device solution.

David Pashley

Article: 3634
Subject: Looking for a PCI bus model
From: dando@phish.nether.net (Mann`y)
Date: 5 Jul 1996 18:04:22 GMT
Links: << >>  << T >>  << A >>
Hello All:
   I am looking for a PCI bus model in VHDL or Verilog with proper
documentation for the various cycles. Any pointers will be OK for
me to find out.
  Thanks,
Manish
Article: 3635
Subject: size of fpga
From: ploog <ploog@e-technik.uni-rostock.de>
Date: Fri, 05 Jul 1996 15:56:54 -0400
Links: << >>  << T >>  << A >>
-- 


Hey folks,
I want to break down my design into a fpga. By starting design_analyzer
I've to tell him what libraries he should use. But who do I know before
compilation if the choosen part of the family will have the right size?
Or, the other way round: What error messages are generated if the design 
doesn't fit?
Any hints? Many thanks...

Hagen











====================================================================

EMail: mailto:ploog@baltic.e-technik.uni-rostock.de
www:   http://www-md.e-technik.uni-rostock.de/~ploog/ploog.htm
University of Rostock                        Tel.: (+49 381) 4983534
Department of Electrical Engineering         Fax.: (+49 381) 4981126
Institute of Applied Microelectronics and Computer Science
Richard-Wagner Str. 31
18119 Rostock-Warnemuende 
Germany
Article: 3636
Subject: Re: size of fpga
From: espsys@aol.com (ESPSys)
Date: 5 Jul 1996 16:11:11 -0400
Links: << >>  << T >>  << A >>
Hagen:

If you are using the Xilinx XACT fitting software, the error log file will
tell you that it won't fit in the particular device that you've chosen. 
However, it will give you suggestions as to which Xilinx devices it WILL
fit into.  So in your case, you can pick out the device after you've done
the logic design.  Just make sure you don't commit to a particular
footprint for your printed circuit board too soon!  (Unless you've already
determined your i/o for the design and you know the number of pins won't
have to change).

Also, by doing some rough estimates of logic complexity (how many ff's per
state machine, size of RAM or ROM needed, quantity and size of registers,
etc.) you should be able to get close to the size of FPGA you need. 
Always be conservative in your estimates.

Hope that helps,

Ed.
espsys@aol.com
Article: 3637
Subject: Motorola 68000 Chips
From: ins@ins-group.com (ins)
Date: Fri, 05 Jul 1996 20:42:41 GMT
Links: << >>  << T >>  << A >>
I am trying to locate hardware engineers with experience of Motorola
68000 chipsets, particularly in an ISDN development environment,
working in Europe. If you are such a person, please can you contact me
via email at lisad@ins-group.com. Alternatively, if anybody can
suggest a better news group where I could find such people, please let
me know.

Many thanks

Lisa		

Article: 3638
Subject: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
From: ft63@dial.pipex.com (Peter)
Date: Sat, 06 Jul 1996 07:35:08 GMT
Links: << >>  << T >>  << A >>


>With switched current circuits you can do it on a pure digital process.
>With switched capacitor circuits you can do it on a digital process with
>some analog features. [Good resistors and capacitors.]

Plus a comparator.

And with "good resistors" and a comparator you could do an ADC as
well, using just a successive approximation register as the only
logic. A switched cap ADC is just that, instead of resistors it uses
caps.

I think someone is pulling our leg here, unless this "model" is a
freebie, or unless it contains the pretty complex algorithm used to
self-calibrate the switched-cap ADCs.

Peter.
Article: 3639
Subject: Re: size of fpga
From: eteam@aracnet.com (bob elkind)
Date: Sat, 6 Jul 1996 18:35:37 +0100
Links: << >>  << T >>  << A >>
Ed's advice is very appropriate.

At the risk of seeming to patronize, I'll add the following
generalisation:

The problem of properly sizing an FPGA design is very much like the
problem of sizing a circuit board design.

1. It's very much easier to do with greater accuracy and predictability
if this isn't your first design for this problem, and/or you're familiar
with the technology.

2.  If you don't have a low-risk design, you'll either be very
conservative in your estimates (re: pins, area, power, etc.), or you
can be very conservative in your schedule (i.e. do a first cut at the
entire design, and see how big it really turns out before committing
to a certain size).

We can go on and on with this, but you catch my drift.  The problem
and blessing of FPGA design is that you don't *have* to (rather than
*should*) do most of the design until the board is already committed.

If you have the time/cost flexibility, stick in a bigger/faster
FPGA than what you could possibly use.  The extra space may turn into
additional features or bug fixes, even after first product release,
in which case you'll be a hero because the improvements were made at
no further increase in the product cost (see Dilbert for references
on how to be a project hero to management!).

One of the dynamics of FPGA design is that you can count on the
part cost dropping dramatically over the first year of the product's
life (usually!).

Any time you push the limits of any technology; either in size, speed,
power, cost, or whatever; there is an engineering cost that usually
shows up as added development time.  For some projects, the additional
development time is crucial for a lowest possible cost design.  For
some projects, exactly the opposite is true;  the additional cost of
a larger than "necessary" FPGA is far outweighed by the cost of
the lost opportunity for developing new products and/or capabilities,
or in lost time to market.

As I said before, there are parallels between board design/sizing
and FPGA design/sizing.  And your mileage *will* vary.

Bob Elkind

**************************************************************************
Bob Elkind                mailto:eteam@aracnet.com            CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************
Article: 3640
Subject: why? internal error in VSS when simulting
From: flxchen@diig.dlink.com.tw (Felix K.C. CHEN)
Date: Sun, 7 Jul 1996 09:07:29 +800
Links: << >>  << T >>  << A >>
Dear Friends,

I use Synopsys's VSS expert v.33b to simulate the ALTERA's
FLEX10K VHDL output file (post-route) in the test bench.  This
test bench is identical to the one I used in function simulation.
In short, these two simulation activities differ from each
other only in the UUT (unit under test).  One is modeled with
behavioral VHDL, and the other is modeled with primitive-gate
structural VHDL.  Since ALTERA's MAX+PLUSII embedds timing
parameters inside the structural VHDL.

However, I get very serious internal error causing the
halt of VSS when I simulate the post-route test bench
with the very first run command.  (The patterns is
identical to the one I used in function simulation)

** internal error: vhdlsim:
Please Report (No attributes on signal /T_BENCH/TO_SW/ESWCLK)
FAULT CONTEXT
      program: 'vhdlsim'
      release: '3.3b'
      Architecture: 'sparc'
      phase: 'Run-time'
      last UI Command: run 200
      simulation time = 0ps
FAULT ID:
'2304524 374576 454228 323452 324296 79012 3049100 3046720 300676 8300'

Have any of you encountered similar troubles before?  I need
help.

Regards,

Felix K.C. CHEN
-- 
---------------------------------
Felix, Kuan-chih CHEN ( a )
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw

Machines and tools are only as
good as the people who use it.
---------------------------------
Article: 3641
Subject: RE: 100k gate DSP
From: stuart_clubb@bytech.win-uk.net (STUART CLUBB)
Date: Sun, 07 Jul 1996 03:00:00 GMT
Links: << >>  << T >>  << A >>

Dave Decker's sanity check for big Xilinx DSP project had a few Q's

M(>Would VHDL etc. make this a piece of cake?
No, but perhaps less stressful than schematics!

M(>Is there another chip family/tool set intended for DSP designs, that
M(>would make all this easier?
Not necessarily, but Lucent Technologies ORCA 2CxxA series may be of interest.
See below.

M(>General purpose multipliers, if they existed, would be useless.
M(>Besides being wasteful of CLBs, in the extreme, a design using them
M(>would not even fit in the 5215 and would be slower.

With the carry initialisation, and two LE's per bit for an adder, 5200 series
is not as dense as others - either 4000(E) (EX) (EXX?), FLEX10K/8K, ORCA, etc.

Also in a multi-chip implementation, what about clk2q and input setup times
for chip to chip comms?

I've done a 16x16 unsigned multiply in an ORCA 2C06-3S208 (6K gates - $59
part. Yes that is US Dollars, UK pricing. If you get them cheaper, or pay
more, let me know)

With a new multiplier & multiplicand every clock cycle. It runs at 33MHz with 
only a 4 clock cycle latency for pipelining.

Lucents new 0.35 m 2CxxA series has a multiplier mode, meaning that an 8x8
mpy requires only 16 PFU's (about 7% of a 10K gate part) a 12x12 would need
around 36 PFU's, but may need piping to get the data rate up, depending on the
speed grade. Even a 16x16 mpy will take only 64 PFU's which is pretty compact.

For large signed multipliers, a modified Booth (triplet) algorithm can be used
in most architectures to reduce pipeline depth and reduce
multiplier/multiplicand pipeline delays etc. The break-even width is difficult
to judge though.

Lucent are planning a DSP designers kit, but I have no firm details at
present.

Honesty time...
I'm a disti FAE, supporting Lucent. Read into this what you will.

CHALLENGE...
What's the most dense, and fastest implementation possible of a 16x16 unsigned
multiplier? ie, how small a part can you fit it into, and how fast will it
run. I'd be interested to know, as math acceleration/image processing was a
big part of my life pre-FAE days.


=========================================
Stuart Clubb, Field Applications Engineer
Eurodis Bytech Limited
Direct Line: (+44) 1256 602578
Facsimile  : (+44) 1256 707162
E-mail : STUART_CLUBB@bytech.win-uk.net
=========================================
---
 * PowerAccess 1.08 Choosy modemers choose GIF


Article: 3642
Subject: RE: Best HDL lang.
From: stuart_clubb@bytech.win-uk.net (STUART CLUBB)
Date: Sun, 07 Jul 1996 03:00:00 GMT
Links: << >>  << T >>  << A >>

DJ>I'm programming the XILINX-FPGA for two years with the schematic entry 
DJ>tool. Now, I want do that with a HDL language.
DJ>So my questions are:
DJ>- Which is the best HDL language?

Verilog & VHDL. Try them both and see which you like. Most 
synthesis packages support both these days. IMHO I wouldn't advise going 
with vendor specific HDL's as these are just going to tie you in with one 
vendor. Never mind the fact that a CV with real Verilog or VHDL experience, 
possibly makes you more marketable in the future.

DJ>- Is there a cheap Demo-Tool, I can learn the language?

Synplicity do an eval copy of Synplify (free). The editor seems pretty cool 
for the beginner, as it annotates mistakes, and colour keys everything.



=========================================
Stuart Clubb, Field Applications Engineer
Eurodis Bytech Limited
Direct Line: (+44) 1256 602578
Facsimile  : (+44) 1256 707162
E-mail : STUART_CLUBB@bytech.win-uk.net
=========================================
---
 * PowerAccess 1.08 OS/2    That's half an operating system...?


Article: 3643
Subject: Re: PCI compliance
From: stuart_clubb@bytech.win-uk.net (STUART CLUBB)
Date: Sun, 07 Jul 1996 03:00:00 GMT
Links: << >>  << T >>  << A >>

Lucent Technologies do a complete HDL PCI target for ORCA. Good 
documentation etc. etc.


=========================================
Stuart Clubb, Field Applications Engineer
Eurodis Bytech Limited
Direct Line: (+44) 1256 602578
Facsimile  : (+44) 1256 707162
E-mail : STUART_CLUBB@bytech.win-uk.net
=========================================
---
 * PowerAccess 1.08 Took an hour to bury the cat. Silly thing kept moving.


Article: 3644
Subject: Re: FPGA Companies
From: stuart_clubb@bytech.win-uk.net (STUART CLUBB)
Date: Sun, 07 Jul 1996 03:00:00 GMT
Links: << >>  << T >>  << A >>

J(>: Altera's (formerly Intel's) FLEX family is flash based.
J(>
J(>We were looking at using the Altera flash-based FPGAs for some 
J(>small projects here.  Rather than wire a bunch of discrete components
J(>together, we want to put all the logic on a single chip (it's not too
J(>involved).  We're absolute newbies with regard to FPGAs;
J(>are there any comments, good or bad, about these (Altera) FPGAs?

One of my customers told me that the price of these devices is actually 
going up! In an industry where everyone wants to tell you how cheap they 
will be six months down the line, if only you would design in today, this 
seems a bit strange. What's up, isn't Altera making enough money?

Those things aside, the architecture is great, why Intel got rid of it I 
don't know. Down-side is the cost per gate, but you pays your money and 
takes your choice.

Regards
Stuart

=========================================
Stuart Clubb, Field Applications Engineer
Eurodis Bytech Limited
Direct Line: (+44) 1256 602578
Facsimile  : (+44) 1256 707162
E-mail : STUART_CLUBB@bytech.win-uk.net
=========================================
---
 * PowerAccess 1.08 Never put off till tomorrow what you can ignore entirely.


Article: 3645
Subject: emulation software
From: sci-rjc2@jcu.edu.au (Robyn Cheyne)
Date: 7 Jul 96 12:23:01 GMT
Links: << >>  << T >>  << A >>
Hi,

I am looking for a simple emulation software system to help a
feasibility analysis of building a prototype board.

I have limited CAD experience, so any assistance would be greatly
appreciated.

Thanks,

Robyn Cheyne

email me at sci-rjc2@jcu.edu.au
--

	 ,\/~~~\_                            _/~~~~\
	 |  ---, `\_    ___,-------~~\__  /~' ,,''  |
	 | `~`, ',,\`-~~--_____    ---  - /, ,--/ '/'
Article: 3646
Subject: Re: FPGA Companies
From: eric@wolf359.exile.org (Eric Edwards)
Date: Sun, 07 Jul 1996 19:31:19 GMT
Links: << >>  << T >>  << A >>
In article <2922@bytech.win-uk.net>, STUART CLUBB writes:

> 
> J(>: Altera's (formerly Intel's) FLEX family is flash based.

> Those things aside, the architecture is great, why Intel got rid of it I 
> don't know. Down-side is the cost per gate, but you pays your money and 
> takes your choice.

As I understand it, Intel sold their entire PLD business to Altera. 
FlexLogic was only part of the deal.  

At least they sold it.  National Semiconductor just shut down their
programable logic division.

----
"..very sad life.  Probably have very sad death.  But there's symetry"
Remember the home hobbyist computer: Born 1975, died April 29, 1994

Article: 3647
Subject: Re: FPGA Companies
From: Ray Andraka <randraka@ids.net>
Date: 8 Jul 1996 15:20:34 GMT
Links: << >>  << T >>  << A >>
eric@wolf359.exile.org (Eric Edwards) wrote:

> At least they sold it.  National Semiconductor just shut down their
> programable logic division.
> 
FWIW National still has an FPGA and a group doing configurable logic 
development/research called the Softlogic Technology group.  The FPGA
is similar to the Atmel AT6002 and AT6005 (they both are descendants 
of the Concurrent architecture). Parts may be obtained through 
Seacliff technology. Contact at NSC is Al Brilliott at 408/721-4277

-Ray Andraka
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
mailto:randraka@ids.net
http://www.ids.net/~randraka/
 
The Andraka Consulting Group is a digital hardware design firm 
specializing in high performance FPGA designs.  Services include 
complete design, development, simulation, and integration of these 
devices and the surrounding circuits.  We also evaluate,troubleshoot, 
and improve existing designs. Please call or write for a free 
brochure.

Article: 3648
Subject: online w/s - evolutionary electronics
From: monty@watson.open.ac.uk (Tony Hirst)
Date: Mon, 8 Jul 1996 15:23:40 GMT
Links: << >>  << T >>  << A >>

*****************************************************************
        1st On-line Workshop on SOFT COMPUTING (WSC1)
             August 19 (Mon.) - 30 (Fri.), 1996

                  		Special Session on

      		EVOLUTIONARY ELECTRONICS
               
*****************************************************************

                    Call for Papers and 

         Invitation to take part in the Discussion
        
*****************************************************************

As part of the 1st on-line workshop on soft computing, we call for papers
for the special session on 'Evolutionary Electronics'. The session is
intended as a forum for discussing the use of evolutionary computing
techniques in electronics design and manufacturing, and the application of
reconfigurable logic as the medium for the rapid prototyping of (evolved)
digital logic designs.

The session welcomes survey  and tutorial style papers.
The areas of interest include but are not limited to :

        a. Evolving anlogue circuits
        b. Intrinsic/extrinsic evolvable hardware
        c. VLSI placement, routing and testing using evolutionary
algorithms
        d. Hardware implementations of evolutionary algorithms
        e. Evolutionary co-design
        f. Embryonics
        g. Implicit fault tolerance afforded by evolutionary design
        h. Field programmable gate arrays
       (i.  Hardware implemented neural networks)
        

The contributions can be in the form of :

     a) 6 page (max) Original paper, to be published in the workshop
        proceedings. In the case of survey or tutorial style papers 
        authors are encouraged to submit the paper in several 
        parts (such as part I and part II with the same title).     
     b) 6 page (max) paper on your already published work 
     c) YOUR PARTICIPATION in the discussion during the workshop

PLEASE NOTE: 

The DEADLINE FOR SUBMISSION of abstracts and main text is Aug. 5, 1996

WSC1 will accept  both  ORIGINAL and ALREADY PUBLISHED papers  (in
electronic form). It is intended that original papers will be published in
the conference proceedings.

Please refer to the ORIGINAL CALL FOR PAPERS below for the
submission and further details.

To submit  a paper  for the  special session, use  the same submission
procedure as for the WSC1 workshop, but, please, CLEARLY INDICATE THAT
YOUR PAPER IS FOR THE SPECIAL SESSION ON EVOLUTIONARY ELECTRONICS.

For any queries about the special session (only) 
please send email to:

    a.j.hirst@open.ac.uk

To contact the WSC1 organisers:

   http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/


==============================================================
                    ORIGINAL CALL FOR PAPERS
===============================================================

From: furuhashi@nuee.nagoya-u.ac.jp (Takeshi FURUHASHI)
Date: Tue, 4 Jun 1996 13:46:10 +0900
Subject: WSC1

 This is the preliminary CFP for the 1st Online Workshop on Soft 
Computing. This is also available on WWW. The URL is

    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/

        CALL FOR PAPERS

     The 1st Online Workshop on Soft Computing (WSC1)

         Aug. 19 (Mon) - Aug. 30 (Fri)

    On Internet (WWW (World Wide Web) ) Served by Nagoya University

 We call for your papers for online discussions using the Internet.
The purpose of this workshop is to give its attendees opportunities to
exchange informaiton and ideas on various aspects of Soft Computing
and  "save travel expenses" without having to visit foreign countries.
We aim to have ample discussion time between the authors and attendees
make them visible to everyone on the Internet.

 This is the 3rd workshop of On-line Workshop series on Internet. The 
first on-line workshop(WEC1) was held on Oct. 9 - 20, 1995. In spite 
of the very short preparation time ( 2 weeks ) for the workshop, 22 
papers were submitted and great many people visited the home page:

    http://www.bioele.nuee nagoya-u.ac.jp/wec

 Encouraged by the unprecedented repercussions, we held the second on-
line workshop(WEC2) on March 4 - 22, 1996. More people showed great 
interest into the workshop. You can still visit the home page at:

    http://www.bioele.nuee.nagoya-u.ac.jp/wec2

 The scope of the 3rd on-line workshop is expanded from those of the 
preceding workshops. We call for your papers on Soft Computing. The 
great merit of this workshop series is that you can save travel 
expenses without having to visit and attendees and make them visible 
to everyone on the Internet.

 The WSC1 will welcome original contributions. The proceedings is 
planned to be published. We all look forward to your active 
participation.

TOPICS:
 Fuzzy Logic
 Neuro - Computing
 Genetic Computing
 Probabilistic Reasoning
 Chaos Computing
 Hybrid Systems

IMPORANT DATES:
 Deadline for Submission of Abstracts and Main Text: Aug. 5, 1996
 Opening the papers to the public:                   Aug. 12, 1996
 Workshop Weeks:                                     Aug. 19-30, 1996

SUBMISSION PROCEDURE:
 Send an abstract and main text to the address below.

    mail address is : wsc@bioele.nuee.nagoya-u.ac.jp

   The abstract should be in text file. The main text should be in 
text file or in ps ( PostScript ) file. The size of the paper should 
be either A4 ( metric ) or letter size. Papers should be written in 
Times or similar font style, 10 points or larger with 2.5 cm margins 
on all four sides. If you write your paper with LaTeX, you can use 
"IEEEtran.sty" and "wscsample.tex" which is available from

    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/IEEEtran.sty
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/wscsample.tex

   Another alternative is that if you prepare a WWW page for your 
main text, please send us only the abstract and tell us the Internet 
address ( URL ), and yours will be linked to our WWW page.

   The steering committee will make your abstracts visible on the 
Internet. The home page address is:

    URL: http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/

  *Note:
    This workshop will accept papers both original and already 
published. If your paper is not original, please clarify the 
source of your paper. Your paper will not be included in the 
proceedings.

    If your paper is an original one, you need to send ps file or 
camera - ready manuscript of your main text. The paper should not 
exceed 6 pages in length. Please also send us the copyright form by 
postal mail or facsimile. The proceedings including your original 
contribution will be published. The copyright form is available 
also from

    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/copyright.ps
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/form/copyright.txt

DISCUSSION PROCEDURE:
 1. Read the abstracts.
 2. Copy the main texts ( ps files ) of interested papers.
 3. Send questions and comments to
    wsc@bioele.nuee.nagoya-u.ac.jp
 (The steering committee will send the questions to the authors and 
receive answers from the authors, and make the Q&A visible on the 
Internet.) 
 4. Read the answers from the authors on
    http://www.bioele.nuee.nagoya-u.ac.jp/wsc1/
 5. Repeat the above steps 3 and 4 until you are satisfied.

OFFICIAL LANGUAGE: English
 (Notice should be made that the main texts in ps files should not 
include any fonts other than English.)

 For further information, contact:
    Takeshi Furuhashi
    Dept. of Information Electronics
    Nagoya University,
    Furo-cho, Chikusaku
    Nagoya 464-01, Japan
    Tel. +81-52-789-2792
    Fax. +81-52-789-3166


        Paper Submission Form
Title :
Authors :
Affiliation :
Address :
Phone :
Fax :
e-mail :
Source(if your paper is already published):
Keywords :
Link(if you have a WWW home page of the paper) :
Abstract :

Article: 3649
Subject: Consultant$$Work$$Xilinx
From: David McKenna <dmckenna@dne.com>
Date: 8 Jul 1996 17:58:54 GMT
Links: << >>  << T >>  << A >>
Consultant needed immediately to Develop Static Timing Diagrams and Test 
Bench Suite for four (4) Xilinx FPGAs. VHDL experience essential.



Development Tools:
Chronology Timing Designer
Viewlogic Workview 7.1 or ProSeries 6.1
Vantage Simulator  or  ProSim
Xilinx XACT 6.0

For additional info please call or write.

David McKenna
DZyn InGaNier
phone:  (860) 265-7151 x4804
e-mail:        dmckenna@dne.com





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