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In the old days, when the XC3000 devices used a place and route program called APR, it also seemed like nets were routed in order by their name. Are you using any of the XACT-Performance (i.e. timing-driven) features in the Xilinx software? These may help guarantee your 30 ns timing requirements. You should be able to set some global parameters from XDM. -- Raymond Gaita OptiMagic Logic Design Studios > > I'd be interested to hear from anybody who has similar experiences or who on > the basis of my observations has experimented and noticed similar phenomena. >Article: 3951
This used to be on the Xilinx bulleting board. I havn't checked but it may also be available on their web site (http://www.xilinx.com). -- Raymond Gaita OptiMagic Logic Design Studios > > If so, then where is my striphex utility!! or am I > missing something!!! > Does anyone know about this. >Article: 3952
Hughes Research Laboratories has an immediate opening for a researcher to join our Embedded Real-Time Processing Project team developing special purpose, high performance, processors for embedded real-time signal and image processing. While specific duties will be matched to the skills of the team as a whole, anticipated job functions include developing special purpose processors at one or more levels of: architecture, performance modeling, HDL design, ASIC/FPGA design, digital circuit design, and board level design; developing software tools to support the design process, including runtime support software and application code for the special purpose. Additional responsibilities will include working with customers to analyze, identify and develop new research areas. Preference will be given to candidates with greater technical breadth. It is desired that candidates posses technical knowledge in several (not all) areas from the following list: € digital system design (including custom ASIC, gate array, and FPGA design) € computer architecture € digital signal and image processing € processor performance modeling € software tool development € hardware design in VHDL or Verilog € software engineering € programming in C or C++ for UNIX/WindowsNT € parallel processing Candidates should possess a M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science; a Ph.D. is preferred. In addition, candidates should possess: strong verbal and written communications skills, the ability to function effectively in a team environment; and an openness to technical challenges and learning new skills. HRL staff members are encouraged to invent, patent and publish on a regular basis. This commitment helps keep Hughes poised at the frontiers of electronics and information technology. Our ideal location, competitive salary and benefits package contribute to a work environment designed to optimize creative research. Please send your resume to: € Lynn W. Ross € Department 2DSWWW € Hughes Research Laboratories € 3011 Malibu Canyon Road, € Malibu € CA € 90265 FAX: 310-317-5651 € E-mail: lross@hrl.com. To learn more about HRL, visit our WebPage at http://www.hrl.com/ Proof of legal right to work in the United States is required. An Equal Opportunity Employer.Article: 3953
Hi,
I would like to learn the Xilinx's FPGA but I am not able to
locate books or resources to start with. Can somebody suggest
possible way(s) that I could learn it?
Artur
8.23.96
Article: 3954In article <DwLr8M.L8@cce.com>, Ed Casas writes: > But there isn't much in the way of synthesis tools for the > individual hobbyist. What I have found is: > > - Synplicity had a demo for their nice-looking VHDL synthesizer > but it doesn't do simulation. Actually, most synthesis products don't do simulation. It is expected that one uses a seperate simulator. Fortunately, low cost simulators are much easier to come by than low cost synthesis. Among Verilog simulators, there are: 1) Veriwell: Free for up to 1000 lines. $495 for the unlimited version. 2) Viper: Free for up to 750 lines. $5000 for the "real" version. 3) Silos: Free for up to 500 lines. $3000 for the full version. 4) Finsim: $995 for (I think) 2500 lines. Accolade has a free size limited VHDL simulator. I haven't used it myself, I chose Verilog at the fork in the road. > - There is a free ASIC design package called Alliance which > includes VHDL synthesis but it only runs on UNIX machines and the > VHDL subset is limited and rather unusual. It has an FPGA > compiler that produces XNF but you still need the Xilinx > place/route tools. > > - There's a free synthesizer for Xilinx 4000 series that uses 'C' > as the HDL. Again, you'd need to buy the Xilinx place/route. Xilinx conciders their bitstream format to be a trade secret. Only one company ever reverse engineered it. Xilinx bought them. > If you're willing to abandon Xilinx there are a couple of other > options: > > - Cypress sells their Warp synthesis package for $99. > Unfortunately it only targets Cypress FPGAs which are not > reprogrammable. Cypress's CY7Cxxx series of CPLD are reprogrammable and supported by the $99 Warp2 package. Unfortunately, programming the parts in the first place could be a problem. None of the <$1000 device programmers support the chips. Of course, these are CPLD's not FPGA's. > - Motorola has a free place/route tool for their FPGAs (not > Xilinx). You need something to generate the netlists first > though. Yeah. The Motorolla parts sound nice but I can't find any software support for them. No Minc, no Synplicity. I think Synario and Exempler passed them over as well. ---- "..very sad life. Probably have very sad death. But there's symetry" Remember the home hobbyist computer: Born 1975, died April 29, 1994Article: 3955
aleung@engr.ukans.edu (Artur Leung) wrote: > I would like to learn the Xilinx's FPGA but I am not able to >locate books or resources to start with. Can somebody suggest >possible way(s) that I could learn it? I simply bought the Xilinx development software with the OrCAD interface and dived right in. Within a couple of days I had my first XC4010 going with some counters and silly experiment logic. I was immediately frustrated with the clumsy GUI interface, so I found a way to do all my builds with DOS batch files. The software is a collection of DOS utilities and libraries. They seem very stable and reliable. For me, the biggest challenge was finding answers in the one-foot thick stack of poorly-indexed manuals. So far I've done ten successful XC4010 designs that are about 70% utilized. _________________________________________________________ Kirk Hobart Santa Barbara, California hobart@rain.orgArticle: 3956
>Xilinx conciders their bitstream format to be a trade secret. Only one >company ever reverse engineered it. Xilinx bought them. Did Neocad reverse-engineer the bitstream, or did they do it with Xilinx's co-operation? Peter.Article: 3957
Ignore this; testArticle: 3958
In article <321E409D.22A@erols.com>, Richard Schwarz <aaps@erols.com> wrote: [...] >I have also tried a FLEX 10k ALTERA chip >which software could not convert my VHDL tristates (ALTERA has no >internal tristates). ALTERA is still trying though (thank you ALTERA). While the Altera devices you mentioned do not have internal tri-states the software will implement tri-states with multiplexers. Would that not work for you, or would it just result in more logic than you would like? Wayne TurnerArticle: 3959
--
Sorry to post this to your newsgroup, but I had to try it!
I read this and thought, "What could I lose?"
Read through it and maybe you'll like to try it as well!
But please be honest. That is how it works.
"MAKE-MONEY-FAST"
----- Adapted article by Jody Vining (#4 below) ----------------
Want to make a few bucks? Quick, easy and cheap?
Ok ok, we have all heard this before, laughed at it, thought it was
stupid, so did I. But one day, I was bored, and wanted to see if this
thing really works, the now infamous newsgroup "make-money-fast"
routine.
And well, to my surprise, it ACTUALLY WORKED. I didn't make $50,000
like some said, but I DID make $3,200 in 1 month. Thats not bad for a
$5 investment!
So now try it, maybe you'll make less, maybe you'll make more, but its
worth a shot right?
The procedure is very simple.
STEP 1. Write your name and address on 5 separate pieces of paper with
the words "PLEASE ADD ME TO YOUR MAILING LIST". Fold a $1 note or money
order or bank draft in each of the pieces of paper and mail them to the
following five addresses:
----------------------------------------------------------
1. Sahba Zadeh, 16115 122 Pl. NE, Bothell, WA 98011, USA
2. John England, 570 Vista Ave. Palo Alto, CA 94306, USA
3. Jeannette Bidegain, 2301 Redwood Street, #1406, Las Vegas, NV
89102,USA
4. Jody Vining, 987 Shetland Ave, Winter Springs, FL, 32708
5. Mitch Whiteley, 1026 N. 510 W. Apt. 4A, Logan, UT 84341
---------------------------------------------------------------
STEP 2. Now remove the 1st name on the list, move the other 4 names up
(5 becomes 4, 4 becomes 3 etc) and put your name and address as number 5
on the list. You can do this by re-typing this article or simply editing
and re-posting it in this or another newsgroup.
STEP 3. Post your amended article to at least 200 new groups (there are
17 000 of them).
You are now in the Mail Order Investment Business and you will start
receiving $1 returns by mail within a week or two. The more newsgroups
you post to, the bigger your return will be. You may want to rent a Post
Office Box to handle the volume of mail you are likely to receive.
If you wish to remain anonymous, you can use a pseudonym such as
"The Manager" or "The Investor", but make sure your address is correct!
NOW LET ME TELL YOU WHY THIS SYSTEM WORKS!
Of every 200 postings I made, I received an average of 5 replies, YES -
ONLY 5, each with a $1 bill enclosed. You make $5 for every 200
postings WITH YOUR NAME AT NUMBER 5.
Each person who sent you $1, now also makes let's say,only 200
additional postings WITH YOUR NAME AT NUMBER 4, i.e. 1000 postings.
On average therefore, 50 people will send you $1 with your name at
number 4. You make $50.
Your 50 new agents make 200 posting each WITH YOUR NAME AT NUMBER 3
or 10 000 postings - average return 500 at $1 each is $500. They
make 200 postings each WITH YOUR NAME AT NUMBER 2 = 100 000 postings
= 5 000 returns at $1 each = $5 000.
Finally, 5 000 people make 200 postings each WITH YOUR NAME AT NUMBER 1
and you get a return of $50 000 before you name drops off the list.
AND THAT'S IF EVERYONE DOWN THE LINE ONLY MAKES 200 POSTINGS! Total
income in one cycle = $55 500.
From time to time, when your name is no longer on the list, you take
the latest posting that is appearing in the newsgroups, SEND OUT
ANOTHER $5 TO THE NAMES THAT ARE ON THE LIST, PUT YOUR NAME IN
AT NUMBER 5 AND START POSTING AGAIN. Remember, 200 postings is only
a guideline. The more you post, the greater the return.
Let's review the reasons why you should do this: THE ONLY COST FACTORS
ARE 5 STAMPS, 5 ENVELOPES, AND 5 $1 BILLS. Anyone can afford five
dollars to put into such an effortless investment with SPECTACULAR
RETURNS.
Some people have said to me "What happens if the scheme is 'played
out' and no one sends me any money"? Big deal! So you lose $5 - but
what are the chances of that happening?
Do you realise how many Internet Users there are? Do you realise how
many times this scheme can be utilised over and over again - with
COMPLETELY NEW people participating?
There are not HUNDREDS, NOT EVEN THOUSANDS, BUT HUNDREDS OF THOUSANDS
OF NEW INTERNET USERS EVERY MONTH!
Remember, read the instructions carefully and play FAIRLY...that's
the only way this will work. Get a printout so you can refer back
to this article easily.
Try to keep a list of everyone that sends you money and always keep
an eye on the newsgroup postings to make sure everyone is playing
fairly. You know where your name should be.
Article: 3960Kevin Kolb wrote: > > EDN had an article on reconfigurable computing in their 3/28/96 > issue. [stuff deleted] > It was my understanding from the article that reconfigurable > FPGA's differ from regular SRAM FPGA's and in-system programmable > CPLD's by the speed with which they can be reconfigured, [more stuff deleted] > I am a radar system engineer [the rest of the stuff deleted] The SRAM FPGAs are what has spurred the reconfigurable computing thing. The XC6200 is an attempt to improve on the relatively slow reconfiguration times of the other Xilinx SRAM FPGAs. It has a rather neat feature that lets you address the configuration SRAM sort of like a random access memory. Previous Xilinx devices used a sequential configuration program, which is/was an all or none deal. The programming times of the 3K and 4K devices run over a millisecond, where the 6200 cuts that down by an order of magnitude for full configuration and considerably less for partials. The Atmel/NSC devices have been around for a number of years and run in the 400uS for complete reconfiguration. The relatively fast reconfiguration, the ability for partial reconfiguration, and the ability for flip-flops in the design to hold state and/or continue to operate during configuration makes these devices better suited to reconfigurable computing. Reconfigurable computing in this context applies to systems which dynamically change the logic in accordance to the existing conditions in the FPGA or a control circuit. The 3K and 4K xilinx devices are also suitable for reconfigurable computing, but the reloading effects the entire device. Systems such as the SPLASH, VCC's virtual computer, and Metalithics processor have used the more familiar 3K and 4K devices quite successfully. Believe it or not, reconfigurable logic has application in radar too. I am currently involved in a design of radar equipment using Xilinx 4K in reconfigurable hardware. Stuff in there includes FIR filtering, digital quadrature oscillators, gaussian and gamma distributed noise generators, CORDIC magnituding and hardware sorting....all at 40Mhz data rates. Definitely fun work, and the best part is the rest of the world is finally starting to sit up and take notice of pipelined DSP in hardware. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randraka/ The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs. Services include complete design, development, simulation, and integration of these devices and the surrounding circuits. We also evaluate,troubleshoot, and improve existing designs. Please call or write for a free brochure or visit our web site.Article: 3961
Hello, I am using Viewdraw/Viewsim (DOS version 4.1) with QEMM7.03. I have upgraded to QEMM7.5, and find that Viewlogic crashes (reboots the PC) immediately at startup. Reverting to QEMM7.03 makes it OK again, and this is no big deal since 7.05 has only one useful feature I can see. Xilinx always used to say that one "must" run their Viewdraw etc under QEMM, and in fact they used to include QEMM, as well as the classic 3-button PC Mouse :), in the package. But I never established why QEMM was really needed. The only sort-of explanation I ever got was that only QEMM supported the inter-program communication used by the various DOS extenders used. The obvious answer (upgrading to a Windows version of all this) is not on because I have tried it, and the DOS version is far better. Peter.Article: 3962
-- I am really sorry about my SPAM. I didn't realize how wrong it was. Other's articles seemed convincing and legel, but I guess not. Please disregard posting: "I had to try it!" (delete it if your a system administrator). My mistake.Article: 3963
Hello
I have problems using MAXPLUS2 6.2 (solaris)
together with the synopsys interface when compiling for
FLEX8000 or FLEX10k families.
When reading the EDIF netlists generated by FPGA compiler
with target/link library flex8000_fpga.db / flex10k_fpga.db
I get the error "Can't find Design file 'LUT'".
I have no problems when compiling for CPLD devices.
So I think my pathes are setup right.
Thanks for any help
--
---------------------------------------------------------------
Andreas Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 3964Hi, I'm having problems with downloading a "large" design (XC4010E-PQFP160, 70% of CLB's used) When the design is almost downloaded(20blocks, 91%), windows crashes. A smaller design doesn't have this problem. Anyone having similar problems ? Thanks, Kim -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3965
Raymond Gaita (optmagic@ix.netcom.com) wrote: : Are you using any of the XACT-Performance (i.e. timing-driven) features in : the Xilinx software? I'm using PPR, and yes, I am supplying TIMESPECs. In regard to the other stuff, however, I'm afraid I posted my message before fulling exploring all the possiblities. When PPR is supplied with the same seed value for the random number generator, it produces the same results regardless of the names of the nets. ERIK.Article: 3966
In article <4vrurn$apb@rc1.vub.ac.be> tw38966@vub.ac.be (Rafiki Kim Hofmans) writes:
>I'm having problems with downloading a "large" design (XC4010E-PQFP160,
>70% of CLB's used)
>When the design is almost downloaded(20blocks, 91%), windows crashes.
>A smaller design doesn't have this problem.
>Thanks,
>Kim
Try running xchecker in a dos box.
Try exiting windows and running xchecker in DOS directly.
Try running xchecker on a different serial port (interrupt conflicts with
mouse?)
Try emailing Xilinx support hotline@xilinx.com
Good luck.
Philip
Article: 3967In article jJ4@wolf359.exile.org, eric@wolf359.exile.org (Eric Edwards) writes: > > - Motorola has a free place/route tool for their FPGAs (not > > Xilinx). You need something to generate the netlists first > > though. > > Yeah. The Motorolla parts sound nice but I can't find any software > support for them. No Minc, no Synplicity. I think Synario and Exempler > passed them over as well. Exemplar and Synopsys support Moto parts. Also, the free software includes an OrCad library if you're not interested in synthesis. ---------------------------------------------------------------------- Jeff Hunsinger jeffh@oakhill-csic.sps.mot.comArticle: 3968
Joe Buck <jbuck@synopsys.com> wrote:
>Maybe courts need third parties without an axe to grind to educate the
>judges on things like (say, in the recent EDA litigation) the modern chip
>design process, what placement and routing are, an outline of which
>algorithms are in the public research literature and what software was
>released by universities, and all the other background technical questions
>that both sides can agree to.
>
>Me? I have no idea whether Avant! ripped off Cadence or not.
Ironically, that's supposed to be the function of the "experts" they bring
into cases (but these "experts" seem to be brought in based on how they'll
influence a case; not on how objective they are.)
Anyway, concerning the Avant!/Cadence lawsuit, the general view that I
seemed to be getting from the engineers that I polled was sort of the
same view that most Americans have about various Republican/Democratic
scandals that periodically break out -- that is, both sides are "dirty"
and this is just a temporary wrinkle favoring one side. Very few people
feel that the courts actually provide justice because of how they can
be so easily skewed by hot shot lawyers that wheelbarrels full of cash
can buy. Although I don't have polling numbers, judging from the letters
I got that were anti-Cadence after the news of the Cadence/Cooper & Chyan
lawsuit broke, I'd say that the mood has gone further against Cadence
overall.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4599 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3969In article <4vrurn$apb@rc1.vub.ac.be>, tw38966@vub.ac.be (Rafiki Kim Hofmans) wrote: > I'm having problems with downloading a "large" design (XC4010E-PQFP160, > 70% of CLB's used) > Are you talking about loading a bitstream into a device, i.e. configuring it? If so, you might consider that there is no difference in file size between an empty and a full design. They all take the same number of bits. Peter Alfke, Xilinx ApplicationsArticle: 3970
>But I never established why QEMM was really needed. The only sort-of >explanation I ever got was that only QEMM supported the inter-program Me neither. you don't really need QEMM (I think), unless you load some other programs in the Upper Memory Area. If you need QEMM, you should use a utility msd to print out the upper memory area map, and exclude all unavailable locations that has been mapped to devices. PS: xdocs has some useful discussion about upper memory managers...Article: 3971
Still using schematics for FPGA design? Want to be properly equipped for your next major design project -- or for your next job? Learn VHDL fast, with the PeakVHDL Training Edition Simulator and "VHDL Made Easy". Available now from Accolade Design Automation. PeakVHDL Training Edition supports VHDL 1076-1993 features, has no design size limits and runs on Windows (95, NT or 3.1) platforms. Includes dozens of examples, Hierarchy Browser, Entity Wizard and 32-bit native-compile simulation kernel, and has an easy-to-use Windows interface. Included with the Training Edition simulator is "VHDL Made Easy" (published 1996, Prentice Hall). This book is over 400 pages of tutorials, code examples and language reference sections covering VHDL for synthesis and for test bench development. PeakVHDL Training Edition is available now from Accolade Design Automation. For details visit our Web site at http://www.acc-eda.com. We can take credit card orders via FAX to (206) 788-3768. "VHDL Made Easy" can be ordered separately for $49.95. -- -- David Pellerin (pellerin@seanet.com) -- -- Accolade Design Automation, Inc. -- 26331 NE Valley, Suite 5-120, Duvall, WA 98019 -- (800) 470-2686, (206) 788-1802, FAX (206) 788-3768 -- Visit http://www.acc-eda.com for a free PeakVHDL/PeakFPGA demo!!Article: 3972
John Cooley <jcooley@world.std.com> wrote:
>The biggest surprise came when I later compiled the 36 additional responses
>from EDA employees. This group was three times as likely (42 percent versus
>the EDA users' 13 percent) to grant Cadence's injunction. And EDA makers
>were twice as likely (53 percent vs. 27 percent) to see the courts as
>competent -- which helps explain why the EDA industry is so litigious!
This result from the survey still kind of stumps me. Why are EDA vendors
significantly more legalistic than their customers? I can't seem to figure
this one out. Any insights anyone?
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4599 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3973jcooley@world.std.com (John Cooley) writes: >>The biggest surprise came when I later compiled the 36 additional responses >>from EDA employees. This group was three times as likely (42 percent versus >>the EDA users' 13 percent) to grant Cadence's injunction. And EDA makers >>were twice as likely (53 percent vs. 27 percent) to see the courts as >>competent -- which helps explain why the EDA industry is so litigious! >This result from the survey still kind of stumps me. Why are EDA vendors >significantly more legalistic than their customers? I can't seem to figure >this one out. Any insights anyone? It's just a guess, but quite possibly the USERS think the value of the software is how much it costs to distribute, while the VENDORS of the software think the value is in what it costs to write in the first place. If you perceive high value in the sales chain, then source code is not worth fighting over. If you perceive value in the source code, then any company that even LOOKS LIKE they have their hand in the cookie jar is deemed a threat to your (or the industry's) revenue. I wonder about the "courts as competent" numbers. Precisely how was the question asked? You seem to equate granting the injunction with seeing the courts as competent... or at least you indicate that others might. Did I read that wrong? -- SRE * * * - - - - - - - - - - - - - - - * * * * Eckert Enterprises Steve Eckert eckert@netcom.com * * * * - - - - - - - - - - - - - - - * * * * ftp: 192.100.81.1 415-508-0500 fax: 415-508-0501 * * * * - - - - - - - - - - - - - - - * * * TRY THIS: echo '[q]sa[ln0=aln256%Pln256/snlbx]sb3135071790101768542287578439snlbxq'|dcArticle: 3974
Hi All, Do any of you know of a USB host interface (UHCI) design available for an FPGA (any vendor will do)? I am aware of an Actel function block that fits in a mid-size 3200DX part (but they don't say which part and the two central parts in the family are 10K and 20K gates, quite a difference). I've not seen a stand alone host interface ship (for non PCI, non intel CPU) yet. If you know of an off-the-shelf stand alone host controller with a simple CPU bus interface, please let me know. I'd also appreciate any information on approximate gate count implementations of the USB host interface. Also, does anybody know of a peripheral side USB controller other than Intel's 82930 and the impending Atmel part? Thanks, Scott
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