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Messages from 4150

Article: 4150
Subject: OrCAD schematic based multiplier for XC4000 series
From: Jason Crawford <jcrawfor@rp.csiro.au>
Date: Wed, 18 Sep 1996 23:37:35 GMT
Links: << >>  << T >>  << A >>
Hi,

Does anyone know of any web-sites that offer OrCAD based schematics of 
Xilinx macro components such as multipliers, FIR filters and the like?

I need to implement a 10-bit complex multiplier in an XC4025 and will 
possibly also need to implement some FIR filters.

Thanx in advance,
Jason.

====================================================
Jason  Crawford. B.E.(Hons 1)
Experimental Scientist.
Radio-Systems Program
CSIRO Division of Radio-Physics
phone:  +61 2 9372 4163
fax:    +61 2 9372 4490
e-mail: jcrawfor@rp.CSIRO.AU
web:    http://www.rp.csiro.au/staff/jcrawfor.html
====================================================
Article: 4151
Subject: Are there any FPGA Starter Kits?
From: ray@rucus.ru.ac.za (Ray Heasman)
Date: 19 Sep 1996 12:44:57 GMT
Links: << >>  << T >>  << A >>
Hi All,

I was just wondering - is there an equivalent of the DSP Starter Kit for
FPGA's? I would love to fiddle with something like that.

Cheerio,
Ray
--
             _/_/_/   ""\ ""\    ""\ ""\ """""""\ ""\   _/_/_/_/_/_/_/_/_/_/_/
           _/_/_/   """"\ """\  """\ ""\ ""\      """"\   _/ StarWriter  /  _/
         _/_/_/   ""\ ""\ ""\"""\""\ ""\ ""\ """\ ""\ ""\   _/    Genisys   _/
_/_/_/ _/_/_/   """"""""\ ""\ "\ ""\ ""\ ""\  ""\ """"""""\   _/            _/
 _/_/_/_/_/   ""\     ""\ ""\    ""\ ""\ """""""\ ""\     ""\   _/_/_/_/_/_/_/
   _/_/_/             Amiga - The canvas of the Gods.                













Article: 4152
Subject: Re: Are there any FPGA Starter Kits?
From: bon@elektron.ikp.physik.th-darmstadt.de (Uwe Bonnes)
Date: 19 Sep 1996 15:27:56 GMT
Links: << >>  << T >>  << A >>
Ray Heasman <ray@rucus.ru.ac.za> wrote:
: Hi All,

: I was just wondering - is there an equivalent of the DSP Starter Kit for
: FPGA's? I would love to fiddle with something like that.

Try http://www.pmel.com/softprod.html


(and cut down your sig please)
-- 
Uwe Bonnes                bon@elektron.ikp.physik.th-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 4153
Subject: Re: Good starting point to learn FPGA for hobbyist?
From: Ed Barrett <ed.barrett@worldnet.att.net>
Date: Thu, 19 Sep 1996 08:34:49 -0700
Links: << >>  << T >>  << A >>
Give the Lattice CPLD parts a try. They offer a free CD with schematic 
capture, ABEL code entry and a functional simulator. They have a large 
family of simple to use isp (in sytem programmable - and reprogrammable) 
parts. These are programmed with a simple cable from a PC and some 
windows based software they have. There is also a starter kit that 
includes the above software, design tool, cable and samples for $495.

Contact them at www.lattoicesemi.com

Ed

Peter wrote:
> 
> >: I've worked with PAL's and GAL's before, but never FPGA's.  I would
> >: like to learn how to use them for hobbyist-type electronic projects.
> 
> I missed the original post, but I would recommend only RAM-based FPGAs
> for this requirement. OTP parts will be too much hassle. Especially if
> one is learning VHDL (or some dialect of) at the same time.
> 
> Furthermore, the cost of place-route software will probably rule out
> Xilinx, which is a pity because they do good parts.
> 
> Peter.
Article: 4154
Subject: Re: 256K EEPROM
From: Mark Shand <shand@acm.org>
Date: Thu, 19 Sep 1996 09:23:31 -0700
Links: << >>  << T >>  << A >>
Martin Mason and Peter Alfke expressed various opinions
about the Xilinx download cable vs Atmel EEPROMs.

I'm not too keen on the download cable solution since I
often "do development" on systems that are half way
across the world from me.

I have built a board that uses both XC17XXX and ATMEL
AT17CXXX parts.  I'm relatively happy with the result.
My biggest gripe is that we are still waiting for the
17C256 part.  I'm not sure where the disconnect came
from but this part has taken much longer to come out
than we expected.  I have still not actually seen one.
We are rumoured to get some 1 October 1996.  (I specify
the year because given the delays we've had ...).

Anyway the ATMELs can be daisy chained so we have been
able to get by with a pair of AT17C128 parts.

We have been able to write our own config code for the atmel
part and can reload it "in system" however here's another
caveat.  RESET polarity is programmable, but setting it
in system is tricky especially if you need to daisy chain.
If you want to avoid a trip to the PROM
programmer before you stuff each board you might want to design
your board to use ATMELs factory shipped default polarity.
Of course this is the opposite to what you want to use
with the newer xilinx parts so I use and external inverter.

I said I use a XC17256 too.  Why?  It is a failsafe ROM.
Under control of a jumper my board can be loaded from a
socketed Xilinx part in cases where the board is fresh
from stuffing or where the programming of the ATMEL got
screwed up by say a power outage (I am afterall composing
this message from my office in downtown Palo Alto where we've
had 4 power outages this summer!).

For those who care, you can see photos
of the board (in living colour) at:

http://www.research.digital.com/SRC/pamette/PPamPhotos.html

The Xilinx + Atmel ROM are in the top left corner.
The second daisy chained Atmel is lurking on the backside,
it will go away once we get the AT17C256 parts.

Mark Shand
shand@pa.dec.com
Article: 4155
Subject: Re: manchester clock recovery
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 19 Sep 1996 11:59:48 -0700
Links: << >>  << T >>  << A >>
The delay element looks nice on paper, but its practical implementation 
is more complicated than the clock recovery for Manchester code.

BTW, I have faxed the Xilinx schematic to four requestors. That's a 
better response than I got when I first mentioned it to this newsgroup a 
year ago.
Peter Alfke, Xilinx Applications
Article: 4156
Subject: Re: Good Starting points to learn FPGA for hobbyist?
From: devb@katie.vnet.net (David Van den Bout)
Date: 19 Sep 1996 16:51:56 -0400
Links: << >>  << T >>  << A >>
In article <51k4nf$55i@gap.cco.caltech.edu>,
Rudi Cilibrasi <cilibrar@ugcs.caltech.edu> wrote:
>Hi there,
>
>I've worked with PAL's and GAL's before, but never FPGA's.  I would
>like to learn how to use them for hobbyist-type electronic projects.
>Can anyone suggest good starting points for me?  i.e., any cheap or
>free software that can be used, places to find information on fuse-file
>formats (or whatever the equivalent is in FPGA's), websites, or books
>that would be helpful in starting out?  I have a working 68hc11 interfaced
>to my computer already, and can download code to it, so was hoping that
>I might be able to use this as a programmer instead of shelling out more
>$$$ for a hardware programmer in addition to whatever other costs are
>involved in FPGA design.
>
>Any tips (followup or through email) would be greatly appreciated,
>

Rudi:

My company (XESS Corp.) makes a starter kit based on the EPX780/EPX880
series of parts from ALTERA.  For $159, you get a 232-page textbook on
FPGA design techniques, a small board with an EPX780, display, oscillator,
and some other stuff, a downloading cable, and PLDSHELL design software
and examples.  We have a higher level version that also includes an 8032
microcontroller and 32 Kbyte RAM for $249. You can use the EPX780 as
a reconfigurable coprocessor in this version.  You can check these out at
www.xess.com.  Send us your physical address and we'll mail you some
product literature.
-- 
|| Dave Van den Bout  --  XESS Corp. ||
|| 2608 Sweetgum Dr., Apex, NC 27502 ||
|| (919) 387-0076 FAX:(919) 387-1302 ||
|| devb@xess.com       devb@vnet.net ||
Article: 4157
Subject: Re: Are there any FPGA Starter Kits?
From: devb@katie.vnet.net (David Van den Bout)
Date: 19 Sep 1996 16:54:30 -0400
Links: << >>  << T >>  << A >>
In article <51rf89$15e@quagga.ru.ac.za>,
Ray Heasman <ray@rucus.ru.ac.za> wrote:
>Hi All,
>
>I was just wondering - is there an equivalent of the DSP Starter Kit for
>FPGA's? I would love to fiddle with something like that.
>
>Cheerio,
>Ray

Ray:

I'm repeating myself, but my company (XESS Corp.) makes such products.
You can check them out at www.xess.com.  Send me your physical address
and I can also send you some product literature.


-- 
|| Dave Van den Bout  --  XESS Corp. ||
|| 2608 Sweetgum Dr., Apex, NC 27502 ||
|| (919) 387-0076 FAX:(919) 387-1302 ||
|| devb@xess.com       devb@vnet.net ||
Article: 4158
Subject: FPGAs design tools for PC
From: vrowley@kipawa.gel.ulaval.ca (Vincent Rowley)
Date: 19 Sep 1996 22:13:14 GMT
Links: << >>  << T >>  << A >>

Hi,

I'm looking for FPGAs design tools for PC including HDL and gate-level
simulator, synthesis tool and also FPGA development system to implement
Xilinx or Altera FPGAs.

I will appreciate all suggestion from experimented users.

Thanks,

Vincent Rowley
Article: 4159
Subject: Crosspoint FPGA
From: snowbin@ix.netcom.com(Snowbin)
Date: 20 Sep 1996 05:04:25 GMT
Links: << >>  << T >>  << A >>

Has anyone used Crosspoint FPGAs. Are they any good?

--Bin

Article: 4160
Subject: Re: OrCAD schematic based multiplier for XC4000 series
From: mush@netgate.net (David Decker)
Date: Fri, 20 Sep 1996 05:51:51 GMT
Links: << >>  << T >>  << A >>
Jason Crawford <jcrawfor@rp.csiro.au> wrote:

>Hi,

>Does anyone know of any web-sites that offer OrCAD based schematics of 
>Xilinx macro components such as multipliers, FIR filters and the like?

>I need to implement a 10-bit complex multiplier in an XC4025 and will 
>possibly also need to implement some FIR filters.

>Thanx in advance,
>Jason.

>====================================================
>Jason  Crawford. B.E.(Hons 1)
>Experimental Scientist.
>Radio-Systems Program
>CSIRO Division of Radio-Physics
>phone:  +61 2 9372 4163
>fax:    +61 2 9372 4490
>e-mail: jcrawfor@rp.CSIRO.AU
>web:    http://www.rp.csiro.au/staff/jcrawfor.html
>====================================================
The people at 

dsp@xilinx.com 

gave me some very nice multipliers in ViewLogic schematic form, that I
was able to modify for my data widths,. Perhaps they have them in
Orcad form, as well. 

They also have a lot of DSP tools close to release, that use
'distributed arithmetic'. These include tools for FIRs. I haven't had
a chance to try them yet, but my understanding is: the result will
likely be a design that's a little larger than a fully custom FIR, but
you will be able to design it from coefficients  in just an hour or
two. You may be able to get an advanced look at these tools, too, if
you're in a hurry.

I've been contacted by at least 4 people from Xilinx on the DSP work
they are doing. They're really working hard on DSP tools, over there.

Dave Decker
ddecker@diabloresearch.com


Article: 4161
Subject: Re: OrCAD schematic based multiplier for XC4000 series
From: mush@netgate.net (David Decker)
Date: Fri, 20 Sep 1996 05:51:51 GMT
Links: << >>  << T >>  << A >>
Reposting article removed by rogue canceller.

Jason Crawford <jcrawfor@rp.csiro.au> wrote:

>Hi,

>Does anyone know of any web-sites that offer OrCAD based schematics of 
>Xilinx macro components such as multipliers, FIR filters and the like?

>I need to implement a 10-bit complex multiplier in an XC4025 and will 
>possibly also need to implement some FIR filters.

>Thanx in advance,
>Jason.

>====================================================
>Jason  Crawford. B.E.(Hons 1)
>Experimental Scientist.
>Radio-Systems Program
>CSIRO Division of Radio-Physics
>phone:  +61 2 9372 4163
>fax:    +61 2 9372 4490
>e-mail: jcrawfor@rp.CSIRO.AU
>web:    http://www.rp.csiro.au/staff/jcrawfor.html
>====================================================
The people at 

dsp@xilinx.com 

gave me some very nice multipliers in ViewLogic schematic form, that I
was able to modify for my data widths,. Perhaps they have them in
Orcad form, as well. 

They also have a lot of DSP tools close to release, that use
'distributed arithmetic'. These include tools for FIRs. I haven't had
a chance to try them yet, but my understanding is: the result will
likely be a design that's a little larger than a fully custom FIR, but
you will be able to design it from coefficients  in just an hour or
two. You may be able to get an advanced look at these tools, too, if
you're in a hurry.

I've been contacted by at least 4 people from Xilinx on the DSP work
they are doing. They're really working hard on DSP tools, over there.

Dave Decker
ddecker@diabloresearch.com


Article: 4162
Subject: Re: FPGAs design tools for PC
From: Tony Disanto <adisanto@aloft.att.com>
Date: Fri, 20 Sep 1996 11:33:36 -0400
Links: << >>  << T >>  << A >>
John L. Smith wrote:
> 
> Vincent Rowley wrote:
> >
> > Hi,
> >
> > I'm looking for FPGAs design tools for PC including HDL and gate-level
> > simulator, synthesis tool and also FPGA development system to implement
> > Xilinx or Altera FPGAs.
> >
> > I will appreciate all suggestion from experimented users.
> >
> > Thanks,
> >
> > Vincent Rowley
> 
>   I recently started using the Xilinx Foundation tools, coupled w/
> the Xilinx Core toolset. They work very well together. Additionally,
> the support from Xilinx is excellent.
> 
> --
> John L. Smith, Pr. Engr.
> Univision Technologies, Inc.
> 6 Fortune Dr.
> Billerica, MA 01821-3917
> jsmith@univision.com

I'm currently using Synario w/the VHDL option coupled to the Altera
MaxPlus Tools. So far I have been doing some blocks that contain
counters and some state machines. The front tools appears to 'work'
okay. We'll see how well VHDL maps to the target FPGA in a couple of
weeks. So far the test cases for the state machine run 'reg --> reg' at
35MHZ using a FLEX8000-A2 device.  

Adisanto@lucent.com
Article: 4163
Subject: Re: FPGAs design tools for PC
From: "John L. Smith" <jsmith@univision.com>
Date: Fri, 20 Sep 1996 08:47:40 -0700
Links: << >>  << T >>  << A >>
Vincent Rowley wrote:
> 
> Hi,
> 
> I'm looking for FPGAs design tools for PC including HDL and gate-level
> simulator, synthesis tool and also FPGA development system to implement
> Xilinx or Altera FPGAs.
> 
> I will appreciate all suggestion from experimented users.
> 
> Thanks,
> 
> Vincent Rowley

  I recently started using the Xilinx Foundation tools, coupled w/
the Xilinx Core toolset. They work very well together. Additionally,
the support from Xilinx is excellent.

-- 
John L. Smith, Pr. Engr.
Univision Technologies, Inc.
6 Fortune Dr.
Billerica, MA 01821-3917 
jsmith@univision.com
Article: 4164
Subject: Re: Inaccrate Xilinx simulations ???
From: Simon <106072.1620@CompuServe.COM>
Date: 20 Sep 1996 16:05:18 GMT
Links: << >>  << T >>  << A >>
All timing information used for xilinx simulation and by xdelay 
are worst case timings. i.e. for a commercial part, at 4.75v,80 C 
and fro the worst batch ever released. Not only will a -4 speed 
grade part always run faster than the simulation but it might 
infact not be a -4 at all. Because of the way the silicon 
processes yield they are more likely to produce -3 than -4 and so 
if there is a shortage of -4 parts xilinx will ship -3 parts 
marked as -4 to meet the demand. It is exactly for this reason 
that xilinx recomend synchronous design methods.

Simon
Article: 4165
Subject: Re: manchester clock recovery
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 20 Sep 1996 09:19:55 -0700
Links: << >>  << T >>  << A >>
This discussion is now getting interesting.
If you want to receive a Manchester-encoded bit stream of arbitrary
length, it is preferrable if you know the transmitting frequency ( bit
rate ) with a plus/minus 30 percent accuracy.
If you don't, the design gets considerably more complicated, with an
adaptive state machine design.

Let's assume that you know the incoming bit rate, then the circuit that
I mentioned ( the offer to fax it still stands ) does the clock and data
recovery, using only three CLBs clocked at a rate that is eight times
the expected incoming bit rate. The clock frequency can be anywhere
between 0 and 200 MHz, which means the bit rate can be up to 25 MHz.
The circuit works over a ratio of 5 to 12, i.e you need at least 5 and
no more than 12 clocks per incoming bit. That means the design is fairly
tolerant of frequency errors and phase distortions.
The length of the bitstream is irrelevant.

Please, never, never use monostables, and use an analog PLL only as the
last resort. The world is going digital !
 
Peter Alfke, Xilinx Applications
Article: 4166
Subject: Starter Boards
From: john@einstein.vcc.com (John Schewel)
Date: Fri, 20 Sep 1996 22:15:08 GMT
Links: << >>  << T >>  << A >>

Virtual Computer Corp. offers an ISA/FPGA  Protoyping Board for
rapid product development and reconfigurable computing. Though
not a rock-bottom priced product ($1100 & $1400), the added feature 
of this board can be worth it, depending upon your application. It
offers Plug n Play compatiblity, bread board areas, sockets for
drams & eeproms and many other features. The board was designed
with input from university professors, commerical customers, and 
engineers.

You can see the board and it's details on our website:

			www.vcc.com

or contact me directly at jas@vcc.com.

John Schewel, Virtual Computer Corp.


Article: 4167
Subject: BRASS and Re: query: C to FPGA
From: "Andre' DeHon" <amd@CS.Berkeley.EDU>
Date: Sat, 21 Sep 1996 00:08:16 GMT
Links: << >>  << T >>  << A >>

	Brass has come up twice now in conjunction with C->FPGA
translation, so perhaps I should try to clarify our research focus.  The
BRASS project is specifically looking at architectures which tightly couple
reconfigurable resources onto more conventional processors.  We will be
putting serious effort into software mapping issues, but in the process,
we're likely to assume there's a processor available (and very close by) to
handle computations better matched to the processor than for the
reconfigurable array.


	As to the current state of the art for C->FPGA mapping, I think
Scott Hauck did a fairly good job of covering the research in his review. 

	There are a couple of points which may still bear some clarification. 

   ------------------------------------------------------------------------

	First, there are two different things you could want out of a
(nominally) C->FPGA translator. 

	1) translate dusty-deck C, hands-off to your FPGA 
          (reconfigurable system) 
	2) use a familiar, C-like syntax as a "friendly" way to 
            describe FPGA implementations

	I'd argue there's nothing, today, that can really do (1) in a
respectable way.

	Most of the things Scott discussed were more oriented toward (2) --
though some are faithful enough to a proper C subset that you could think
of them as doing (1) on a subset of the code and not with high quality.  

	At least two of the systems are available for you to download
from the net and play with.  Last I looked into them much (a year or two
ago, so my impression could be a bit stale), these were both mostly
syntactic translations -- i.e. they are pretty straightforward translations
of the C(++)-code with minimal analysis and optimization. 

NLC
Christian.Iseli@di.epfl.ch (Christian Iseli)
anonymous ftp to lslsun5.epfl.ch look in /pub
        (contains nlc distributions and thesis excerpts)

TMCC
Dave Galloway, University of Toronto, drg@eecg.toronto.edu
ftp://ftp.eecg.toronto.edu/pub/software/tmcc/
http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmcc

   ------------------------------------------------------------------------

	There are also two cases where you might think of using the C->FPGA
translation.

	a) convert complete C program to run on the FPGA array
	b) convert bits and pieces of the program to run on FPGA
             while running rest on a host processor

	Certainly, PRISM and RECON were oriented toward (b).

      Brass, to the extent it gets into this, will be concerned with (b),
as well. 

	The benefit of (b) is that you can punt back to the processor on
things for which it doesn't make sense to use the array (irregular
computations, i/o, full-blown FP, etc.) or when you have insufficient array
resources.  It also allows you to punt back to the processor for things you
haven't, yet, figured out how to map well to the array (e.g. places where
you can't sufficiently disambiguate pointer aliasing).  

	Of course, to do (b), you need to have a processor, and you must
have a pretty good idea of the characteristics of the interface between
your processor and array.

   ------------------------------------------------------------------------


	Tim Callahan <timothyc@cs.berkeley.edu> is the person working on
the current C compilation effort
<http://www.cs.berkeley.edu/projects/brass/compile.html>.  His target is
GARP (by John Hauser) which includes a custom array design which has some
different properties from conventional FPGAs.  Tim plans for the compiler
to be somewhat retargettable, but host->array coupling and configuration
management aspects are part of the BRASS research and may be not have
direct analogs in existing FPGAs.  While PRISM/RECON/NLC/TMCC/etc. output
standard FPGA netlists, Tim's tools pull in some of the backend issues to
deal with the custom array.  As a result, Tim's compiler might not actually
"transform selected C (or Fortran) routines into FPGA netlists" in a strict
sense.  Nonetheless, many of the ideas developed as part of the effort
might be useful to people doing direct mapping to more traditional FPGA
netlist mapping.



						       Andre' DeHon
						amd@cs.berkeley.edu

   ------------------------------------------------------------------------
> From: ray@rucus.ru.ac.za (Ray Heasman)
> Date: 3 Sep 1996 14:31:54 GMT
> Subject: Re: query: C to FPGA?
> 
> Mark Smotherman (mark@hubcap.clemson.edu) wrote:
> : I would like to get pointers to any work on custom computing
> : machines that transform selected C (or Fortran) routines into
> : FPGA netlists.  I have found papers and links to PRISM-II, being
> : done at the Lab for Engineering Man/Machine Systems at Brown
> : University.  Are there other configuration compilers available,
> : either at universities or from vendors?
> 
> : What is the state-of-the-art in taking a C function that uses
> : floating-point and compiling it to FPGAs?  Is there any kind of
> : automated scaling for changing floating-point (w/ ranges on the
> : input variables) into integer-only replacements, and thus easily
> : into FPGAs?  (I've seen Dan McCracken's 1957 textbook that shows
> : how to do this by hand, but I wonder if it has been automated
> : and integrated into a configuration compiler.  PRISM-II doesn't
> : do flt-pt.)
> 
> : Thanks.
> 
> Erm, there is such a system in development, but I can't remember the name.
> However, the following URL will get you pretty close to where you want to
> go:
> 
> 	http://HTTP.CS.Berkeley.EDU/Research/Projects/brass
> 
> It has a pointer to a site about the compiler used.
> 
> Cheerio,
> Ray

   ------------------------------------------------------------------------

> From: ray@rucus.ru.ac.za (Ray Heasman)
> Date: 17 Sep 1996 13:05:02 GMT
> Subject: Re: ? C to FPGA
> 
           .
           .
           .
 
> Have a look for the BRASS and IRAM pages at Berkeley. They are working with
> Stanford to make such compilers.
> 
> Cheerio,
> Ray


   ------------------------------------------------------------------------

	


	

	
	
Article: 4168
Subject: Q: PLD vs. FPGA
From: mpayne@io.com (Michael Payne)
Date: 21 Sep 1996 01:56:22 GMT
Links: << >>  << T >>  << A >>
I'm a hobbyist that is designing a project using an MCU (PIC17 or 
something else) that will connect to the following:

* 64K of memory - partitioned in EEPROM (maybe FLASH) and SRAM
* Graphic LCD display with builtin controller
* Serial A/D converter
* An A/D device that clocks out 24-bits of data 4-bits at a time.
  This device needs two 2ms delays before bit 0 and bit 12.
* Possibly a serial eeprom for data storage
* 3-5 pushbuttons of user input

My problems is that when I use external memory with an MCU most of my I/O 
pins get used and there isn't enough left to connect the rest of my 
components.  I searched for a simple control port chip but could not find 
one that would solve my problem.  Would an FPGA or PLD solve my problem?  
Could I use one of these devices to map into the address space and access 
these devices?  Also, could I program an FPGA or PLD to do my data access 
for me and just send an interrupt when the data was ready?

I've seen PLD designs that are basic I/O control ports (Amtel had one on 
their web page) but one of my devices needs two 2ms delays during it's 
access.  Can you program delays in PLDs?

I've already built this project with a 68HC711E9 and a 2x16 LCD display 
but the 12K of internal EPROM was a little small and the 512 bytes of 
EEPROM was not enough.

Any help or opinions would be appreciated

Regards,
Mike

mpayne@io.com

Article: 4169
Subject: CFP - Int. Symp. on Physical Design, Apr 14-16, CA
From: ispd97@jade.cs.Virginia.EDU (ISPD-97 Organization)
Date: Sat, 21 Sep 1996 02:29:56 GMT
Links: << >>  << T >>  << A >>
                             Call for Papers

               1997 International Symposium on Physical Design
                             April 14-16, 1997
                          Napa Valley, California

              Sponsored by the ACM SIGDA in cooperation with 
                   IEEE Circuits and Systems Society

The International Symposium on Physical Design provides a forum to exchange
ideas and promote research on critical areas related to the physical design
of VLSI systems.     All aspects of physical design, from interactions with
behavior- and logic-level synthesis, to back-end performance analysis and
verification, are within the scope of the Symposium.    Target domains include 
semi-custom and full-custom IC, MCM and FPGA based systems.
 
The Symposium is an outgrowth of the ACM/SIGDA Physical Design Workshop.  
Following its five predecessors, the symposium will highlight key new 
directions and leading-edge theoretical and experimental contributions to 
the field. Accepted papers will be published by ACM Press in the Symposium 
proceedings. Topics of interest include but are not limited to:

       1. Management of design data and constraints 
       2. Interactions with behavior-level synthesis flows 
       3. Interactions with logic-level (re-)synthesis flows 
       4. Analysis and management of power dissipation 
       5. Techniques for high-performance design 
       6. Floorplanning and building-block assembly 
       7. Estimation and point-tool modeling 
       8. Partitioning, placement and routing 
       9. Special structures for clock, power, or test
      10. Compaction and layout verification
      11. Performance analysis and physical verification 
      12. Physical design for manufacturability and yield 
      13. Mixed-signal and system-level issues.
      
IMPORTANT DATES:    Submission deadline:              December 20, 1996
                    Acceptance notification:          February 1, 1997
                    Camera-ready (6 page limit) due:  March 1, 1997

SUBMISSION OF PAPERS:
    Authors should submit full-length, original, unpublished papers 
    (maximum 20 pages double spaced) along with an abstract of at most 
    200 words and contact author information (name, street/mailing address, 
    telephone/fax, e-mail).

    Electronic submission via uuencoded e-mail is encouraged (single 
    postscript file, formatted for 8 1/2" x 11" paper, compressed with 
    Unix "compress" or "gzip''). Email to:

                        ispd97@ece.nwu.edu

    Alternatively, send ten (10) copies of the paper to:

                        Prof. Majid Sarrafzadeh
                        Technical Program Chair, ISPD-97
                        Dept. of ECE, Northwestern University
                        2145 Sheridan Road, Evanston, IL 60208 USA
                        Tel 847-491-7378 / Fax 847-467-4144 

SYMPOSIUM INFORMATION:
    To obtain information regarding the Symposium or to be added to the
    Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu. 
    Information can also be found on the ISPD-97 web page:   

                         http://www.cs.virginia.edu/~ispd97/

SYMPOSIUM ORGANIZATION:

Steering Committee:          J. Cohoon (Virginia), S. Dasgupta (Sematech),
                             S. M. Kang (Illinois), B. Preas (Xerox PARC) 
Past Chair:                  G. Robins (Virginia)
General Chair:               A. B. Kahng (UCLA and Cadence)
Program Chair:               M. Sarrafzadeh (Northwestern)
Keynote Address:             T. C. Hu (UC San Diego) and E. S. Kuh (UC Berkeley)
Special Address:             R. Camposano (Synopsys)
Publicity Chair:             M. J. Alexander (Washington State)
Local Arrangements Chair:    J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego),
                             W. W.-M. Dai (UC Santa Cruz), 
                             D. D. Hill (Synopsys), 
                             M. A. B. Jackson (Motorola), 
                             J. A. G. Jess (Eindhoven),  
                             Y.-L. Lin (Tsing Hua), 
                             C. L. Liu (Illinois),
                             M. Marek-Sadowska (UC Santa Barbara),
                             M. Sarrafzadeh (Northwestern), Chair, 
                             C. Sechen (Washington), 
                             K. Takamizawa (NEC),
                             S. Trimberger (Xilinx), 
                             M. Wiesel (Intel), 
                             D. F. Wong (Texas-Austin), 
                             E. Yoffa (IBM)


Article: 4170
Subject: What's the difference between PLD and FPGA?
From: mpayne@io.com (Michael Payne)
Date: 21 Sep 1996 16:31:22 GMT
Links: << >>  << T >>  << A >>
I'm a hobbyist that is designing a project using an MCU (PIC17 or 
something else) that will connect to the following:

* 64K of memory - partitioned in EEPROM (maybe FLASH) and SRAM
* Graphic LCD display with builtin controller
* Serial A/D converter
* An A/D device that clocks out 24-bits of data 4-bits at a time.
  This device needs two 2ms delays before bit 0 and bit 12.
* Possibly a serial eeprom for data storage
* 3-5 pushbuttons of user input

My problems is that when I use external memory with an MCU most of my I/O 
pins get used and there isn't enough left to connect the rest of my 
components.  I searched for a simple control port chip but could not find 
one that would solve my problem.  Would an FPGA or PLD solve my problem?  
Could I use one of these devices to map into the address space and access 
these devices?  Also, could I program an FPGA or PLD to do my data access 
for me and just send an interrupt when the data was ready?

I've seen PLD designs that are basic I/O control ports (Amtel had one on 
their web page) but one of my devices needs two 2ms delays during it's 
access.  Can you program delays in PLDs?

I've already built this project with a 68HC711E9 and a 2x16 LCD display 
but the 12K of internal EPROM was a little small and the 512 bytes of 
EEPROM was not enough.

Any help or opinions would be appreciated

Regards,
Mike

mpayne@io.com


Article: 4171
Subject: What's the difference between PLD and FPGA?
From: mpayne@io.com (Michael Payne)
Date: 21 Sep 1996 16:31:22 GMT
Links: << >>  << T >>  << A >>
Reposting article removed by rogue canceller.

I'm a hobbyist that is designing a project using an MCU (PIC17 or 
something else) that will connect to the following:

* 64K of memory - partitioned in EEPROM (maybe FLASH) and SRAM
* Graphic LCD display with builtin controller
* Serial A/D converter
* An A/D device that clocks out 24-bits of data 4-bits at a time.
  This device needs two 2ms delays before bit 0 and bit 12.
* Possibly a serial eeprom for data storage
* 3-5 pushbuttons of user input

My problems is that when I use external memory with an MCU most of my I/O 
pins get used and there isn't enough left to connect the rest of my 
components.  I searched for a simple control port chip but could not find 
one that would solve my problem.  Would an FPGA or PLD solve my problem?  
Could I use one of these devices to map into the address space and access 
these devices?  Also, could I program an FPGA or PLD to do my data access 
for me and just send an interrupt when the data was ready?

I've seen PLD designs that are basic I/O control ports (Amtel had one on 
their web page) but one of my devices needs two 2ms delays during it's 
access.  Can you program delays in PLDs?

I've already built this project with a 68HC711E9 and a 2x16 LCD display 
but the 12K of internal EPROM was a little small and the 512 bytes of 
EEPROM was not enough.

Any help or opinions would be appreciated

Regards,
Mike

mpayne@io.com


Article: 4172
Subject: Re: Q: PLD vs. FPGA
From: mush@netgate.net (David Decker)
Date: Sat, 21 Sep 1996 17:40:49 GMT
Links: << >>  << T >>  << A >>
mpayne@io.com (Michael Payne) wrote:

>I'm a hobbyist that is designing a project using an MCU (PIC17 or 
>something else) that will connect to the following:

>* 64K of memory - partitioned in EEPROM (maybe FLASH) and SRAM
>* Graphic LCD display with builtin controller
>* Serial A/D converter
>* An A/D device that clocks out 24-bits of data 4-bits at a time.
>  This device needs two 2ms delays before bit 0 and bit 12.
>* Possibly a serial eeprom for data storage
>* 3-5 pushbuttons of user input

>My problems is that when I use external memory with an MCU most of my I/O 
>pins get used and there isn't enough left to connect the rest of my 
>components.  I searched for a simple control port chip but could not find 
>one that would solve my problem.  Would an FPGA or PLD solve my problem?  
>Could I use one of these devices to map into the address space and access 
>these devices?  Also, could I program an FPGA or PLD to do my data access 
>for me and just send an interrupt when the data was ready?

.  .  .  
>Regards,
>Mike

>mpayne@io.com

Of course you can do all these things with FPGAs. I extend micro I/O
all the time, by implementing memory mapped I/O ports in Xilinx chips.
If you are going to have the micro's address and data lines connected
to your FPGA anyway, you could use an SRAM type FPGA and, configure it
from data stored at the top of your FLASH, while your micro runs from
the lower portion. The FPGA would hold the micro reset while it
configures, after which time the FPGA would release the adr lines and
starts implementing the I/O ports.

Delay should be implemented by a counter in the FPGA, possibly using
the clock from your micro as a time base, if you don't have another
clk. The rest of this long winded reply just covers ways to use the
micro xtal clock signal as an FPGA clk source.

Some micros have a buffered version of the xtal clock that can be fed
to the FPGA, but if that is not possible, here's what I do. Steal a
little energy from the micro's xtal amp output, via a 100pF cap. Bring
this to the Xtal input of your FPGA. (xtal2 on a Xilinx 3K or 2K) Bias
the FPGA's inverting xtal amp into its linear region with a 1M ohm
resistor tied between the xtal in and xtal out pins on the FPGA.
Internal to the FPGA, you can now use this amplified clock signal to
run your counter.

In the rare design where you must stop the micro's clock, yet keep the
FPGA running, you will have a problem with the above suggestion. You
don't want the FPGA's xtal amp to be allowed to just sit with both its
input and output statically at the threshold! That would cause both to
draw a bunch of current and in general be poor design practice. In
cases like this I would use general purpose I/O pins on the FPGA
rather than the special xtal amp. Use a NAND gate rather than an
inverter as the FPGA clock amp. This allows you to break the bias feed
back during the time when the micro's clock stops, by supplying a
logic high to the bias resistor instead of the threshold Voltage.

Just to cover all the bases, if you need to use this FPGA xtal amp,
for speed, you can short the xtal amp input pin to a general purpose
I/O FPGA pin externally. When you need to stop the micro clock, just
pull the xtal pin up or down with the I/O pin. The 1M ohm resistor
will only draw a few uA. When the micro clock is running, make the
general purpose I/O pin 'Hi Z'.

Cheers, 
Dave Decker
ddecker@diabloresearch.com
or mush@netgate.net


Article: 4173
Subject: Re: Q: PLD vs. FPGA
From: mush@netgate.net (David Decker)
Date: Sat, 21 Sep 1996 17:40:49 GMT
Links: << >>  << T >>  << A >>
Reposting article removed by rogue canceller.

mpayne@io.com (Michael Payne) wrote:

>I'm a hobbyist that is designing a project using an MCU (PIC17 or 
>something else) that will connect to the following:

>* 64K of memory - partitioned in EEPROM (maybe FLASH) and SRAM
>* Graphic LCD display with builtin controller
>* Serial A/D converter
>* An A/D device that clocks out 24-bits of data 4-bits at a time.
>  This device needs two 2ms delays before bit 0 and bit 12.
>* Possibly a serial eeprom for data storage
>* 3-5 pushbuttons of user input

>My problems is that when I use external memory with an MCU most of my I/O 
>pins get used and there isn't enough left to connect the rest of my 
>components.  I searched for a simple control port chip but could not find 
>one that would solve my problem.  Would an FPGA or PLD solve my problem?  
>Could I use one of these devices to map into the address space and access 
>these devices?  Also, could I program an FPGA or PLD to do my data access 
>for me and just send an interrupt when the data was ready?

.  .  .  
>Regards,
>Mike

>mpayne@io.com

Of course you can do all these things with FPGAs. I extend micro I/O
all the time, by implementing memory mapped I/O ports in Xilinx chips.
If you are going to have the micro's address and data lines connected
to your FPGA anyway, you could use an SRAM type FPGA and, configure it
from data stored at the top of your FLASH, while your micro runs from
the lower portion. The FPGA would hold the micro reset while it
configures, after which time the FPGA would release the adr lines and
starts implementing the I/O ports.

Delay should be implemented by a counter in the FPGA, possibly using
the clock from your micro as a time base, if you don't have another
clk. The rest of this long winded reply just covers ways to use the
micro xtal clock signal as an FPGA clk source.

Some micros have a buffered version of the xtal clock that can be fed
to the FPGA, but if that is not possible, here's what I do. Steal a
little energy from the micro's xtal amp output, via a 100pF cap. Bring
this to the Xtal input of your FPGA. (xtal2 on a Xilinx 3K or 2K) Bias
the FPGA's inverting xtal amp into its linear region with a 1M ohm
resistor tied between the xtal in and xtal out pins on the FPGA.
Internal to the FPGA, you can now use this amplified clock signal to
run your counter.

In the rare design where you must stop the micro's clock, yet keep the
FPGA running, you will have a problem with the above suggestion. You
don't want the FPGA's xtal amp to be allowed to just sit with both its
input and output statically at the threshold! That would cause both to
draw a bunch of current and in general be poor design practice. In
cases like this I would use general purpose I/O pins on the FPGA
rather than the special xtal amp. Use a NAND gate rather than an
inverter as the FPGA clock amp. This allows you to break the bias feed
back during the time when the micro's clock stops, by supplying a
logic high to the bias resistor instead of the threshold Voltage.

Just to cover all the bases, if you need to use this FPGA xtal amp,
for speed, you can short the xtal amp input pin to a general purpose
I/O FPGA pin externally. When you need to stop the micro clock, just
pull the xtal pin up or down with the I/O pin. The 1M ohm resistor
will only draw a few uA. When the micro clock is running, make the
general purpose I/O pin 'Hi Z'.

Cheers, 
Dave Decker
ddecker@diabloresearch.com
or mush@netgate.net


Article: 4174
Subject: Re: manchester clock recovery
From: murray@pa.dec.com (Hal Murray)
Date: 21 Sep 1996 22:06:45 GMT
Links: << >>  << T >>  << A >>
In article <3242C3DB.7EB8@xilinx.com>, Peter Alfke <peter@xilinx.com> writes:

> Please, never, never use monostables, and use an analog PLL only as the
> last resort. The world is going digital !

I think the analog guys still own the high frequency end.  Consider
doing clock recovery at 622 MHz.

Another way of looking at things is that a small counter is an easy
way to implement a monostable.


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