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Messages from 4250

Article: 4250
Subject: Re: Reconfigurable hardware
From: husby@fnal.gov (Don Husby)
Date: 4 Oct 1996 16:22:31 GMT
Links: << >>  << T >>  << A >>
Pasquale Corsonello pascor@ccusc1.unical.it wrote:
> does anybody know of reconfigurable hardware for arithmetic operations?
> For example, reconfigurable hardware for division and square root.

I have algorithms for square-root, small-integer division, and 
Center-of-Mass.  These are implemented in ORCA FPGA's.

The SQRT algorithm can implement a 16-to-8 square root in about 70ns
non-pipelined.  It can be pipelined to about 8 levels.

The Div uses log tables and shifters.  It accepts 9-bit numbers and
produces a result accurate to about 4 bits.  It also works in under
100ns non-pipelined.  It can be pipelined to 4 levels.

The COM algorithm accepts a vector of five 6-bit numbers (pixel values)
and computes their center of mass.  It can accept a pixel value every
20ns.

Contact me if you want schematics or C-language simulations for
these algorithms.


Article: 4251
Subject: FPGA for Reed-Solomon Codec
From: Hui Zhang <hui@eecs.berkeley.edu>
Date: Fri, 04 Oct 1996 11:04:54 -0700
Links: << >>  << T >>  << A >>
Hi!

Has anyone done any FPGA design for Reed-Solomon Codec (which is for
error correction in data communication)? I would like to do some
perfomance/cost comparison between FPGA, Custom IC, and processors,
etc..

Any information will be appreciated.

Thomas H. Zhang
email: hui@eecs.berkeley.edu
Article: 4252
Subject: Re: Q on Xilinx/Viewsim macros
From: Ray Andraka <randraka@ids.net>
Date: Fri, 04 Oct 1996 12:56:43 -0700
Links: << >>  << T >>  << A >>
The following is copied from SynaptiCAD's web page.  While I haven't 
personally used this tool yet, I've heard lots of good things about it.  
It does export to the viewsim command file format, and from what I've 
heard makes short work of long stimulus files:

SynaptiCAD presents WaveFormer Pro, a tool for creating and analyzing 
timing diagrams and for porting to and from simulators and logic
analyzers. Draw timing diagrams using all the features of Timing 
Diagrammer like delays, setups, and holds which force and monitor signal
transitions. Use WaveFormer scripts to export timing diagrams to your 
favorite simulator. Import waveforms from simulators or logic analyzers
and use WaveFormer's features to annotate and document the waveforms. 

Check out their page at http://www.syncad.com/index.htm

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 4253
Subject: Re: Reconfigurable hardware
From: Ray Andraka <randraka@ids.net>
Date: Fri, 04 Oct 1996 13:31:01 -0700
Links: << >>  << T >>  << A >>
Pasquale Corsonello wrote:

> does anybody know of reconfigurable hardware for arithmetic operations?
> For example, reconfigurable hardware for division and square root.


Several years ago I designed a pipelined CORDIC processor that could 
compute both division and square root, along with multiplication,squares,
all the trig functions and their inverses, hyperbolic trig functions and 
their inverses, logs and exponents, vector rotations and 
polar/rectangular conversions at better than 25 Mhz.  The chip is not 
commercially available, but the algorithms can be made to fit in an FPGA, 
and with some clever design you can even get similar performance.

All of the algorithms use a similar structure consisting of shifters, 
adder/subtractors and for a few of them, comparators or very small LUTs. 
The similar structure permits the same hardware to be reused with very 
small interconnection changes for a wide variety of functions.  The 
CORDIC algorithms are iterative.  The result generally improves in 
accuracy by around a bit per iteration. The iterations can be straighted 
out into a pipelined processor for high performance systems, or 
implemented in bit serial hardware loop for an extremely compact 
processor.

Naturally, there are other solutions for most of these functions. For a 
fixed function a different solution may be a better solution, but for a 
compact flexible processor I think the CORDIC approach is probably best.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
mailto:randraka@ids.net
http://www.ids.net/~randraka/
 
The Andraka Consulting Group is a digital hardware design firm 
specializing in high performance FPGA designs.  Services include 
complete design, development, simulation, and integration of these 
devices and the surrounding circuits.  We also evaluate,troubleshoot, 
and improve existing designs. Please call or write for a free 
brochure or visit our web site.
Article: 4254
Subject: Re: Viewlogic 4.1 (DOS) mouse alternatives?
From: "Jon Harris" <jharris@spectralinc.com>
Date: 5 Oct 1996 00:35:05 GMT
Links: << >>  << T >>  << A >>
I use a Logitech 3-button mouse.  They are easy to find and not too
expensive.  I have to make a call to the mouse driver before entering
Workview for it to work properly, but that's no big deal.  Let me know if
you want more info.


Peter <scanner@dial.pipex.com> wrote in article
<3250dbed.106499@news.alt.net>...
> The above app requires a "Mouse Systems PC Mouse". It calls it
> directly, on com1 or com2, so any driver emulation does not work.
> 
> Has anyone ever found a way to use a normal "Microsoft" serial or bus
> mouse with this program?
> 
> The reason I ask is that mice which *internally* emulate the old
> PC-Mouse are now rare. Perhaps I should ask if anyone has one of the
> original 3-button Mouse Systems optical mice to sell :)
> 

Article: 4255
Subject: Re: Viewlogic 4.1 (DOS) mouse alternatives?
From: eteam@aracnet.com (bob elkind)
Date: Sat, 5 Oct 1996 06:39:04 +0100
Links: << >>  << T >>  << A >>
In article <3250dbed.106499@news.alt.net>, scanner@dial.pipex.com says...
> Hello,
> 
> The above app requires a "Mouse Systems PC Mouse". It calls it
> directly, on com1 or com2, so any driver emulation does not work.

I *think* that the old versions of ViewLogic also supported the
Logitech mouse.  Maybe the Logitech support was added later than
your version, but it's worth a shot.  Logitech mice are available
around here for about $20 retail.

Give it a shot...  and good luck!

- Bob

**************************************************************************
Bob Elkind                mailto:eteam@aracnet.com            CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************
Article: 4256
Subject: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
From: ispd97@jade.cs.Virginia.EDU (1997 International Symposium on Physical Design)
Date: Sat, 5 Oct 1996 17:40:51 GMT
Links: << >>  << T >>  << A >>
=============================================================================

                             Call for Papers

               1997 International Symposium on Physical Design
                             April 14-16, 1997
                          Napa Valley, California

              Sponsored by the ACM SIGDA in cooperation with 
                   IEEE Circuits and Systems Society

   The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems.  All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium.  Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
 
   The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop.  Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings. Topics of
interest include but are not limited to:

       1. Management of design data and constraints 
       2. Interactions with behavior-level synthesis flows 
       3. Interactions with logic-level (re-)synthesis flows 
       4. Analysis and management of power dissipation 
       5. Techniques for high-performance design 
       6. Floorplanning and building-block assembly 
       7. Estimation and point-tool modeling 
       8. Partitioning, placement and routing 
       9. Special structures for clock, power, or test
      10. Compaction and layout verification
      11. Performance analysis and physical verification 
      12. Physical design for manufacturability and yield 
      13. Mixed-signal and system-level issues.
      
IMPORTANT DATES:    Submission deadline:              December 20, 1996
                    Acceptance notification:          February 1, 1997
                    Camera-ready (6 page limit) due:  March 1, 1997

SUBMISSION OF PAPERS:

    Authors should submit full-length, original, unpublished papers 
    (maximum 20 pages double spaced) along with an abstract of at most 
    200 words and contact author information (name, street/mailing address, 
    telephone/fax, e-mail).

    Electronic submission via uuencoded e-mail is encouraged (single 
    postscript file, formatted for 8 1/2" x 11" paper, compressed with 
    Unix "compress" or "gzip''). Email to:

                        ispd97@ece.nwu.edu

    Alternatively, send ten (10) copies of the paper to:

                        Prof. Majid Sarrafzadeh
                        Technical Program Chair, ISPD-97
                        Dept. of ECE, Northwestern University
                        2145 Sheridan Road, Evanston, IL 60208 USA
                        Tel 847-491-7378 / Fax 847-467-4144 

SYMPOSIUM INFORMATION:

    To obtain information regarding the Symposium or to be added to the
    Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu. 
    Information can also be found on the ISPD-97 web page:   

                         http://www.cs.virginia.edu/~ispd97/

SYMPOSIUM ORGANIZATION:

General Chair:               A. B. Kahng (UCLA and Cadence)
Past Chair:                  G. Robins (Virginia)
Steering Committee:          J. Cohoon (Virginia), S. Dasgupta (Sematech),
                             S. M. Kang (Illinois), B. Preas (Xerox PARC) 
Program Chair:               M. Sarrafzadeh (Northwestern)
Keynote Address:             T. C. Hu (UC San Diego) & E. S. Kuh (UC Berkeley)
Special Address:             R. Camposano (Synopsys)
Publicity Chair:             M. J. Alexander (Washington State)
Local Arrangements Chair:    J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
                             W. W.-M. Dai (UC Santa Cruz) 
                             J. Frankle (Xilinx) 
                             D. D. Hill (Synopsys) 
                             M. A. B. Jackson (Motorola) 
                             J. A. G. Jess (Eindhoven)  
                             Y.-L. Lin (Tsing Hua) 
                             C. L. Liu (Illinois)
                             M. Marek-Sadowska (UC Santa Barbara)
                             M. Sarrafzadeh (Northwestern)
                             C. Sechen (Washington) 
                             K. Takamizawa (NEC)
                             M. Wiesel (Intel) 
                             D. F. Wong (Texas-Austin) 
                             E. Yoffa (IBM)

=============================================================================

Article: 4257
Subject: Re: Q on Xilinx/Viewsim macros
From: scannner@dial.pipex.com (mis-spelt!)
Date: Sat, 05 Oct 1996 22:28:37 GMT
Links: << >>  << T >>  << A >>

>(l rd- ; sim 1us ; h rd- ; sim 1us)*256

Philip, you are a GENIUS!

And, no, I still can't find this in my manual... Probably parts are
missing.

Article: 4258
Subject: Re: Altera Checksums
From: Richard_Vireday@ccm.jf.intel.com (Richard Vireday)
Date: Sat, 05 Oct 1996 22:33:57 GMT
Links: << >>  << T >>  << A >>
Fred,

Sometimes devices are not wholly erased from manufacturing. If you are using
both OTP and windowed, this can show up from the hidden trim bits which are
left in after programming.  On OTP devices, those never get erased.

Also the are you looking at the FUSE checksum or the JEDEC file checksum.
There are two, so make sure you don't get them confused.

If the devices programmed okay, and are both working in the circuit, there
is no problem.  It is probably accountable by the different test trim bits
on these older EP1810 devices.

--Richard Vireday
(speaking for myself, !Intel)

david@fpga.demon.co.uk (David Pashley) wrote:
>Fred,
>
>A couple of suggestions:
>
>Use the programmer's Compare function to find out exactly which bits 
>are different. This may give you a clue.
YES.  Of course, then you need a bitmap to tell what the bits do or
don't do.

>Being programmed is the most stressful event in the life of the 
>device, and only by applying vector test after this event can you 
>reach the highest quality levels.
>

>"Thes two devices function identically yet there must be some
>"difference between them
>"Possibilities:

>
>-- 
>David Pashley  
>

Article: 4259
Subject: Re: QuickLogic
From: sarfati@netvision.net.il
Date: Sun, 06 Oct 96 08:23:08 PDT
Links: << >>  << T >>  << A >>

I have used these chips and their developement package (QuickWorks) for some
designs. 
In my opinion, the QuickWorks package is very good for its price, both for 
schematic and HDL developement; they are reasonably easy to learn and use, 
don't require a super-powerful PC and give pretty good results.

the chips are fast and have good routing resources. The problems are:

QL don't have yet high-capacity chips; their largest chips is currently 
approx. 9K gates.

Another problem: these chips are OTP and can't be programmed on-board; 
programming a chip in a fine-pitch package is tricky and updating a chip 
already soldered is both VERY tricky and expensive (you throw away the old 
chip and may damage the whole board).

			Regards
			Assaf Sarfati


Article: 4260
Subject: 1 Download -> alle Mails in allen Global foren weg
From: Michael Schnell <MSCHNELL@LUMINO>
Date: Mon, 7 Oct 96 09:43:27 +0100
Links: << >>  << T >>  << A >>

-Michael Schnell, Lumino GmbH, Krefeld, Germany.
 mailto:mschnell@lumino.mhs.compuserve.com

Article: 4261
Subject: Anyone using Altera MaxPlus VHDL ???
From: sja@world.std.com (Stuart J Adams)
Date: Mon, 7 Oct 1996 13:54:06 GMT
Links: << >>  << T >>  << A >>
I am considering getting Altera's MaxPlus VHDL synthesis
add-on. Was wondering if anyone is using this and how it
compares to other synthesis tools such as Synplicity,
Synopsys, or Exemplar ???


Thanks,
  Stuart Adams
  sja@world.std.com

-- 

Stuart Adams
Chief Engineer
Bright Star Engineering
Article: 4262
Subject: Re: FPGA for Reed-Solomon Codec
From: christof@goya.WPI.EDU (Christof Paar)
Date: 7 Oct 1996 13:59:29 GMT
Links: << >>  << T >>  << A >>
Thomas,

I have done extensive work on low-complexity arithmetic architectures 
for Galois fields, in particular for RS codes. Recent results suggest 
that they are extremely well suited for FPGA implementation (almost 
half the CLB count for bit parallel multiplication in GF(2^8) as 
compared to traditional architectures.) There are also very efficient
inversion architectures. The basic idea is to introduce a subfield,
e.g., to represent GF(2^8) as GF((2^4)^2).

We also implemented an RS codec on a DSP with a simple FPGA coprocessor 
for Galois field arithmetic with 16 bit symbols a while ago.

Please email me if you are interested in more detailed information 
(papers etc.)

Hope this is of interest,

Christof


******************************************************************************
Christof Paar                        http://ee.wpi.edu/People/faculty/cxp.html
Assistant Professor                  email:  christof@ece.wpi.edu
ECE Department                       phone:  (508) 831 5061
Worcester Polytechnic Institute      fax:    (508) 831 5491
100 Institute Road 
Worcester, MA 01609, USA 
******************************************************************************





Hui Zhang (hui@eecs.berkeley.edu) wrote:
: Hi!

: Has anyone done any FPGA design for Reed-Solomon Codec (which is for
: error correction in data communication)? I would like to do some
: perfomance/cost comparison between FPGA, Custom IC, and processors,
: etc..

: Any information will be appreciated.

: Thomas H. Zhang
: email: hui@eecs.berkeley.edu
Article: 4263
Subject: Re: FPGA for Reed-Solomon Codec
From: wright@iecorp.com (Jason T. Wright)
Date: Mon, 07 Oct 1996 16:44:16 GMT
Links: << >>  << T >>  << A >>
Hui Zhang <hui@eecs.berkeley.edu> wrote:

>Hi!

>Has anyone done any FPGA design for Reed-Solomon Codec (which is for
>error correction in data communication)? I would like to do some
>perfomance/cost comparison between FPGA, Custom IC, and processors,
>etc..

>Any information will be appreciated.

>Thomas H. Zhang
>email: hui@eecs.berkeley.edu

----------------------------------------------------------
There is a company in England, Object Oriented Hardware, that is
selling HDL models.  Check Altera's home page.

Also, you could check with Boonsieng Benjauthrit at Datatape.  He has
been doing some work along that line.  (benjauth@datatape.com)


Jason T. Wright

Article: 4264
Subject: Re: Partition tool for FPGAs?
From: ccwest@ix.netcom.com (Bill Seiler)
Date: Mon, 07 Oct 1996 17:23:05 GMT
Links: << >>  << T >>  << A >>
I have a package from a company called:

ACEO Technoligy, Inc.
48834 Kato Road, #105A
Fremont, CA 94538-7368
Phone (510) 656-2189
Fax (510) 770-9937

This appears to do synthesis from Verilog as well as partitioning of
large designs into multiple FPGA's.  I am trying to get an update to
run this software under Windows95.  I will post my results.


Thanks
 
    ___  ___
   /   /\  /\           Bill Seiler
  /___/  \/__\          Circuit City / Patapsco West  
 /\   \  /   /\         3255-4 Scott Blvd, Suite 105
/__\___\/___/  \        Santa Clara, CA 95054
\  /   /\   \  /        408 982 5420 Direct
 \/___/  \___\/         408 982 5430 FAX
  \   \  /\  /\         ccwest@ix.netcom.com 
   \___\/__\/  \
        \   \  /        "Fold me up into 4D space."
         \___\/


david@fpga.demon.co.uk (David Pashley) wrote:

>In article <324A817A.2C6D@nmp.nokia.com>
>           teppo.hemia@nmp.nokia.com "Teppo Hemia" writes:

>"Hi all,
>"
>"Does anyone know a good partition tool for multiple
>"FPGAs? It should not be too automatic letting possible
>"to do the partition partly manually also. 
>"
>"It can be fully manual, if it is interactive for 
>"resulting the partition changes.
>"
>"Any suggestion most welcome.
>"
>The partitioner from MINC-IST is worth looking at. You can constrain 
>it via a number of means such as manual partition definition.

>The product is timing-driven, and supports Xilinx, Actel and Altera 
>FLEX. MINC also have a PLD partitioner that supports AMD MACH 
>devices.

>Try salesinfo@minc.com or support@ist.fr

>Cheers

>David



Article: 4265
Subject: Re: Q on Xilinx/Viewsim macros
From: Paul Hartley <pjh@microplex.com>
Date: Mon, 07 Oct 1996 11:43:06 -0700
Links: << >>  << T >>  << A >>
mis-spelt! wrote:
> 
> >(l rd- ; sim 1us ; h rd- ; sim 1us)*256
> 
> Philip, you are a GENIUS!
> 
> And, no, I still can't find this in my manual... Probably parts are
> missing.

Parts of the Xilinx manuals _are_ missing (Oct 1995 edition).  Xilinx 
appears to have written their own version of the Viewlogic tutorials and 
interface guide, making these documents next to useless as reference 
books.  Documentation is a weak link in what is an otherwise good Xilinx 
product.

Interestingly, in our eng department we also use the same Viewlogic tools 
for Actel FPGAs.  The're the same tools, but the Viewlogic documentation 
that came with the Actel/Viewlogic tools is much more complete.

-- 

Paul Hartley             mailto:pjh@microplex.com   Tel: 1 604 444-4232
Microplex Systems Ltd.   http://www.microplex.com/  Tel: 1 800 665-7798
8525 Commerce Court                                 Fax: 1 604 444-4239
Burnaby, BC, Canada V5A 4N3
Article: 4266
Subject: Re: Q on Xilinx/Viewsim macros
From: ecp@focus-systems.on.ca (Eric Pearson)
Date: Mon, 7 Oct 1996 20:31:55 GMT
Links: << >>  << T >>  << A >>
In article <3254f51e.652454@news.alt.net>,
mis-spelt! <scannner@dial.pipex.com> wrote:
>
>Thanks all. Viewsim is a rather basic simulator. I wish it had some
>basic macros, like
>
>rept 256
> l rd-
> sim 1us
> h rd-
> sim 1us
>endm
>
>Peter.

I would try the built in command loops

(l rd-; sim 1us; h rd-; sim 1us)*256

Eric
-- 
Eric Pearson -- Focus Systems -- Waterloo, Ontario
     ecp@focus-systems.on.ca  (519) 746-4918
    "We Engineer Innovative Imaging Solutions"
Article: 4267
Subject: Re: Altera Checksums
From: Fred Giorgi <fgiorg@atl.com>
Date: Tue, 8 Oct 1996 00:01:26 GMT
Links: << >>  << T >>  << A >>
In article <325ade83.84274390@news.jf.intel.com> Richard Vireday,
Richard_Vireday@ccm.jf.intel.com writes:
>is no problem.  It is probably accountable by the different test
trim bits
>on these older EP1810 devices.

What are test trim bits?  All my parts are OTP. Can bits be left
in the programmer ram after a previous programming operation?

Let me restate the problem a little. 
The Data I/O programmer gives 8DD2 when reading all programmed
1810T parts,
Yet gives 8DD5 for some 1810 parts and 8DD2 for others.
Which of the 1810 devices have the turbo bits set?
Article: 4268
Subject: Viewlogic v4.1 Plotter.exe cmd line usage?
From: scannner@dial.pipex.com (mis-spelt!)
Date: Tue, 08 Oct 1996 09:38:51 GMT
Links: << >>  << T >>  << A >>
Hello,

I want to plot a lot of files, and would like to run the plotter.exe
program (part of the Xilinx/Viewlogic v.4.1 DOS suite) on its own.

I am sure this is possible, because this is what workview.exe does; it
just shells out to DOS and runs plotter.exe (which in turn invokes
placer.exe, it seems).

Doing "plotter -h" shows the command line usage, but it needs a
"metafile" input, and there appears to be no way of exporting a
metafile from Viewlogic.

Can anyone supply an example showing how to run plotter on its own,
plotting a schematic file?

Peter.
(address mis-spelt to stop junk mail)
Article: 4269
Subject: Require micrograph picture of an antifuse
From: andy@caprof.demon.co.uk (Andrew Valentine)
Date: Tue, 08 Oct 1996 10:43:29 GMT
Links: << >>  << T >>  << A >>
I have been trying to find a micrograph picture of a programmed
antifuse, but I have so far been unsuccessful.

Does anybody have or know where I can obtain a picture in electronic
form.

Many thanks

Andy

Article: 4270
Subject: COMMERCIAL: workshop on designing with FPGAs
From: devb@jazzmin.vnet.net (David Van den Bout)
Date: 8 Oct 1996 09:29:23 -0400
Links: << >>  << T >>  << A >>
_________________________________________________________________
   
  XESS Corp. presents a one-day workshop on 
  
  Designing with FPGAs

  for engineers and technicians who need a quick, hands-on
  introduction to programmable logic devices. 
  
  Dates: Oct. 30 or Nov. 12
  Time:  8:30 AM - 4:30 PM
  Place: Cybermaster Computer Training Center
         Room 202
         3948 Browning Place
         Raleigh, NC 27609
         
  For course outline, fees, and other information:
         go to http://www.xess.com/FPGA/course.html, or
         email to devb@xess.com, or
         call (800) 549-9377 or (919) 387-0076.
   
_________________________________________________________________
   
Motivation
   
   Field-programmable gate arrays (FPGAs) and programmable logic devices
   (PLDs) are chips that you can electronically program to build a
   digital logic system. No more wires to move around and solder! FPGAs
   and PLDs let you rapidly prototype your designs and can reduce the
   product design cycle. This course serves as a practical, hands-on
   introduction to FPGAs and PLDs.
   

What's In This For You? 

     * Get practical, hands-on experience with an FPGA and its
       development tools.
     * Learn what you need to start using FPGAs in your own designs.
     * No wasted time! Get up-to-speed on FPGAs in just one day.
     * Lay the foundation to move on to more advanced FPGA design
       techniques.
     * Receive your own software and hardware for designing with FPGAs.
     * Improve your design productivity.

-- 
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||
Article: 4271
Subject: Re: Reconfigurable hardware
From: husby@fnal.gov (Don Husby)
Date: 8 Oct 1996 13:44:05 GMT
Links: << >>  << T >>  << A >>

I've posted C-language simulations and schematics (Adobe Acrobat format)
for these algorithms at

     http://www-ese.fnal.gov/eseproj/trigger/arith.zip

This is about 18K bytes and includes:

    sq.c      Simulation of square roots
divide.c      Simulation of center-of-mass and short division
   com.pdf    Top level schematic for COM calculator
sqrt16.pdf    Schematic for square root

Article: 4272
Subject: Re: Reversible LFSR?
From: "Jorge P. Seidel" <jseidel@wlv.hp.com>
Date: Tue, 08 Oct 1996 08:55:33 -0700
Links: << >>  << T >>  << A >>
John L. Smith wrote:
> 
> LFSRs make good cheap address generators for FIFOs, but how about
> an address generator for a LIFO? Has anyone ever looked at an LFSR
> that can run in both directions? One bit is lost from the end of the
> shift register each clock, but perhaps there is an interesting
> combination of xor's that can produce the neccessary bits for shifting
> reversibly in either direction? Just posing the question...
> 
> --
> John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
> Univision Technologies, Inc. | those who are once-and-a-half witted
> 6 Fortune Dr.                | with the half-witted, because we
> Billerica, MA 01821-3917     | appreciate only a third part of their wit.
> jsmith@univision.com         | - Henry David Thoreau

Every LFSR is reversable.  When I worked for Xilinx we did some research on 
LFSR implementations for X-BLOX and that is one of the tidbits that we found.
I think credit goes to Peter Alfke for providing that insight, although he 
may have obtained the proof from another source.

Jorge Seidel
Pro-Cut Video
jseidel@pro-cut.com
Article: 4273
Subject: Reversible LFSR?
From: "John L. Smith" <jsmith@univision.com>
Date: Tue, 08 Oct 1996 09:11:21 -0700
Links: << >>  << T >>  << A >>
LFSRs make good cheap address generators for FIFOs, but how about
an address generator for a LIFO? Has anyone ever looked at an LFSR
that can run in both directions? One bit is lost from the end of the
shift register each clock, but perhaps there is an interesting
combination of xor's that can produce the neccessary bits for shifting
reversibly in either direction? Just posing the question...

-- 
John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
Univision Technologies, Inc. | those who are once-and-a-half witted
6 Fortune Dr.                | with the half-witted, because we
Billerica, MA 01821-3917     | appreciate only a third part of their wit.
jsmith@univision.com         | - Henry David Thoreau
Article: 4274
Subject: Re: Reversible LFSR?
From: "Jorge P. Seidel" <jseidel@wlv.hp.com>
Date: Tue, 08 Oct 1996 13:54:29 -0700
Links: << >>  << T >>  << A >>
John,

I'd like to add to my earlier post which was a bit terse.  I found
a reference in an e-mail I wrote back in those long ago days.  The
diagram is best viewed with a fixed-width font like courier.

/*******************************************************************/
Courtesy of Chuck Erickson at Xilinx:

It is always possible to have an up/down LFSR counter:

n=16

 +--- XOR_R=2,3,5,16                              XOR_L=1,3,4,16 --+
 |     +-----------------------------------------------------+     |
 |     |                                                     |     |
 +---->|      16-bit Right/Left Shift Register               |<----+
       |                                                     |
       +-----------------------------------------------------+
            |  |
Clock ------+  |
               |
R/L -----------+

The right shift sequence will exactly mirror the left shift sequence.

This is useful if you want to detect overflow by detecting '1' (which
is always the terminal count in a maximal length LFSR), but will be
counting up and down without caring about the magnitude of the count.
[The count in an LFSR is unweighted - that is, it is not easily 
possible to determine how far apart two patterns generated by the
counter are.]

/*******************************************************************/

Determining the taps for the reverse shift is not trivial, indeed, 
determining taps for LFSR's is always difficult, but for your 
application, since the length of the LFSR register will be fairly small,
it should be doable.  A list of taps can be found in most good math
handbooks, or I can send you a list of taps (clustered at the ends of
the LFSR for easy implementation in a LUT-based FPGA) for up to an 80
stage LFSR.

The limits of your LIFO would be '0' (the starting point) and '1' (the 
maximum value in an LFSR counter).  Both of these are easy to decode in 
short (less than 32-bit) LFSRs.  LUT-table based FPGAs are especially 
good where the taps are clustered in the first and last few registers, 
since you can fold the LFSR and have all of the necessary gates feed a 
single nearby LUT for the feedback XOR(XNOR).

Another interesting LFSR items is that if the number of stages in the 
LFSR is divisible by '8', then the number of taps *must* be greater than 
two.  That is, avoid making the number of registers in you LFSR an even
multiple of eight.  Tap patterns with only two taps are known for 
#stages in {2,3,4,5,6,7,9,10,11,15,17,18,20,21,22,23,25,28,29,31,33,35,
36,39,41,47,52,60,63} where #stages < 81.  You'd still need to find the 
"reverse" pattern.

John L. Smith wrote:
> 
> LFSRs make good cheap address generators for FIFOs, but how about
> an address generator for a LIFO? Has anyone ever looked at an LFSR
> that can run in both directions? One bit is lost from the end of the
> shift register each clock, but perhaps there is an interesting
> combination of xor's that can produce the neccessary bits for shifting
> reversibly in either direction? Just posing the question...
> 
> --
> John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
> Univision Technologies, Inc. | those who are once-and-a-half witted
> 6 Fortune Dr.                | with the half-witted, because we
> Billerica, MA 01821-3917     | appreciate only a third part of their wit.
> jsmith@univision.com         | - Henry David Thoreau


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