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Messages from 4700

Article: 4700
Subject: Re: In Search of Xilinx Routing Statistics
From: "Jon Harris" <jharris@spectralinc.com>
Date: 2 Dec 1996 19:02:58 GMT
Links: << >>  << T >>  << A >>
How about trying a simple test.  Keep adding 8 or 16-bit binary counters
until the thing won't place or route.  I realize this may be a little
time-consuming, but it should give you accurate real-world numbers.  If you
don't like adding binary counters because they are very much unlike the
logic you might want to add, use something else like LFSRs or decoders or
whatever.  Binary counters are convenient because they use both function
generators and CLB flip flops, come in a variety of sizes, and can be
placed and connected (and removed) quickly.

Lance Gin <c43lyg@dso.hac.com> wrote in article
<32A0FA6A.595@dso.hac.com>...
> I've just finished a Xilinx 4025E design that PPR required 99% CLB's to
> place/route. Utilization of CLB resources is a bit on the high side
> (80%+ FG's, 50%+ DFF's). I've looked at the placed design with FPLAN
> and PPR appears to have done an OK job given the speed requirements.
> There are, however, many CLB's where only a few internal resources are
> used. There are also many split nets (nets routed through CLB's)
reported.
> 
> I'd like to make an informed assessment of how much more logic I can
> *ADD* to the design. So far, I've got the following to work with:
<snip>
> Does anyone have any suggestions on other data I can use ?
> How would you go about making such an assessment ?

Article: 4701
Subject: Re: How to utilize XC4000e IOB FFs in Synopsys?
From: hari@syzygy.xilinx.com (Hari Vattikota)
Date: 2 Dec 1996 23:52:47 GMT
Links: << >>  << T >>  << A >>

In article <slrn59oha5.8ns.dietrich@krusty.htc.honeywell.com>,
dietrich@krusty.htc.honeywell.com (Paul Dietrich) writes:
|> On 26 Nov 1996 23:49:57 GMT, Hari Vattikota <hari@syzygy.xilinx.com>
|> wrote:
|> >
|> >In article <32998FFF.1466@martis.fi>, Mark Sandstrom
|> ><Mark.Sandstrom@martis.fi> writes:
|> >|> Has anyone managed to utilize Xilinx 4000e IOB FFs through
|> Synopsys?
|> >
|> >Please avoid global reset on the I/O flip-flops you want to infer
|> 
|> Why should global set/reset be avoided?  The 4000e supports GSR in
|> IOB
|> flip-flops.  I've used GSR in my designs and the flip-flops get
|> merged into
|> IOBs.  It's true that the IOB flip-flops don't have another reset
|> besides
|> GSR.

IOB flip-flops (in 4kE) don't have asynchronous reset. Synopsys
will synthesize flip-flops with asynchronous reset which get placed in the CLBs
Article: 4702
Subject: Re: Addressbility.
From: jahlstro@cisco.com (John Ahlstrom)
Date: 3 Dec 1996 00:19:10 GMT
Links: << >>  << T >>  << A >>
Now that you have the answer to the MINIMUM number of pins to address
any  amount of memory, maybe you can convince your boss that he
really wants something like a range of solutions for a range of
memory sizes and a range of numbers of pins.  For example, 
   can use 8-pins to address 2**72 bytes by using 8-pins 9 times
   can use 32 pins to address 2**96 bytes by using 32 pins 3 times
   ...

--
John Ahlstrom			jahlstrom@cisco.com
408-526-6025			Using Java to Decrease Entropy

   Any neural system sufficiently complex to generate the axioms 
   of arithmetic is too complex to be understood by itself.
                                       Kaekel's Conjecture

Michael Quinlan (mikeq@primenet.com) wrote:
: TukryopKim <acsapark@public.bta.net.cn> wrote:

: >Hi,
: >I am having duty of to make a algorithm which is able to access the
: >abundant memory with minimum address pin lines. Perhaps that memory has
: >about several Tera bytes capacity. Ofcouse this is a hypothesis. But my
: >boss require me it.
: >Probably it could be carried out with only new mathematical approach.
: >With group theory?

: If you know in advance how much memory you can have, you should be able =
: to
: address it with a single pin by sending the address serially instead of =
: in
: parallel. If you don't know how much memory you have, you might have to =
: use
: something like a stop bit (a signal 1.5 or 2 times the length of your
: normal signal) to mark the end of the address.

: -------------------------------------
: Michael A. Quinlan
: mikeq@primenet.com
: http://www.primenet.com/~mikeq
: "If it doesn't fit, you must acquit!"
: -------------------------------------


Article: 4703
Subject: Memory Requirements
From: joe@iscm.ulst.ac.uk (Joe Blake)
Date: 3 Dec 1996 10:08:59 GMT
Links: << >>  << T >>  << A >>
Hi 
I'm using Xilinx 5.1 version with Viewlogic as my schematic editor. I am 
designing neural networks and implementing them on a XC4013 FPGA. However I
am having trouble with memory requirements. When I go and run XMAKE on my 
schematic, I get an error during the X-BLOX routine stating that X-BLOX 
cannot process the design due to 
		Error 20244: Out of memory

I have about 600K of conventional memory available and 24M of RAM. Is this
not enough??  
Article: 4704
Subject: Re: Free Evaluation VHDL Editor
From: John Maher <jmaher@vhdl.com.au>
Date: 3 Dec 1996 11:55:51 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

---------------------------------987992337016
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset=us-ascii

Setanta ED runs under Windows 3.x/Windows 95 and Windows NT.

It will run un WABI on Unix boxes.

Regards,

John

---------------------------------987992337016
Content-Transfer-Encoding: 7bit
Content-Type: text/plain

Article: 4705
Subject: CFP: Reed-Muller 97 -- Int. Workshop on Function Representations
From: Jon Saul <Jon.Saul@comlab.ox.ac.uk>
Date: Tue, 03 Dec 1996 15:58:13 +0000
Links: << >>  << T >>  << A >>
Call For Papers
                                                                               
 
      	   3rd International Workshop on Applications of the
                Reed-Muller Expansion in Circuit Design 
			   (Reed-Muller 97)

		  In Cooperation with IFIP WG 10.5.

                                                                          
Place: Oxford University, Oxford, UK.
Date:  September 19-20, 1997
	just after ESSCIRC 97 (European Solid-State Circuits Conference)
		Southampton, UK, September 16-18 . 
	just before EuroDAC 97 (European Design Automation Conference)
		Dusseldorf, Germany, September 22-26 . 
 	

This workshop focuses on the application of new techniques in the
representation and realization of discrete functions. AND-EXOR based
representations are often simpler than AND-OR based representations,
and have other important properties. Decision diagrams are being
extensively studied, and have offered powerful new techniques for
verification and synthesis.  The goal of the workshop is to bring
together researchers in these and related fields to discuss new
approaches and results. The first workshop was held in September 1993,
in Hamburg, and the second in August 1995, in Tokyo.

A non restrictive list of interest includes the following topics:
	* Graph-based representation of logic functions 
           Binary decision diagrams,  Functional decision diagrams etc.
	* EXOR-based logic synthesis
           Reed-Muller expressions, Kronecker expressions,
           Exclusive-OR Sum-of-Products Expressions (ESOPs), 
	   Multi-level circuits
	* Spectral techniques
	* New representations for discrete functions
	* Complexity theory
           AND-OR vs. AND-EXOR 
	* Easily testable circuits using EXORs
	* Implementation in silicon (FPLDs, FPGAs,...)
	* Applications, both inside and outside circuit design. 

Chairman:                              	Co-Chairman:
Jonathan Saul                         	Udo Kebschull
Oxford University,			FZI 
UK.					Germany.

Authors are invited to submit, by April 4, 1997, 10 copies of draft
papers not exceeding 20 pages, together with a signed statement that
if the paper is accepted the author will present it at the
workshop. Notifications of acceptance will be sent by June 20, 1997. A
workshop handout will be distributed to the workshop attendees, and it
is planned to publish selected papers in a more widely distributed
form. The camera-ready paper must be received by August 1, 1997.

Submissions should be sent to:
Jonathan Saul, Oxford University Computing Laboratory, Wolfson Building, 
Parks Road, Oxford OX1 3QD, UK.						
or
Udo Kebschull, Forschungszentrum Informatik (FZI),
Haid-und-Neu-str. 10-14, 76131 Karlsruhe, Germany

Enquiries :
Miss Frances Page
Oxford University Computing Laboratory
Wolfson Building
Parks Road
Oxford OX1 3QD, UK.
Tel: +44 1865 283505/273838
Fax: +44 1865 273839

Further details will become available on the website: 
http://www.comlab.ox.ac.uk/oucl/users/jon.saul/ReedMuller97.html

Program Committee:

Bernd Becker        	University of Freiburg, Germany.
Jon T. Butler       	Naval Postgraduate School, USA.
Olivier Coudert		Synopsys, USA.
Rolf Drechsler		University of Freiburg, Germany. 
Masahiro Fujita     	Fujitsu Laboratories of America, USA.
Kiyoshi Furuya      	Chuo University, Japan. 
Udo Kebschull       	Forschungszentrum Informatik (FZI), Germany.
Tomasz Kozlowski	University of Zielona Gora, Poland. 
GueeSang Lee		Chonnam National University, Korea. 
Margaret Marek-Sadowska	University of California, Santa Barbara, USA.
Christoph Meinel    	University Trier, Germany.
Michael Miller		University of Victoria, Canada.
Shin-Ichi Minato    	NTT LSI Laboratories, Japan.
Marek A. Perkowski  	Portland State University, USA.
Tsutomu Sasao       	Kyushu Institute of Technology, Japan.
Jonathan Saul 		University of Oxford, UK.
Endric Schubert		Exemplar Logic, USA.
Article: 4706
Subject: Re: How to use Xilinx ?
From: cong shiping <vn5s-cng@asahi-net.or.jp>
Date: Wed, 04 Dec 1996 15:02:45 +0900
Links: << >>  << T >>  << A >>
Steve Wiseman wrote:
>   what synthesis tools are you using? 

I'm using ACTIVE CAD 2.2 and Xilinx Foundation Series Version 6.0.1 .

Good luck !

Shelby Cong
Article: 4707
Subject: Re: Cypress CPLD, pASIC380 Programmer
From: cong shiping <vn5s-cng@asahi-net.or.jp>
Date: Wed, 04 Dec 1996 15:15:44 +0900
Links: << >>  << T >>  << A >>
Hans Tiggeler wrote:
> 
> Can anybody tell me if there is a low-cost programmer for Cypress CPLD and
> pASIC380 family?
> 
> Their VHDL synthesis software is amazingly cheap (32 Pounds for Warp2
> Version4.0 + VHDL synthesis book). The Cypress databook describes the Impulse
> 3 programmer which is based on an OEM version of the DATA I/O ChipLab
> programmer. Those of you who know this programmer also know is far from
> low-cost.
> 

Even the software is cheap , but the device can be written only time . Maybe
Lattice's device is better , because their software(not VHDL) is cheap and 
needn't a speical programmer .

Cong
Article: 4708
Subject: Re: Memory Requirements
From: DTHIBAUL <DTHIBAUL@mailgw.sanders.lockheed.com>
Date: Wed, 04 Dec 1996 12:57:41 -0800
Links: << >>  << T >>  << A >>
Joe Blake wrote:
> 
> Hi
> I'm using Xilinx 5.1 version with Viewlogic as my schematic editor. I am

>                 Error 20244: Out of memory
> 
> I have about 600K of conventional memory available and 24M of RAM. Is this
> not enough??

  I ran into problems with 32Meg on a full 4013 design as well as a 
4025e.  I upgraded to 64Meg and a lot of "interesting" problems 
just disappeared.

Dave Thibault

Speaking for myself (of course).
Article: 4709
Subject: Re: What Does ASIC Stand For?
From: jcooley@world.std.com (John Cooley)
Date: Wed, 4 Dec 1996 21:26:51 GMT
Links: << >>  << T >>  << A >>
simonson@skopen.dseg.ti.com (Kevin M Simonson) writes:

>     I'm feeling really ignorant right now.  Is there anyone who can tell
>me what ASIC stands for?  Thanks.
> 
>                                     ---Kevin Simonson

Aren't "ASICs" a brand of tennis shoe?   :^)


(It could also stand for "Application Specific Integrated Circuit",
too, I think!)
                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 4599 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

Article: 4710
Subject: Re: FPGA Gate Counts: No Truth in Advertising?
From: vincent@kodak.com (John Vincent)
Date: 4 Dec 1996 22:08:41 GMT
Links: << >>  << T >>  << A >>

It appears that discussion on this thread has died out, but I'll add my two
cents worth. The problem here is another classic case of mononumerousis,
that dreaded disease most common to marketing and management. Device
capacity is a complex quantity of several dimensions and cannot possibly
be expected to be adequately described by a single number. This has been
true since PLDs were first invented, when device architectures were fairly
simple and regular, before the myriad of special functions and architectural
enhancements. This has only added additional dimensions to an already very
complex problem. The best one can hope for when taking a simplistic approach
to determining device capacity is to derive some statistical measures and
to determine reasonable practical limits. And vendors are beginning to do
this. At least one is even openly describing the assumptions and equations
used to obtain the "nominal" device capacity ratings and ranges for
practical applications. This is definitely a step in the right direction.
It is important for the designer to realize what these numbers mean and
how to use them. One way is consider them in a somewaht analogous fashion
to component power ratings. A good designer will de-rate them in order to
achive better reliability. The principle hold here as well, but the derating
factor isa bit larger....
 

************************************************************************
 *******          *********
*******        *************   	John Vincent
******      ****************   	Eastman Kodak Company   
*****    *******************   	Equipment & Software Platform Center
****  **********************   	Digital Technology Center
*** ************************   	Elmgrove Plant Bldg. 1
****  **********************   	Rochester New York 14653-5211
*****    *******************   	Phone:  716-726-4607
******      ****************   	Fax:    716-726-7131
*******        *************   	email:  vincent@kodak.com
 *******          *********
************************************************************************


=======================================================================
  Anything I say may or may not be my opinion, but certainly is not
  the opinion of my kind and generous Internet-enabling employer.
                     (How's that sound, boss?)
=====================================================================

Article: 4711
Subject: US LA *Job Post* Vhdl, FPGA, Mentor Engineer Needed to $75/hr
From: voltj@ix.netcom.com (Jason Tayles)
Date: Thu, 05 Dec 1996 07:06:41 GMT
Links: << >>  << T >>  << A >>
Volt Services Group currently has an contract opening to work in the
Los Angeles area for a VHDL engineer.

Tasks include FPGA Design, Verify Xilinx 4000, Board level debuf and
verification

Tools: Design architecture, Quicksim, X Delay.

Rate to $75/hr DOE
Position is in LA and must be done onsite!
Length:  Approx 2 months.

Contact:


Jason J. Tayles

Volt Regional 
E-mail: voltj@ix.netcom.com
www.volt-tech.com
V:800.422.8777
V 602.955.8717 (outside US)
F 602.955.8536
Article: 4712
Subject: Re: Looking for hc0324
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 5 Dec 1996 17:04:48 GMT
Links: << >>  << T >>  << A >>
In article <E1y6pA.Bv6@nonexistent.com> kardos@mail.matav.hu writes:
>   Hi!
>
>   Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know,
>where to search for it ? (AltaVista couldn't find it.)
>   Please answer in e-mail too ! Thanks for any hint.
>
>*****************************
>Botond Kardos
>kardos@mail.matav.hu

Yes, I know what this chip is. It is the control chip inside a software
security block (dongle), right next to a 93C46K ( a serial EEPROM), and an
HC00 (quad CMOS nand gate).  There are also 17 surface mount resistors, 7
capacitors, and 4 diodes near by. I hope you aren't trying to crack it. 


Article: 4713
Subject: Re: XACT under WinNT is very slow
From: Marc Baker <marc.baker@xilinx.com>
Date: Thu, 05 Dec 1996 09:10:11 -0800
Links: << >>  << T >>  << A >>
The latest Xilinx XCELL Newsletter has an article on running
XACT under Windows NT.  You can find the Acrobat file at
http://www.xilinx.com/xcell/xl23/xl23_20.pdf

The article references the following patch files available
from our BBS or FTP site:

ftp://ftp.xilinx.com/pub/swhelp/xact-pc/prep_nt.zip
ftp://ftp.xilinx.com/pub/swhelp/xact-pc/rainport.exe

The complete table of contents for the latest XCELL is at
http://www.xilinx.com/xcell/xcell23.htm


******************************************************
      Marc Baker              marc.baker@xilinx.com   
      Competitive Marketing and Applications          
      Phone: (408) 879-5375   Fax: (408) 879-4676     
      Xilinx, Inc.                                    
      2100 Logic Drive       
http://www.xilinx.com                        
      San Jose, CA  95124                             
******************************************************
Article: 4714
Subject: Announcement: public release of POLIS-0.2, an embedded system design software
From: The POLIS team <polis@ic.eecs.berkeley.edu>
Date: Thu, 05 Dec 1996 13:45:08 -0800
Links: << >>  << T >>  << A >>
Dear colleague,

It is our pleasure to announce the public availability of POLIS-v0.2
co-design environment for control-dominated embedded systems.
 
POLIS offers an integrated interactive environment for specification,
co-simulation, formal verification, and synthesis of embedded systems
implemented as a mix of hardware and software components.

Version 0.2 offer many add features, including brand new microcontroller
resource library handling and ptolemy simulation debugging.  Please see
REL_NOTES for more detail.
 
Most of the information about POLIS, including pointers to source and
object code (for various CPUs and OSes) is available at our WEB site
http://www-cad.eecs.berkeley.edu/Respep/Research/hsc/abstract.html
 
The software is available under the usual copyright rules of the 
University of California
(see also http://www-cad.eecs.berkeley.edu:80/copyright.html).
 
If you are interested, but do not have WEB access, please contact us via
e-mail at polis-questions@ic.eecs.berkeley.edu.

 
Best regards,
                the POLIS team
(currently including Felice Balarin, Massimiliano Chiodo, Alberto
Ferrari, Paolo Giusto, Harry Hsieh, Attila Jurecska, Marcello Lajolo,
Luciano Lavagno, Claudio Passerone, Claudio Sansoe', Ellen Sentovich,
Marco Sgroi, Kei Suzuki, Bassam Tabbara, Reinhard von Hanxleden, and
Alberto Sangiovanni-Vincentelli)
Article: 4715
Subject: Re: Looking for hc0324
From: bwilson@newshost (Bob Wilson)
Date: 5 Dec 1996 22:22:21 GMT
Links: << >>  << T >>  << A >>
kardos@mail.matav.hu wrote:
:    Hi!

:    Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know,
: where to search for it ? (AltaVista couldn't find it.)
:    Please answer in e-mail too ! Thanks for any hint.

Soooooo!! Trying to duplicate a hardware copyright protection key are we???

As I understand it the chip is a custom device (full name: 74HC032AM).

Bob.

Article: 4716
Subject: Looking for hc0324
From: kardos@mail.matav.hu
Date: Thu, 5 Dec 1996 22:50:30 GMT
Links: << >>  << T >>  << A >>
   Hi!

   Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know,
where to search for it ? (AltaVista couldn't find it.)
   Please answer in e-mail too ! Thanks for any hint.

*****************************
Botond Kardos
kardos@mail.matav.hu

Article: 4717
Subject: Re: Looking for hc0324
From: phony@see.sig.for.real
Date: Thu, 05 Dec 1996 22:59:19 GMT
Links: << >>  << T >>  << A >>
fliptron@netcom.com (Philip Freidin) wrote:

>In article <E1y6pA.Bv6@nonexistent.com> kardos@mail.matav.hu writes:
>>   Hi!
>>
>>   Have anybody ever heard of a circuit named 74hc0324 or 74hco324 ? Or does anybody know,
>>where to search for it ? (AltaVista couldn't find it.)
>>   Please answer in e-mail too ! Thanks for any hint.
>
>Yes, I know what this chip is. It is the control chip inside a software
>security block (dongle), right next to a 93C46K ( a serial EEPROM), and an
>HC00 (quad CMOS nand gate).  There are also 17 surface mount resistors, 7
>capacitors, and 4 diodes near by. I hope you aren't trying to crack it. 
>
 Hacking aside, is that chip a custom part for that specific dongle,
or a merchant part produced for general sale? If the latter, it might
have wider application than just security blocks.










--  Dave Brooks    <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
    "From" line rigged to foil spambots: daveb <at> iinet.net.au
Article: 4718
Subject: Re: Memory Requirements
From: wright@iecorp.com (Jason T. Wright)
Date: Thu, 05 Dec 1996 23:58:10 GMT
Links: << >>  << T >>  << A >>
joe@iscm.ulst.ac.uk (Joe Blake) wrote:

>Hi 
>I'm using Xilinx 5.1 version with Viewlogic as my schematic editor. I am 
>designing neural networks and implementing them on a XC4013 FPGA. However I
>am having trouble with memory requirements. When I go and run XMAKE on my 
>schematic, I get an error during the X-BLOX routine stating that X-BLOX 
>cannot process the design due to 
>		Error 20244: Out of memory
>
>I have about 600K of conventional memory available and 24M of RAM. Is this
>not enough??  

Not if you are using any significant portion of the chip's resources.
Even for the 4010, you should have 32 MBytes.  (I used 24 MB for some
designs, but some REQUIRED more memory--even with no XBLOX modules.)

Jason T. Wright
Article: 4719
Subject: what is "token chain"?
From: flxchen@smtp.dlink.com.tw (Felix K.C. CHEN)
Date: Fri, 6 Dec 1996 09:15:42 +800
Links: << >>  << T >>  << A >>
Dear Friends,

I read the terminology "token chain" in an article, but
I do not know waht it is?  That article is about the
FIFO control mechanism.

Could anyone give me a reference or explanation?

Best wishes,

Felix K.C. CHEN
Article: 4720
Subject: Or- gated clock solution?
From: "Jae-Ho Shin" <jhshin@mjl.co.kr>
Date: 6 Dec 1996 07:07:29 GMT
Links: << >>  << T >>  << A >>
Hi.
I'm using FPGAs.
In a FPGA, I want to use OR gated clock to flipflop.
For And gated clock, I convert this to enable flip-flop to remove glitch.
But, I can not find Or gated clock conversion which is glitch free.
Is thee anybody knows glitch free OR gated clock usage?

Thanks.

============================================================
Jae-Ho Shin                                     MJL Korea,Ltd
Section Chief/FAE                          19th Fl. Korea Investment Trust
Bldg.
Field Application Engineering    27-1 Youido-Dong, Yungdeungpo-Ku
Section  2                                           Seoul, Korea 150-010
Electronic Component                   Tel: +82(2)767-2292, -2200, Fax-2221
Business Department                    Email: jhshin@mjl.co.kr
                                                                          
http://www.mjl.co.kr
============================================================
Article: 4721
Subject: ASICs Vs. FPGA in Safety Critical Apps.
From: Kayvon Irani <kirani@cinenet.net>
Date: Thu, 05 Dec 1996 23:14:31 -0800
Links: << >>  << T >>  << A >>
Hi everyone:

	Just wondering if anyone out there has first hand experience or cares to comment
	on the use of ASICs and FPGAs in safety critical applications such as in 	
	passanger airplanes. Are the FPGAs more prone to failure by their virtue of
	being "programmable" and because they have unused dangling gates on the silicon?
	Any one used any particular FPGAs on FAA certified equipment?
	

	Regards,
	Kayvon Irani
	Los Angeles, ca
Article: 4722
Subject: Name this chip !!
From: Hamilton <hamilton@dimensional.com>
Date: Fri, 06 Dec 1996 07:48:52 -0700
Links: << >>  << T >>  << A >>
Does anyone know what this chip is???


	   @M	<-- Motorola Logo
	SC419510FU
	F66Y
	HLKH9518

This chip is inside a Sony Playstation memory cartridge next to
a AT29LV010 eeprom.

thanks
Article: 4723
Subject: Re: XACT under WinNT is very slow
From: Scott Kroeger <Scott.Kroeger@mail.mei.com>
Date: Fri, 06 Dec 1996 09:31:39 -0600
Links: << >>  << T >>  << A >>
Marc Baker wrote:
> 
> The latest Xilinx XCELL Newsletter has an article on running
> XACT under Windows NT.  You can find the Acrobat file at
> http://www.xilinx.com/xcell/xl23/xl23_20.pdf
> 
> The article references the following patch files available
> from our BBS or FTP site:
> 
> ftp://ftp.xilinx.com/pub/swhelp/xact-pc/prep_nt.zip
> ftp://ftp.xilinx.com/pub/swhelp/xact-pc/rainport.exe

That's where I started and it doesn't work (under 3.51 or 4.0).  The
only solution that worked for me was to get a 2nd PC and load Win3.1 on
it.  The solution for my colleague was Actel :(

Regards,
Scott
Article: 4724
Subject: FIND OUT HOW $$$ EASY MONEY HERE
From: swgarb@aol.com
Date: 6 Dec 1996 16:47:27 GMT
Links: << >>  << T >>  << A >>
It sucks to be poor.  Everyone knows this to be true, but if you are
willing
to take 5 minutes, 5 stamps & 5 dollars & apply it to what you read below,
being poor will not be a problem anymore.  This is the best way of raising
money, in an easy, honest & fast way.  Oh, & it's legal too.  In essence,
you
are contributing to vast corporate mailing lists, simply by helping to
establish a new network.  You send out 5 envelopes & 5 stamps.  You will
only
receive money.  Read this message to completely understand the process &
begin making money today.

The process is very simple & it consists of 3 EASY steps:

STEP 1:  Get 5 separate pieces of paper & write the following on each
sheet
of paper..'PLEASE PUT ME ON YOUR MAILING LIST.  YOU ARE NUMBER 4."  Also
include your address.  Get five $1 bills and place ONE inside each piece
of
paper and fold each piece of paper so the bill will not be seen in the
envelope.  Put one paper inside the envelope and seal it.  Do the same for
all 5.  You should now have 5 envelopes sealed, EACH have a piece of paper
&
a $1 bill stuffed inside of the paper.  What you are doing is creating a
mailing list service, this is PERFECTLY LEGAL.  Now then, mail the 5
envelopes with paper and $1 in each to the following 5 addresses:

1.          M.NAWLO, 27 CROWS NEST LN #17, Danbury, CT  06810

2.          J. Simpson, Brks 447 Box 769, NSA Memphis, TN  38054

3.          Mitch Enterprises, 651 East Holmes, E. Lansing, MI  48825

4.          E.W. Mikulewicz, 7150 W. Rivulet Dr., Tucson, AZ  85743

5.          M.Compton, 1101 Lorick Rd, Blythewood, SC  29016

STEP 2:  Now take the #1 name off the list that you see above, move the
other
4 names up (5 becomes 4, 4 becomes 3, etc.) and put YOUR NAME) as number 5
on
the list.  You can slightly alter this article if you need to, editing
what
you need to edit.

STEP 3:  Post you amended article (with you name at #5) to at least 200
news
groups or mail to at least 300 individuals.  Use the phone book if you
need
to!  The idea is to appeal to as many people like yourself, who need
money,
and are creative enough to make it.  
When you begin to receive names & money, save the names in a file, a shoe
box, your underwear drawer, whatever, just as long as you save them.  The
people who send you money are paying you to save their name, essentially,
as
proff that you gave them this opportunity.  By saving the names, the
business
baecomes legal, and you hold a record of the people you licensed to
continue
the chain.

If you have Netscape 3.0, and want to take the news group option, follow
the
instructions at the bottom of the next page.

THIS SYSTEM WORKS!!!
You only need an average return of 2.5%, that is FIVE PEOPLE, to make more
than $50,000.
Out of every 200 postings, let's say I ONLY receive 5 replies, which is
actually VERY LOW.  So I made 5 dollars with my name at #5.  Now then,
each
person who just sent me $1 makes, say only 200 postings, now with your
name
at #4, WHICH IS A TOTAL OF 1000 POSTINGS, not including yours too.  50
people
send you $1 now (simple math kids, that's $50 you just made!)  Now, then
your
new 50 agents post 200 each with YOUR NAME AT NUMBER 3, OR 10,000 POSTINGS
(50X200).  Average return is 500 at $1 each is $500.  They make 200
postings
each with your name at number 2, which is 100,000 postings, which is 5,000
returns at $1 each, which is $5,000 dollars!  
And finally, 5,000 people make 200 postings each with YOUR NAME AT NUMBER
1.
YOU NOW GET A RETURN OF $50,000 BEFORE YOUR NAME DROPS OFF THE LIST.  AND
THAT'S IF EVERYONE MAKES 200 POSTINGS ONLY, AND IF ONLY 5 PERSONS RESPONS
OR
AN AVERY RESPONSE OF 2.5 PERCENT!!!

Read the following quote:

"Look, it's only $5, five stamps and about 5 minutes.  I read this article
&
figured that I would at least make back my investment.  I'm glad I took
the
time because the money is helping me get out of debt, into a decent cart &
OUT OF DORM LIFE FOREVER!  It is amazing at this stage in life what $50k
can
do to make everything about college seem easier.  I crossed the 25K mark
last
week and have people really pissed about sorting so much mail, and the
bank
seems to believe that I am ripping off change machines, or one hell of a
waiter for all of the one dollar bills I bring in.  I don't thing anyone
could ever need any more convincing that this.  I wish you the best for
taking part and good luck.
                                                                    
Regards,
                                                                    
Steven
Shaw
                                                                      UCLA
Sophomore"                     

If you have Netscape 3.0, and want to take the news group option, follow
these instructions:

1) go to the window file & pull down to News.  Click on any news group
like
normal, THEN click on 'TO NEWS', which is on the far left when you're in
the
newsgroups page.  This will bring up a box to type a message in.
2)  Leave the newsgroup box like it is, CHANGE the subject box to
something
flashy like, "NEED CASH $$$ READ HERE $$$" or "FAST CASH"!!!  
3)  Tab once and you should be ready to type.  Now, retype (only once)
THIS
whole article WORD FOR WORD,  except to insert your name at #5, and  to
remove #1 off the list, plus any other small change you think you need to
make.  Keep almost all of the the SAME!  
4)  When you're done typine the WHOLE article, click on FILE in THIS BOX,
RIGHT ABOVE SEND, NOT WHERE IS SAYS NETSCAPE NEWS ON THE FIRST BOX.
click on SAVE AS when you're under FILE.  Save your article as a text file
to
your C: or A: drive.  DO NOT SENT OR PORT YOUR ARTICLIE UNTIL YOU DO THIS.
Once saved, move on to number 5 below.
5)  If you still have all of lyour text, send or port to this newsgroup
now
by just clicking sent, which is right below FILE, and right above Cc:
6)  Here's were you're going to post all 200.  OK, click on any newsgroup
then click on 'TO NEWS', again in the top left corner.  Leave the
NEWSGROUPS
BOX alone again, put a flashy subject title in the SUBJECT BOX, hit TAB
once
so you're in the body of the message, and then click on ATTACHMENTS, which
is
below the SUBJECT BOX.  You will get another box to come up.  Click on
ATTACH
FILE, then find YOUR file that you saved; click once on the file and then
click OPEN; now click on OK; if you did this right you should see your
file
name in the attachments box and it will be shaded green.
7)  That's it.  Each time you do this, all you have to do is type in a
different newsgroup, so that way, it posts to 200 DIFFERENT newsgroups,
you
see?  Now you just have 199 to go!!  (Don't worry, each one takes about 30
seconds once you get used to it) REMEMBER 200 IS A MINIMUM.  The more you
post to, the more money you will make.  




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