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Messages from 4825

Article: 4825
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: Ray Andraka <randraka@ids.net>
Date: Wed, 18 Dec 1996 00:18:55 -0800
Links: << >>  << T >>  << A >>
Brad Taylor wrote:
> 
> This has got me thinking. Isn't the real problem undetected failures?
> With an SRAM based FPGA, the logic can be tested on boot.  This cannot
> be done with an ASIC.  Also, it is easy to build redundant systems with
> FPGAs, you just parallel two FPGAs and run only one at a time. Given the
> apparent opportunity to increase reliability with intelligent use of
> FPGAs,  doesn't it make sense to figure out how to use them, how to
> qualify them, and to develop the methodologies necessary. As you say
> peoples lives are at stake.

My point exactly!  Although the ASIC can be tested to a degree assuming
a sufficient BIST, it is alot easier  to test an FPGA then monitor its
condition with periodic readbacks of the configuration program.  

Based on the arguments I've seen to date against using SRAM based FPGAs,
it seems the real reason is ignorance of the device characteristics and
correct configuration methods.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 4826
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: "Alvin E. Toda" <aet@lava.net>
Date: Tue, 17 Dec 1996 22:23:50 -1000
Links: << >>  << T >>  << A >>
On 18 Dec 1996, Jan Vorbrueggen wrote:

> jet@eskimo.com (James Thiele) writes:
> 
> > This leads to a total fleet lifetime of 100,000,000 (10^8) hours.
> > Thus a 10 FIT part has a significant chance of failing in that
> > time period.  And it is almost certain that a system of 100 such
> > parts would fail.  
> > 
> > If the failure of such a part causes the crash of a comercial
> > airliner even once during the lifetime of the system, I would
> > consider that unacceptable.
> 
> Is this a reasonable target, compared to other components of the system
> (especially the human part)? That is, aren't we holding the electronic
> component to (nuch?) higher standards than the rest of the system, and to much
> higher standards than we historically tolerated in a system of this type?
> 
> 	Jan
> 
> 

Isn't this the point of selecting "safe" parts. Note that most systems
and made up of more than "100 such parts". Certainly, the overall safety
of system must be judged from the reliability of ALL it's parts, including
the pilots and all the tests and checks that are done. Pilots chosen 
seem to have a lot of physical and mental skills that most of us don't
have, such are better eyesight, better body condition, etc. 

Even here you have the backup of a co-pilot. If you look
at the whole system, certainly there are airplane incidents each year
but the accident rate is probably a lot lower than the auto accident 
rate. It's a lot safer to ride a plane than a car.

The problem for the designer is that he or she must also claim high
reliability (preferably backed up with some data at a design review)
of the bad load problem. This is for all situations over many packages.
This is probably not worth their time except under some unusual
circumstances. 

########################################################################
Alvin E. Toda				aet@lava.net
sr. engineer				Phone: 1-808-455-1331

2-Sigma			  	WEB: http://www.lava.net/~aet/2-sigma.html
1363-A Hoowali St.
Pearl City, Hawaii, USA

Article: 4827
Subject: Re: How to use Xilinx ?
From: Andrew Papageorgiou <ap@smte.demon.co.uk>
Date: Wed, 18 Dec 1996 11:39:20 +0000
Links: << >>  << T >>  << A >>
Hi,

I've found the easiest most flexible solution is to use a constraint
file (.cst). This allows your constraints such as time specs and pin
allocation to be done in a separate file which is easier to modify
than the full VHDL code.

See the Xilinx online documentation, Libraries, chapter 4.

Hope this helps.

        Andy



In article <32B225FB.167EB0E7@exemplar.com>, David Emrich
<emrich@exemplar.com> writes
>Cong shiping wrote:
>> 
>> Hi all,
>> 
>> I'm using Xilinx's XACT to design FPGA . I haven't any experience with 
>Xilinx's
>> FPGA and have some problems . Hope you help me .
>> 
>> 1. When use VHDL
>>    When use VHDL to design a FPGA , how to assign the pin number ? I heard of
>>    it is disable to assign the pin nubmer without using schematic .Is it right 
>?
>
>If you are using Exemplar's Leonardo, or Galileo synthesis tool you can do it 
>this
>way (cut & pasted from one of our application notes):
>
>   TYPE string_array IS ARRAY (natural RANGE<>, natural RANGE <>) OF character;  
>   ATTRIBUTE pin_number : string;
>   ATTRIBUTE array_pin_number : string_array;
>   ATTRIBUTE array_pin_number OF y : signal IS ("P20", "P21", "P22", "P23");
>   ATTRIBUTE pin_number OF i : signal IS "P10";
>
>
-- 
Andrew Papageorgiou
Hardware Designer

Sundance Multiprocessor Technology
httw://www.sundance.com/
Article: 4828
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: walton@emc.com (John Walton)
Date: 18 Dec 1996 08:02:43 -0500
Links: << >>  << T >>  << A >>

In article <32B7A8EF.20BF@ids.net>, Brad Taylor wrote:
|> > 
|> > This has got me thinking. Isn't the real problem undetected failures?
|> > With an SRAM based FPGA, the logic can be tested on boot.  This cannot
|> > be done with an ASIC.  Also, it is easy to build redundant systems with

Of course it can, you have _much_more_ freedom in a mask programmable, than
FPGA. And many more gates to build test logic from.

|> > FPGAs, you just parallel two FPGAs and run only one at a time. Given the

Pop open a IBM SP2 sometime you'll see just such a use of redundancy on the package
level. Or pick up their white paper. The switching network is constructed of 
doubled up packages. 

|> > apparent opportunity to increase reliability with intelligent use of
|> > FPGAs,  doesn't it make sense to figure out how to use them, how to
|> > qualify them, and to develop the methodologies necessary. As you say
|> > peoples lives are at stake.
|> 
Article: 4829
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: walton@emc.com (John Walton)
Date: 18 Dec 1996 08:14:32 -0500
Links: << >>  << T >>  << A >>

In article <1996Dec18.074724@emc.com>, walton@emc.com (John Walton) writes:
|> 
|> In article <32B7A8EF.20BF@ids.net>, Brad Taylor wrote:
|> |> > 
|> |> > This has got me thinking. Isn't the real problem undetected failures?
|> |> > With an SRAM based FPGA, the logic can be tested on boot.  This cannot
|> |> > be done with an ASIC.  Also, it is easy to build redundant systems with
|> 
|> Of course it can, you have _much_more_ freedom in a mask programmable, than
|> FPGA. And many more gates to build test logic from.
|> 
|> |> > FPGAs, you just parallel two FPGAs and run only one at a time. Given the
|> 
|> Pop open a IBM SP2 sometime you'll see just such a use of redundancy on the package
|> level. Or pick up their white paper. The switching network is constructed of 
|> doubled up packages. 

Oops! sorry, forgot,  this application _did_not_ feature FPGAs.

|> 
|> |> > apparent opportunity to increase reliability with intelligent use of
|> |> > FPGAs,  doesn't it make sense to figure out how to use them, how to
|> |> > qualify them, and to develop the methodologies necessary. As you say
|> |> > peoples lives are at stake.
|> |> 
Article: 4830
Subject: PLD
From: Tom Smythers <tesmythers@transys.rockwell.com>
Date: Wed, 18 Dec 1996 11:08:17 -0800
Links: << >>  << T >>  << A >>
Is this an appropriate newsgroup to post PLD questions? (I have a
problem with a Lattice PLD)

Tom Smythers
Article: 4831
Subject: Help: FPGA for fast digital signal processing
From: gomez66@eucmax.sim.ucm.es
Date: 18 Dec 96 20:21:18 GMT
Links: << >>  << T >>  << A >>
Hi!



Does anyone know any architecture based on FPGA for a

fast digital signal processing?



Please, answer me at the below address. Thank you.



Email: jangomez@unex.es

URL:   http://maxwell.unex.es/CALD
Article: 4832
Subject: Proper target for design
From: Mark Norton <mnorton@redwood.dn.hac.com>
Date: Wed, 18 Dec 1996 15:09:12 -0700
Links: << >>  << T >>  << A >>
Hello, first time designer here.

I've got an application that takes a serial 200 MBit/sec data stream
that has a frame length of about 1024 bits give or take a few,
frame sync, and is time-division multiplexed.  The task is to
frame sync and then deinterleave the data depending on the TDMX
mode we're in (there are a few).

I've done a little research so far, and there are devices by
both Actel and Xilinx that will do the trick in that regard.
I believe both are FPGA's

I understand the difference in generalitiex between CPLD's and 
FPGA's, but is one better than the other for specific applications?
For my application there isn't a lot of high level stuff going
on; other than the frame sync process, I'm counting bits and 
sending them off to different outputs.  As I understand it,
CPLD's have a lot of simpler blocks with a very deterministic
prop delay setup, while FPGA's have more complex blocks but 
the prop delay's are not quite so rigid.  

Am I looking in the wrong direction here towards FPGA's over
CPLD's?  Are the CPLD's faster?  Am I totally wrong about counting
bits being a low level sort of thing (as compared in my mind to
trying to do an FFT).

These are the questions I'm trying to figure out.  If you've got
any experience to provide in the matter, I'd really appreciate your
insight.  I'll try to keep an eye on this newsgroup but it's ont
part of my daily routine, so if you email me, I have a more likely
chance of getting it.  I can be reached at mnorton@redwood.dn.hac.com.

Regards
Mark Norton
-- 
========================================================================
Mark Norton                        Hughes Information Technology Company
mnorton@redwood.dn.hac.com     Ph: 303-344-6860         Aurora, Colorado
========================================================================
Article: 4833
Subject: Re: Exemplar's Leonardo on Linux
From: phony@see.sig.for.real
Date: Thu, 19 Dec 1996 00:20:02 GMT
Links: << >>  << T >>  << A >>
David Emrich <emrich@exemplar.com> wrote:

:Phil Ptkwt Kristin wrote:
:> I've heard that Exemplar will release a Linux version of their Leonardo
:> synthesis tool for Linux early next year.  Has anyone else heard this?
:> It would be good if someone from Exemplar could comment on this.
:
:The port is complete for Leonardo 4.0.3.  Available in January 97.
:
[snip]
:> 
:> If this is true it is very good news for the Linux engineering community.
:> Leonardo is a popular synthesis tool on NT, having it ported to Linux
:> could very well be the catalyst that causes other EDA vendors to follow
:> suit.
:> 
[snip]

 IMHO, cause for some celebration! The day a major application vendor
does a port to Linux, Linux starts getting credibility in the
commercial (not just academic) zone. The first brick knocked out of
the M$/Intel monolith :-)

Article: 4834
Subject: design should fit, but it doesn't
From: eric@wolf359.exile.org (Eric Edwards)
Date: Thu, 19 Dec 1996 03:14:31 GMT
Links: << >>  << T >>  << A >>
'Got a design, written in verilog of about 1000 lines.  Synopsys reports
3500 gates, at least when targeting the, not very usefull ASIC library
that the university uses.  My normal synthesis tool, Asyl+ doesn't report
gate counts.

For a variety of reasons, I'm trying to fit this to an Altera Flext 10K10
FPGA.  Should be easy, right?  3500 gate design, 10000 gate part.  But it
doesn't fit.  I could understand possibly having routing problems but I'm
running out of logic cells:  610 vs the 565 cell capacity of the 10k10.

On the "8000 gate" Motorolla MPA1034, the design takes up 70% of the
capacity.  (won't route but I think that's just because synthesis isn't
using the clock network)

Any ideas on what could be causing this area explosion?  Better yet,
suggestions as to what to do about it?

----
"..very sad life.  Probably have very sad death.  But there's symmetry"
Remember the home hobbyist computer: Born 1975, died April 29, 1994

Article: 4835
Subject: Re: PLD
From: 96kwong@uxmail.ust.hk (Wong Man Kit)
Date: 19 Dec 1996 03:45:03 GMT
Links: << >>  << T >>  << A >>
Tom Smythers (tesmythers@transys.rockwell.com) wrote:
: Is this an appropriate newsgroup to post PLD questions? (I have a
: problem with a Lattice PLD)

What is your problem on Lattice's PLD?

--
******************************************************************************
* Wong Man Kit                                                        黃文傑 *
* Applications Engineer                                               工程師 *
* Lattice Semiconductor Asia Ltd                        萊迪思半導體有限公司 *
* Rm 201, 72 Tat Chee Avenue,                                       香港九龍 *
* HKITC, Kowloon,                                             達之路七十二號 *
* Hong Kong                                         香港工業科技中心二零一室 *
* (852)-2319-2929                                            (852)-2319-2929 *
******************************************************************************
* Email address     *      mankit_wong@latticesemi.com      *       電郵地址 *
*                   *        96kwong@alumni.ee.ust.hk       *                *
* Home page         *   http://eelindc1.ee.ust.hk/~eekwong  *           網頁 *
******************************************************************************
Article: 4836
Subject: Re: Help: FPGA for fast digital signal processing
From: Ray Andraka <randraka@ids.net>
Date: Wed, 18 Dec 1996 21:50:13 -0800
Links: << >>  << T >>  << A >>
gomez66@eucmax.sim.ucm.es wrote:
> 
> Hi!
> 
> Does anyone know any architecture based on FPGA for a
> 
> fast digital signal processing?
> 
> Please, answer me at the below address. Thank you.
> 
> Email: jangomez@unex.es
> 
> URL:   http://maxwell.unex.es/CALD
Sure, I've worked with quite a number.  Which is best really depends on
the application and on who you ask.  Generally speaking, you will
probably want some local fast SRAM associated with each FPGA in the
system.  In many cases access to two banks of SRAM is desirable.  You
need to study the types of problems your system will be solving and
slant the architecture to fit the problem at hand.  The structure of the
interconnect is the biggest variable  (ie lattice vs. linear pipeline).

There are several commercially available systems out there including
ones by Virtual Computer, GigaOps and Annapolis Microsystems.  Each has
a different architecture that has it's own pluses and minuses. You might
look at these systems to see if the architecture fits your needs before
investing in your own design.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka

The Andraka Consulting Group is a digital hardware design firm
specializing in high performance DSP designs for FPGAs.  Areas of
expertise encompass reconfigurable logic computing, computer arithmetic
optimized for FPGAs and maximum performance FPGA design. Services
offered are design and development of FPGAs and board level systems
based on FPGAs, expert reviews, advice and seminars.
Article: 4837
Subject: Area spent for routing in FPGAs
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Thu, 19 Dec 1996 07:46:58 +0100
Links: << >>  << T >>  << A >>
Hello,
I am interested how much area is spent in current 
FPGAs and CPLDs for routing.
The block diagrams e.g. of lattice devices suggest that 
this is a reasonable amount.
OK I know that the anti-fuse camp claims to have no 
area overhead for programmable interconnects at all.
I am only interested in the area of the routing resources itself,
not for the logic for configuring them.
I have not yet seen die photographs of current CPLDs to 
estimate it. (ok on the databook and the FLEX8000 handbook are
some kind of photographs).
Some insider dares to answer?
Andreas
-- 
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
                        Ratzeburger Allee 160
                 
                        D-23538 Luebeck
                        Germany

		        Tel.: +49 451 500-3741
		        Fax:  +49 451 500-3687
		        Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 4838
Subject: Re: Proper target for design
From: murray@pa.dec.com (Hal Murray)
Date: 19 Dec 1996 08:16:02 GMT
Links: << >>  << T >>  << A >>
In article <32B86B88.41C67EA6@redwood.dn.hac.com>, Mark Norton <mnorton@redwood.dn.hac.com> writes:

> I understand the difference in generalitiex between CPLD's and 
> FPGA's, but is one better than the other for specific applications?

There is another difference that I haven't seen mentioned in the
recent discussion.  Look at the ratio of logic to IO.  FPGAs typically
have more logic per IO pin than CPLDs.  So FPGAs typically work
better than CPLDs if your problem requires a lot of state that
doesn't need to be connected to the outside world.  A good example
would be a few counters and a few comparators that make a few flags.

I'd probably rough out the design in both technologies far enough
to see which felt better.  Beware, don't expect the same logic
equations to work well in both cases.  You want to bend things
to take advantage of the available resources/features.  I recently
ported some logic from an FPGA to a CPLD.  After I finished you
would not quickly recognize them as the same design.
Article: 4839
Subject: Cascaded serial PROMS
From: wehr@mikro.uni-stuttgart.de (Andreas Wehr)
Date: 19 Dec 1996 10:17:56 GMT
Links: << >>  << T >>  << A >>
Hi,

are there any experiences how to use 2 cascaded serial configuration PROMs
for XC4000 and XC17128D devices? 
Config pins m0 m1 m2 ?
Splitting the bitfile ?

Thanks,
Andreas


Article: 4840
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: arnief@wu.cse.tek.com (Arnie Frisch)
Date: 19 Dec 1996 16:24:58 GMT
Links: << >>  << T >>  << A >>
In article <Pine.BSI.3.91.961217220540.8995A-100000@malasada.lava.net> "Alvin E. Toda" <aet@lava.net> writes:
>On 18 Dec 1996, Jan Vorbrueggen wrote:
>
>> jet@eskimo.com (James Thiele) writes:
.....
....
...
..
>Even here you have the backup of a co-pilot. If you look
>at the whole system, certainly there are airplane incidents each year
>but the accident rate is probably a lot lower than the auto accident 
>rate. It's a lot safer to ride a plane than a car.


That is a common misconception combined with an incorrect interpretation
of statistics.  Traveling a given DISTANCE by commercial airline is safer
than traveling the same DISTANCE by car.  Traveling for a given TIME on
a commercial airline is likely to be more dangerous than traveling for the
same time by car.

Estimating exposure to risk for airline flyers has to be measured in deaths per people-mile to create a normalized statistic.

This takes into account both the difference in speed and the difference in numbers of passengers.

Arnold Frisch
Tektronix Laboratories
--------------------------------------------------------
Any ideas or opinions expressed here do not necessarily
reflect the ideas or opinions of my employer.
--------------------------------------------------------
Article: 4841
Subject: Re: Cascaded serial PROMS
From: wright@iecorp.com (Jason T. Wright)
Date: Thu, 19 Dec 1996 17:10:51 GMT
Links: << >>  << T >>  << A >>
wehr@mikro.uni-stuttgart.de (Andreas Wehr) wrote:
>Hi,
>
>are there any experiences how to use 2 cascaded serial configuration PROMs
>for XC4000 and XC17128D devices? 
I've cascaded up to 9 devices.  However, if you only need 2, you
should just use one of the 256 devices instead. 
>Config pins m0 m1 m2 ?
Set to master serial mode as per the data book.
>Splitting the bitfile ?
For using a general programmer (i.e., you want the data in s-record
format or some such), run Xilinx's makeprom software.  There is a free
utility you can get from Xilinx called PSPLIT (I believe--I haven't
used it for a while) that takes the  one large programming file and
splits into N files (for however many PROMs are needed.)  I found this
extremely useful for my design with 9 XC17128s (changed to 5 XC17256s
when they became available.)
>
>Thanks,
>Andreas
>
If you have more questions, Xilinx tech help should be very
supportive.  I had problems initially with the 'D' parts that they
assisted me in troubleshooting.  (Remember:  slow clocks does not
necessarily mean soft edges!  My long run for CCLK to all the parts
was my problem that didn't show up with the old, slower parts.)

Have fun.

Jason

Article: 4842
Subject: Consulting Opportunity
From: mike lottridge <mikel@orcad.com>
Date: Thu, 19 Dec 1996 11:00:24 -0800
Links: << >>  << T >>  << A >>
I am interested in getting some expert feedback on a preliminary release 
of our new Express product (see 
http://www.orcad.com/products/exprssds.htm). We will be issuing a 
preliminary release in January to a select group of users and vendors. 
Would you be interested in participating in this review process? 

If so, please email me a summary of your design experience, including 
which FPGA vendors you are most knowledgeable in, along with your 
requirements for participating in the review. I'm looking for quality, 
detailed feedback during the month of January, 1997, and I am willing to 
offer free software/hourly compensation for this work.

Thank-you,

Mike Lottridge
Product Marketing Manager, System-Level Design Products
OrCAD, Inc.
9300 S.W. Nimbus Ave
Beaverton, OR 97008
(503)671-9500    fax (503)671-9501
mikel@orcad.com  http://www.orcad.com
Article: 4843
Subject: Re: Anyone tried a FFT in a FPGA?
From: waynet@goodnet.com (Wayne Turner)
Date: Thu, 19 Dec 96 20:18:44 GMT
Links: << >>  << T >>  << A >>
In article <32B685A9.4933@sj.co.uk>, steve@sj.co.uk wrote:
>Simon wrote:
>> 
>> I am aware that a 40 MSPS 1024-point complex data FFT engine has
>> been built using 24 XC4010. The total cost of the silicon is only
>> around 2000 and it is faster than a CRAY supercomputer.
>> Performance of 10 to 100 times that of a DSP chip is also
>> achievable using single devices.
>
>I note that Altera are offering a FFT MegaCore function from December.  
>Quotes are 
>  "significantly faster than DSP processors and substantially faster
>than previously available programmable logic implementations"
>  "512 point, 8bit data, 8 bit twiddle, 1150 LEs, 94uS" 
>lots of other figures available in the ad, life's too short to retype
>them. I'd guess their web page http://www.altera.com will have more
>data. 
>
>Please note that I have _no_ idea how fast a hardware FFT _ought_ to go,
>so I'm not commenting, just passing on the ad.
>
>A side issue, has anyone out there used any of the AMPP modules?
>Success? Nightmare? inbetween?

A guy I know in New Mexico (Albuquerque) bought a 3x3 LaPlacian Edge Detector 
from Integrated Silicon Systems up there in Ireland.  He put it in a 10K 
device and he said it works as advertised.

Wayne
Article: 4844
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: waynet@goodnet.com (Wayne Turner)
Date: Thu, 19 Dec 96 20:27:17 GMT
Links: << >>  << T >>  << A >>
In article <32B5BE77.CEC@emf.net>, Brad Taylor <blt@emf.net> wrote:
>Alasdair MacLean wrote:
>> 
>> We tend to use antifuse parts (Actel) which are OTP rather
>> than SRAM based parts. I'm fairly sure we would not be allowed
>> to use SRAM parts in "flight-critical" applications.
>> 
>> 
>
>Let's just assume:
>
>1-  FPGAs allow you to weed out 'all' the BAD devices
>    via extensive device testing.
>3-  FPGAs do not ever just flip a program bit randomly.

Actually, they can.  In flight applications for example, a heavy ion hitting 
an SRAM cell can cause the value to change and thereby change the 
functionality of the circuit without being able to detected before the 
functionality has already changed.

Read up on single-event upsets in SRAM devices (both memory and logic).


>4-  Loading of configuation data into an FPGA is 100% reliable
>    if timing and voltage margins are met.
>  
>If anyone has any evidence contrary to the above assumptions
>I'd like to see it.   

[...]

See above...
Article: 4845
Subject: Silcon Processing Courses from Berkeley this winter
From: course@garnet.berkeley.edu ()
Date: 19 Dec 1996 21:19:39 GMT
Links: << >>  << T >>  << A >>
	  University of California Extension,
	  BERKELEY, 

	  Announces....
 
          Three Short Courses in Semiconductor
          Technology for January-February 1997
          
          
          1. "SILICON PROCESSING FOR THE VLSI ERA"
          
          January 27-31, 1997
          at the San Francisco Airport
          
          This course, organized by Dr. Stanley Wolf,
          provides a detailed introduction to state-of-
          the-art process techniques used in
          fabricating silicon integrated circuits.  Dr.
          Wolf is assisted by a world-class
          industry/university instructional team.
          
          Fee: US $1,595  (2.8 CEU)
          ---------------------------------------------
          2. "PROCESS INTEGRATION FOR SUBMICRON IC
          TECHNOLOGIES"
          
          February 4-6, 1997
          at the San Francisco Airport
          
          This course is an outgrowth of material
          presented in the books "Silicon Processing
          for the VLSI Era---Volume II and Volume III",
          by Stanley Wolf.  The course includes a
          survey of the evolution of various MOS and
          CMOS device structures, culminating with the
          details used to fabricate the advanced device
          structures used in VLSI and ULSI.  In this
          vein, the advances in process technology that
          have contributed to improved device and
          circuit performance are also emphasized.  the
          course is taught by Dr. Wolf and Dr. John
          Shen, V.P. of R&D, Taiwan Semiconductor
          Manufacturing Corporation(TMSC).
          
          FEE:  US $ 1,195 (1.8 CEU)
          ---------------------------------------------
          
          3. "PLASMA ETCHING TECHNOLOGY"
          
          February 10-11, 1997
          at the San Francisco Airport
          
          This course covers the design and
          applications of plasma processing techniques
          in IC manufacture.  The physics and chemistry
          of electric discharges are explained and
          related to processing requirements for
          selectivity, linewidth control, yield and
          throughput.  Basic strategies for designing
          new processes are introduced and fundamental
          principles are illustrated with numerous
          examples of process chemistry, equipment
          technology, and diagnostic techniques. 
          Important trends in new equipment, plasma
          sources, process control and damage
          monitoring and reduction are also surveyed.
          
          The course is taught by Dr. Daniel L. Flamm,
          McKay Lecturer, UC Berkeley and industry
          consultant.  
          
          FEE:  $895   (1.2 CEU)
          ---------------------------------------------
          
          MORE INFORMATION?   For a free brochure
          describing these three courses send your
          POSTAL ADDRESS or FAX NUMBER to us at
          "course@garnet.berkeley.edu"   Please specify
          the course(s) you are interested by name.
          
          ---------------------------------------------
Article: 4846
Subject: Re: Exemplar's Leonardo on Linux
From: celiac@teleport.com (Celia C.)
Date: 19 Dec 1996 21:28:43 GMT
Links: << >>  << T >>  << A >>
In article <32b8899d.135925978@news.iinet.net.au>,
 <phony@see.sig.for.real> wrote:
>David Emrich <emrich@exemplar.com> wrote:
>
>:Phil Ptkwt Kristin wrote:
>:> I've heard that Exemplar will release a Linux version of their Leonardo
>:> synthesis tool for Linux early next year.  Has anyone else heard this?
>:> It would be good if someone from Exemplar could comment on this.
>:
>:The port is complete for Leonardo 4.0.3.  Available in January 97.
>:
>[snip]
>:> 
>:> If this is true it is very good news for the Linux engineering community.
>:> Leonardo is a popular synthesis tool on NT, having it ported to Linux
>:> could very well be the catalyst that causes other EDA vendors to follow
>:> suit.
>:> 
>[snip]
>
> IMHO, cause for some celebration! The day a major application vendor
>does a port to Linux, Linux starts getting credibility in the
>commercial (not just academic) zone. The first brick knocked out of
>the M$/Intel monolith :-)
>

Well, this will only be a major accomplishment if we (EDA users) support
Exemplar's efforts and buy their product on the linux platform. I am
sure that Exemplar will discontinue linux support if there is no
profit in it.




--
-----------------------------------------------------------------------------
--Celia Clause                    Celia's Verilog/EDA web page: 
  celiac@teleport.com             http://www.teleport.com/~celiac/ver_eda.html
Article: 4847
Subject: $$$$$$$$$ HONEST, LEGAL, EASY CASH $$$$$$$
From: lfb3@aol.com (LFB3)
Date: 20 Dec 1996 00:09:18 GMT
Links: << >>  << T >>  << A >>
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

This is the easiest, most honest way to legally break that bondage of debt
and to share great wealth with others!  Yes, Congress has passed a law
making this perfectly legal.  By doing the following, you are creating a
service.
$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$

Hello! Take 5 - 10 minutes to read this and it WILL change your
life!!!!!!!!!

If you want to know how to make thousands of dollars quickly, legally, and
with no catch, then keep reading.

A little while back, I was browsing these newsgroups, just like you are
now, and came across an article similar to this that said you could make
thousands of dollars in weeks with only an initial investment of $5!!!!!!
And I thought "Yeah right, what a scam", but like you (and you are reading
this), I was curious. So I kept reading.  The letter said to send $1 to
each of the 5 names and addresses listed in the article, then to place my
own name and address in the article at the bottom of the list (position
#5) and post the article in at least 200 newsgroups (there are thousands).
 No catch, that was it.

So, after thinking it over and talking to a few people first, I tried it. 
I figured what have I got to lose except 5 stamps and 5 bucks.

Well, guess what.. within 7 days I started getting money in the mail!  I
was shocked!!  I still figured it would end soon, and didn't give it
another thought.  But the money kept coming in, tripling in size and
multiplying by THIRTEEN  times the amount that I got the first week.  

In my first week I made about $20 - $30.  But by the end of the second
week, I had made a total of over $1,000.00 !!!!!  In the third week, I had
received over $13,000.00 and it's STILL growing. 

Let me explain how this works, and most importantly, WHY it does...

**** The process is very simple, and it consists of 5 EASY steps: ********

STEP 1:  Get 5 seperate pieces of paper and write your name and address
along with the words "Please add me to your mailing list. You are
currently # n (where   
n = 1 to 5 position on the list).  This way, you are not just sending a
dollar to someone, you are paying for a legitimate service.  

STEP 2:  Get 5 one dollar bills, place one bill inside each of the five
pieces of paper you wrote on, then fold each piece of paper so that the
bill won't be seen through the envelope. You should now have five sealed
envelopes.  Each one has one dollar in it, folded inside the piece of
paper.  

STEP 3:  Mail the five envelopes to the following five addresses:

     1. T. Johns, P.O. Box 16936, Jackson, MS 39236-6936
     2. B. Pope, 650 Old Fannin Rd Box #D9, Jackson, MS 39208
     3. J. Torok, 2647 SW 33rd Ave apt 811, Ocala, FL 34474
     4. J. Campbell, 1040 C Winners Circle, Bowling Green, KY 42104
     5. L. Brennan, 2605 NW Columbia, Lawton, OK 73505-6237

STEP 4:  Using the above list, edit it by DELETING name #1 on the list. 
Put yourself at position #5.  Move the other names up (5 becoming 4, 4
becoming 3 etc.) The longer your name is on the list the more money you
make, and #5 will be on the list the longest!!!  That's where you want to
be!!!

STEP 5:  Post your edited article (with your name at position # 5) to at
least 200 newsgroups (I use ALT.NET, which has about 26,000 of them!) I
found that 200 will do quite nicely!!

                           HOW TO POST YOUR EDITED ARTICLE

     If you have Netscape 3.0, do the following EXACTLY:

Click on any newsgroup like normal, Then click on "TO NEWS", which is on
the far left when you're in the newsgroups page.  This will bring up a box
to type a message in.

Leave the newsgroup box like it is, change the subject box to something
flashy, like, "NEED CASH $$$ READ HERE" or "FAST CASH"!!!

Tab once and you should be ready to type.  Now retype(only once) this
WHOLE article WORD FOR WORD, except to insert your name at #5 and to
remove #1 off the list, plus any small changes you think you need to make.
 Keep almost all of it the SAME!

When you're done typing the whole article, click on FILE in the BOX right
above SEND, not where it says netscape news on the first box.  Click on
SAVE AS when you're under file.  SAVE your article as a text file to
either your A: or C: drive.  DO NOT SEND OR POST YOUR ARTICLE UNTIL YOU DO
THIS!!  Once SAVED continue on.

If you still have all of your text, send or post to this newsgroup now,
just by clicking send.

Now post this article to all 200 newsgroups. OK, click on any newsgroup,
then click on "TO NEWS", againin the top left corner.  Leave the
NEWSGROUPS Box alone again, put a flashy subject title in the SUBJECT box.
 This will result in a new box coming up.  Click on ATTACH FILE, then find
the article that you saved.  Then click once on the file and then click
OPEN.  Next, click on OK.  If you did this right, you should see your
filename in the attachments box, and it will be shaded green.  

                  IF YOU USE EXPLORER, IT'S JUST AS EASY

Holding down the left mouse button, highlight this article.  Then press
the "Ctrl" key and the "C" key at the same time to copy this article. 
Then print this article for your records to have the names of those you
will be sending $1 bills to.  Next go to the newsgroups and press "post an
article", a window will open.  Type in your headline in the subject area
and then click in the window below it.  press "Ctrl" and "V" and the
article will be placed in the window.

If you want to edit the article, do so and highlight it and copy it again.
 Now everytime you post the article in a newsgroup, all you have to do is
repeat the "Ctrl" and "V" combo and post it.

That's it.  Each time you do this, all you have to do is type in the name
of a different newsgroup (I do ten at a time)so that you end up posting to
at least 200 different newsgroups.  It only takes my computer-illiterate
wife about 30 seconds per post, doing 5 newsgroups per post.  And the more
you post, the more money you will make!!!  And once you see how easy this
is, I promise you that you will become efficient at this program!!!

You are now in the mail order business, and you will start receiving your
$1 envelopes from various people all over the world within days.  You may
want to rent a P.O. Box because of all the mail.  If you wish to remain
anonymous, you can invent a name, such as "manager" or whatever.
Just make sure all of the addresses are CORRECT please.!!!!!

The Internet has grown tremendously.  It doubles in size every 4 months!!
Literally THOUSANDS of people read newsgroups EVERY DAY!!!

Out of 200 postings, let's say I only receive 5 replies, which is actually
VERY LOW.  So I made $5 with my name at position #5.  Now each person who
just sent me $1 makes, say only 200 postings, now with your name at #4,
which is a total of 1000 postings, not including yours.  50 people send
you $1 now.  That's $50 you just made!!  Now your 50 new agents each post
200 with your name at position #3, or 10,000 postings (50 X 200).  The
average return is 500, at $1 each, that's $500.  They make 200 postings
each, which is 5,000 returns, at $1 each is $5,000!!!!!!
And finally, 5,000 people make 200 postings each, with your name at #1. 
You get a return of $50,000 before your name drops off the list.  And
that's if eveyone only does 200 posings, and if only 5 people
respond!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

When your name is no longer on the list,  you just take the latest posting
that is appearing in the newsgroups, and send out another $5 to the people
on it, putting your name at #5 again.  And start posting again.  The thing
to remember is :
THOUSANDS OF PEOPLE ALL OVER THE WORLD ARE JOINING THE INTERNET AND
READING THESE ARTICLES EVERY DAY, JUST LIKE YOU ARE RIGHT NOW.  So are you
willing to risk $5 for a chance to CHANGE your financial future for the
rest of your life?  Believe me it works.

People have said, "What if the plan is played out and no one sends any
money?"  So what!  What are the chances of that happening, when there are
tons of HONEST, NEW users and people who are joining the Internet and
newsgroups daily and are willing to give it a try?  Estimates are at
1,000,000 per DAY worldwide, with many of those joining newsgroups!!  You
might even be new, and you are reading this right now, correct? 

REMEMBER, play FAIRLY and HONESTLY and this will work, I promise you.  You
just have to be honest.  Keep a list of who sends you $1, and keep an eye
on the newsgroups, to make sure everyone is playing fair.  REMEMBER
HONESTY IS THE BEST POLICY.  YOU DON'T NEED TO CHEAT THE BASIC IDEA TO
MAKE A LOT OF MONEY!!!   GOOD LUCK TO ALL, AND PLEASE PLAY FAIRLY THE
FIRST TIME, AND YOU WILL REAP THE REWARDS FROM THIS . . . TONS OF X-TRA
CASH!!!!! ! ! ! ! 


    ********* By the way, if you trt to deceive people by posting the
messages with your name on the list and not sending the money to the
people already on the list, you will not get much.  A guy I talked to did
that, and he only made $150, and that's after 7 or 8 weeks.  The he wised
up.  Who is gonna help you if they don't see that you are honestly doing
your part, by sending them each $1 like they did before you??  Then he
sent the $5 out , and the people ADDED HIM TO THEIR LISTS, and in 4 to 5
weeks he made over 10,000 dollars.

_____________________________________________________________________
                

            THIS IS THE FAIREST AND MOST HONEST METHOD I HAVE EVER SEEN TO
MAKE HUGE CASH BY INVESTING ONLY A LITTLE TIME! !   IF YOU ARE REALLY
SERIOUS ABOUT CHANGING YOUR LIFE AND BECOMING DEBT FREE, DO IT, DO IT
RIGHT NOW, AND IN A MONTH ALL OF YOUR DREAMS CAN COME TRUE! ! ! ! ! ! ! !
! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
! ! ! ! ! ! !


Article: 4848
Subject: Re: FPGA market overview
From: "Thomas C. Jones" <tjones@aspect.com>
Date: Thu, 19 Dec 1996 17:20:56 -0800
Links: << >>  << T >>  << A >>
Alon Hazay wrote:
> 
> I'm doing an overview of the FPGA market.
> Does anyone know a review which compares the FPGA's of the leader
> vendors in the market today(ALTERA,XILINX,ACTEL,ORCA etc.)?
> 
> Alon Hazay


Please post any findings.  I would be particularly interested 
in objective benchmarks for all the traditional parameters 
(routability, etc.) as well as non-traditional, but otherwise 
equally useful metrics such as ease-of-use of tools, changeability, 
etc.

Thanks,
Tom Jones
Article: 4849
Subject: Re: Exemplar's Leonardo on Linux
From: eric@wolf359.exile.org (Eric Edwards)
Date: Fri, 20 Dec 1996 02:03:11 GMT
Links: << >>  << T >>  << A >>
In article <32b8899d.135925978@news.iinet.net.au>, phony@see.sig.for.real writes:

> David Emrich <emrich@exemplar.com> wrote:
> 
> :Phil Ptkwt Kristin wrote:
> :> I've heard that Exemplar will release a Linux version of their Leonardo
> :> synthesis tool for Linux early next year.  Has anyone else heard this?
> :> It would be good if someone from Exemplar could comment on this.
> :
> :The port is complete for Leonardo 4.0.3.  Available in January 97.
> :
> [snip]
> :> 
> :> If this is true it is very good news for the Linux engineering community.
> :> Leonardo is a popular synthesis tool on NT, having it ported to Linux
> :> could very well be the catalyst that causes other EDA vendors to follow
> :> suit.
> :> 
> [snip]
> 
>  IMHO, cause for some celebration! The day a major application vendor
> does a port to Linux, Linux starts getting credibility in the
> commercial (not just academic) zone. The first brick knocked out of
> the M$/Intel monolith :-)

Is it?  Or is it a brick knocked out of Sun, HP, and DEC?  Though I
suppose, it means we may still have a choice of operating system after
we've lost the choice of architecture.

----
"..very sad life.  Probably have very sad death.  But there's symmetry"
Remember the home hobbyist computer: Born 1975, died April 29, 1994



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