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Messages from 5000

Article: 5000
Subject: CFP Memory Technology Workshop
From: fmeyer@cs.tamu.edu (Jackie Meyer)
Date: 10 Jan 1997 17:02:04 GMT
Links: << >>  << T >>  << A >>

                    CALL FOR PAPERS AND PARTICIPATION

                    1997 IEEE INTERNATIONAL WORKSHOP
                ON MEMORY TECHNOLOGY, DESIGN AND TESTING

                           August 11-12, 1997

Submission deadline:  January 15, 1997

Send submissions to:

TECHNICAL PROGRAM CHAIR
Thomas Wik
LSI Logic, MS E-194
1501 McCarthy Blvd
Milpitas CA  95035, USA
408/954--4471; trw@lsil.com

Address general inquiries to:

GENERAL CHAIR
Fabrizio Lombardi
Computer Science MS 3112
Texas A&M University
College Station TX  77843, USA
409/845--5464; fax 847--8578
lombardi@cs.tamu.edu

The 1997 IEEE International Workshop on Memory Technology, Design and
Testing will be held at the Hilton Hotel and Towers, 300 Almaden Blvd,
San Jose, California, USA (408/287--2100), on August 11-12, 1997.

The workshop will include all aspects of memory design, process
technologies and testability related topics.  Memory circuit designs,
cell structures, fabrication processes, design architectures as
related to testing, verification and test methods for SRAM, DRAM,
Flash and Non-Volatile memories, EPROM, EEPROM, embedded memories,
logic-enhanced and FIFO memories, 3-D memories and content addressable
memories.  Some representative topics are:

  -  Memory fault modeling and test generation
  -  Built-in test and testable designs for memories
  -  Concurrent checking and memory fault diagnosis
  -  Quality and reliability issues
  -  Space applications and radiation hardening issues
  -  Memory failure and yield analysis
  -  High-speed, innovative designs
  -  Fault isolation, reconfiguration and repair
  -  Multiported, multibuffered memories
  -  Logic-enhanced and programmable memories
  -  Application-specific and embedded memories
  -  Multimegabit SRAMs and DRAMs
  -  CMOS, BiCMOS and bipolar designs for high yield and reliability

Authors please submit five (5) copies of an extended abstract of about
1000 words of original work on any aspect of memory technology, design
and testing to the Technical Program Chair.  Submissions should
include full names and affiliations of authors, contact information
and should indicate the intended presenter.

Submissions are due January 15, 1997.  Authors will be notified of
acceptance on March 31, 1997.  Final papers will be due May 15, 1997.
Presentations will be 30 minutes, inclusive of discussion.

Sponsored by:
  IEEE Computer Society
  Technical Committee on Test Technology
  Technical Committee on VLSI
In cooperation with:
  IEEE Solid-State Circuit Society
Article: 5001
Subject: Re: What Does ASIC Stand For?
From: Alexandru Petrescu <petrescu@vallin.loria.fr>
Date: 10 Jan 1997 18:12:30 +0100
Links: << >>  << T >>  << A >>

    >> : Aren't "ASICs" a brand of tennis shoe?  :^)
    >> 
    >> Why were the shoes named ASIC's ?

Anima Sana In Corpore Sano.

(hope I'm not too late or too disturbing regarding topic)

-- 
Alex
Article: 5002
Subject: Re: FAQ
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 10 Jan 1997 18:00:03 GMT
Links: << >>  << T >>  << A >>
I haven't found a dedicated FAQ, but you're welcome to look at the
programmable logic and FPGA links on "Jump Station" that I've put together.
 Just point your browser to:

http://www.netcom.com/~optmagic


-- 
Steven Knapp


Geoffrey Bostock <geoff.bostock@zetnet.co.uk> wrote in article
<1997010909352069908@zetnet.co.uk>...
> In message <5b0igk$h2r@Bayou.UH.EDU>
>         st7jp@Bayou.UH.EDU (,, ,) writes: 
> 
> 
> > Hi folks!  I'm new to this newsgroup and was wondering if
> > some sort of a FAQ exists that I can look up ?
> 
> > Thanks a million!
> 
> 
> 
Article: 5003
Subject: Re: Are you looking for CHIP MANUFACTURER websites ???
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 10 Jan 1997 18:04:25 GMT
Links: << >>  << T >>  << A >>
If you are interested in just the programmable logic suppliers, and
subsequent links to the Web pages, you can also point your browser to:

http://www.netcom.com/~optmagic

It's not fancy (no frames or colorful graphics) but functional.


-- 


Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Gray Creager <gcreager@scruznet.com> wrote in article
<32D565DC.44B1@scruznet.com>...
> Don't be fooled by imitations...
> 
> I have been keeping the BEST listing anywhere on the internet for the
> past 1 1/2 years and it gets updated frequently. Right now, there are
> 327 CHIP MANUFACTURER websites listed!
> 
> Check it out (brief or verbose versions available) and bookmark it.
> 
> http://www.scruznet.com/~gcreager/hello5.htm
> 
> --
> Gray Creager
> Applications Engineer
> Xicor, Inc.
> http://www.xicor.com
> 
Article: 5004
Subject: ISP Online Discussion
From: sbaker@best.com
Date: 10 Jan 1997 22:34:13 GMT
Links: << >>  << T >>  << A >>
WE'RE LOOKING FOR A FEW GOOD INQUISITORS

Programming Silicon, the web newspaper for Programmable Logic, and 
"reconfig.com", the web site for reconfigurable computing will host a 
virtual Roundtable in late January on the subject of In-System 
Programming (ISP) in Programmable Logic Devices.

If ISP is important to your work, we invite you to join the Q&A in 
this Roundtable.  You don't have to travel or be any place at a particular 
time.  This is not a real-time event.  It will be on line for about two weeks.
And you can be an anonymous questioner or use your real identity.

This Roundtable will become a Special Interactive Report in 
Programming Silicon and in "reconfig.com" in mid February.  
This will be the most important, definitive and useful editorial 
presentation of ISP to ever be provided to the electronic 
engineering community.

HOW IT WORKS
The Roundtable will begin at our Web site with several presentations 
by ISP applications experts which all of the participants can study.  
The Q&A will commence at that time and proceed for two weeks.  
The questioners are there to comment on, add to and challenge the opinions 
of these experts.

At the end of the Roundtable all of the participants will be invited to
provide summary statements.  The proceedings will then be compiled 
from the presentations and Q&A messages and placed in the 
Programming Silicon (www.pldsite.com) and "reconfig.com" 
(www.reconfig.com) Web sites.  This Special Report will remain 
interactive, so the public can continue to post comments and questions.  

INLIST FOR OUR TWO-WEEK ISP PANEL.  
We need a dozen questioners to critique what the experts say.
Have fun and learn something at the same time.

ISSUES TO BE DISCUSSED
The discussion will be limited to non-volatile devices.  This leaves 
out the SRAM-based products and we won't get into "reconfigurable 
computing."

The ISP issues to be discussed and debated will include:
-- the global implications of ISP
-- future ISP capabilities
-- what is ISP and how it differs from reconfigurable computing 
-- standardizing the programming protocols
-- the new way of thinking generated by ISP 	
	(manufacturing economics, organizational impacts, programming 
	technologies and strategies, etc.)
-- and whatever the inquisitors bring up.

YOUR IDEAS
If you are interested, even if you don't want to participate, we would 
like to get your suggestions about the topics to be discussed (by 12/14).  

NOMINATE
If you have customers or know of others that should be invited to be
questioners, please contact us with your recommendations.

If you would like to participate, we will send the details to you. 

Best regards,
Stan Baker
Editor/Publisher
Programming Silicon and "reconfig.com"
408-356-5119
Fax: 408-356-9018
email: sbaker@best.com



Article: 5005
Subject: Re: Altera clique
From: Scott Redman <sredman@pacbell.com>
Date: Fri, 10 Jan 1997 21:17:54 -0800
Links: << >>  << T >>  << A >>
Benjamin D Klass wrote:
> 
> Mark Adam's suggestion for using the Linked SNF extractor is a good one,
> but you can also do multi-chip designs with one project.  The key is not
> to "chips" instead of "cliques."
> 
> A clique is a strong hint to the compiler that logic should be kept
> together, but the compiler can ignore it.  A "chip" forces the compiler
> to put certain specified logic in a certain device.  Since you want four
> devices, create four chips and assign pins and as much logic as you want
> to specify to each chip.  If you leave some logic unassigned, Maxplus2
> will automatically divide that logic among the chips.  Also "reserve
> resources" can be used to keep utilization within each device down.

Both suggestions will work. However, if the chips are in different
families,
such as MAX7000 and FLEX10K, then you will need to use Mark Adam's
suggestion,
using Linked SNF's.  Assigning chips only works if the chips are in the
same
family.  Someone else suggested using one big chip.  This might not just
save you
time, but also board space.

Scott
Article: 5006
Subject: Re: DES Keysearch by FPGA: $10,000 prize
From: z80@digserv.com
Date: Sat, 11 Jan 1997 12:59:41 GMT
Links: << >>  << T >>  << A >>

I read this paper a while ago, and while it appears to be detailed, it
in fact does NOT contain a great deal of information.

Sure, it is easy enough to get a big FPGA and stick DES into it, then
replicate that design X times (where X is a LARGE number), build some
sort of supervisory PC-based machine to keep stuffing in the keys, and
off you go. Any half-competent hardware man can do this, in say 6
months.

But detecting if you have the right key is easy only if you have the
exact known plaintext, specifically the first 8 bytes of it. Anything
else makes it quite complex. If you are given the first "few" bytes
then you will find many keys which appear to match, and you will need
circuitry which does statistical analysis on the rest of the 8-byte
block, to see if it is ASCII or whatever.

Then you have the huge cost of this machine which every crypto book
says is easy to build. Say a FPGA can do a DES decryption in 1us
(should be possible with a 32-64MHz clock) you will need 1142 years
(keyspace 2^55). So to do it in 24 hours you will need 417000 of these
FPGAs.

An ASIC could do DES in 100ns or less, if the 16 loops were unrolled
into one fall-through design. This would go into perhaps 50k gates,
fine by today's standards.

I think even Xilinx will regard you as a "big" customer if you tell
them you want 417000 pieces of a 4015 or whatever! Come to think of
it, most power supply manufacturers will be happy too...

>There have been theoretical studies done showing that a specialized 
>computer "DES cracker" could be built for a modest sum, which could 
>crack keys in mere hours by exhaustive search. However, no one is 
>known to have built such a machine in the private sector - and nobody 
>knows if one has been built in any government, either.

I wonder why??

Peter.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5007
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: David Erstad <erstad@ssec.honeywell.com>
Date: Sat, 11 Jan 1997 14:48:53 -0600
Links: << >>  << T >>  << A >>
Honeywell does not currently have a rad-hard FPGA.  There is a strong
possibility
of our developing an SRAM-based FPGA becoming available in the future,
but there is no
current product offering.

As far as I know, there is no class-S, rad-hard SRAM FPGA on the market
today.
The Harris effort is no longer active.

Of course, Honeywell (and one or two others) could readily convert a
Xilinx 
design to a rad-hard gate array for flight purposes.

Friedrich Beckmann wrote:
> 
> Rich K. wrote:
> >
> > James W. Swonger <jws@billy.mlb.semi.harris.com> wrote in article
> > <5attn9$mkg@hearye.mlb.semi.harris.com>...
> > >  If you're really interested in SEU-immune, high-rel FPGAs you should go
> > > to the companies which are building Class S, rad hard versions of the
> > > ACTEL form (Lockheed Martin, partnered with Actel) and Xilinx form
> > > (Honeywell). These will be able to provide you with bit error rate,
> > > total dose and other reliability and failure/fault analysis information
> > > (presuming they care to, and that's not a given; they'll probably make
> > > you pass through Marketing first to see if you're a customer or just a
> > > babbler).
> > >
> >
> 
> > Also, is Honeywell building the Xilinx compatible part?  Is there contact
> > information on this?  I know Harris had a data sheet on some of these
> > Xililinx devices a few years ago but I believe they dropped the part.
> >
> > rk
> 
> A few weeks ago I tried to find a rad hard fpga device.
> ACTEL can provide you with rad hard devices. Due to a previous Xilinx
> design I tried to find a rad hard Xilinx Device and I went through
> the marketing departments...
> 
> As far as I could find out, there is no rad hard Xilinx Device
> available.
> 
> The application of this was a satellite.
> 
> Fritz
> 
> * Friedrich Beckmann                                          *
> * University of Bremen                  TEL: +49 421 218 4079 *
> * FB1 - Institute for Microelectronics  FAX: +49 421 218 4434 *

-- 
Dave Erstad
erstad@ssec.honeywell.com
The views above are mine and are not necessarily Honeywell's.
Article: 5008
Subject: Motorola 68HC16 background debugger
From: wctech@why.net (Larry Chen)
Date: 12 Jan 1997 04:19:33 GMT
Links: << >>  << T >>  << A >>
If you are using or going to use 68HC16 microcontroller, you may
be interested to look at HC16BGND, an advanced programmer’s 
interface that helps you to develop, test, and refine your 
assembly language programs for MOTOROLA’s 68HC16 microcontrollers.
The key features include:
- Run under MS Windows
- Interface through PC’s parallel port
- Motorola suggested 10 pin target connector
- Download and debug HC16 assembly language program in S19 or HEX format
- trace through your code by step through or step over
- set up to 100 breakpoints
- On-screen editing of register and data memory
- On-fly assembly of instruction using mnemonics in program memory
- Open infinite Register, Program, and Data windows
- Watch window so that you can watch important variables
- Exchange data through Windows clipboard
- File I/O which can be used to automatically read a hex input file
  into the file and write the result to an output file.
- Easy to use.  Just click on the menu with left mouse or click on 
  the windows’ area.  Everything is self-explained
- Convenient and easy to install due to its parallel port interface.
  You can use laptop to do an on-site demonstration of you products
- Low cost
- 30 day money back guarantee and one year product warranty
For more information or need a demo program,
see http://users.why.net/wctech/hc16bgnd.htm, 
or FTP to FTP.WHY.NET/FTP/PUB/USERS/WCTECH, 
or send email to WCTECH@WHY.NET

Larry Chen
WC Technology
Article: 5009
Subject: Re: Linux version for EDA
From: "Karl W. Pfalzer" <karlp@ez-synthesis.com>
Date: Sun, 12 Jan 1997 08:18:29 -0800
Links: << >>  << T >>  << A >>
John,

The current offering is NOT a synthesis tool, but tools to supplement a
Synopsys Design Compiler based ASIC synthesis flow.

Demos will be provided at the website, soon.

If the Internet-based, (virtual) EDA company business model appears
"fruitful",
maybe there will be a robust, Linux (et. al.) synthesis tool available
in the
not too distant future !!


John B. McCluskey wrote:
> 
> I use Linux 2.0.27 on pentiums, and Sun OS 4.1.3 on Sparc stations.
> 
> I'm very interested in trying out a linux synthesis tool.   Will demo's be
> available soon?
> 
> John McCluskey

-- 
Synthesis Solutions, Inc.
http://www.ez-synthesis.com
vmail: (415) 431-6429
Article: 5010
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Sun, 12 Jan 1997 17:29:01 GMT
Links: << >>  << T >>  << A >>
In article <5attn9$mkg@hearye.mlb.semi.harris.com> jws@billy.mlb.semi.harris.com (James W. Swonger) writes:
> You can get SEU-immune SRAMS and digital ASICs from either of the above.
>No, you won't like the price. You can also get SEU-immune PROMs to reload
>the SRAM-based FPGAs from, ditto on the cost. If you are that concerned
>with eliminating failure modes, though, you'll pay the prices or you'll
>stay on the ground. Anything else will net you an unacceptable probability
>of failure...

Actually, there is an alternative, for memory:  error-correcting codes. 
Even commercial DRAMs have been flown successfully using ECC and a bit of
shielding, although admittedly they only lasted (as I recall) a year or
two (in an elliptical orbit that passed through the Van Allen belts
regularly). 
-- 
"We don't care.  We don't have to.  You'll buy     |       Henry Spencer
whatever we ship, so why bother?  We're Microsoft."|   henry@zoo.toronto.edu
Article: 5011
Subject: Internet Fax Service
From: info@mage.com
Date: 12 Jan 1997 22:03:39 GMT
Links: << >>  << T >>  << A >>
--------------------- Internet Fax Service --------------------------
------------------ Save Your Long distance charges ------------------
------------ HT-Net Internet International Fax Network --------------


For the mobile workers, accessing and managing your faxes from a remote
location. Long distance or international telecommunications can be very
expensive and until now there has been no simple way to manage faxes
from a distance.

Check HT-Net at http://www.twsp.com


Article: 5012
Subject: "NEED CASH $$$$$ READ HERE $$$$$"
From: "Arthur Smilkstinsh" <rider@stoat.riga.lv>
Date: Sun, 12 Jan 1997 22:33:08 GMT
Links: << >>  << T >>  << A >>
DO YOU NEED MONEY... AND NEED IT NOW!?



THIS IS THE FASTEST... AND FAIREST... WAY I KNOW TO SHARE THE WEALTH!



Would you like to make thousands of dollars quickly, legally, and with NO

CATCH?



Then keep reading... please take five minutes to read this article in

its entirety... it will chage your life.  It has certainly changed mine!

You can make up to, or over, $50,000 in only 4-6 weeks.  I know, it

sounds like a scam, BUT IT'S NOT A SCAM... READ ON! Really, if you're

interested, keep reading; if you're not, please don't let me waste any

more of your time.

	OK, still with me?  A little while back, I was browsing through these

newsgroups, just like you are now, and I came across an article similar

to this that said you could make thousands of dollars in only weeks with

an initial investment of ONLY $5!  And, like you, I thought "Yeah,

right, must be a scam..."  But, I was intrigued... like most of us

are... and so I kept reading.  Anyway, the article said that you were to

send $1.00 to each of the 5 names and addresses listed in the article. 

You then placed your own name and address and the article in at least

250 newsgroups... there are thousands!... no catch... that was all you

had to do.

	So after thinking it over and talking to a few friends first, I decided

to try it... after all, if it really was a scam all I would loose would

be my $5 and the cost of 5 stamps, right?  Well, guess what... within 7

days, I started getting money in the mail... NO kidding! I have to tell

you, I was surprised to say the least.  I still figured it would end

soon and didn't give it too much thought.  But then money kept coming

in... tripling in numbers and multiplying by 10 and 20 times the amount

that I got the first week!  In my first week I made about $20 or $30. 

But by the end of the second week, I had made a total of over $1,000!! 

In the third week, I had over $10,000, and it's still growing.  This is

my fourth week and I've made about $42,000 TOTAL.. and the money is

still coming in.

	Let me tell you how this works and more importantly, WHY it works...

also, make sure you print a copy of the article so you get the

information off it and can begin making money yourself.  The process is

very simple and it consists of just 3 EASY steps:



	STEP 1:  Get 5 separate pieces of paper and write the following

statement on each sheet of paper... "PLEASE PUT ME ON YOUR MAILING LIST.

YOU ARE NUMBER ___"  (To do this, you paid for the service and made a

investment.  And make this legal.  Then all people which check the

newsgroupes will trust you and it makes your investment work in the

net.)  Get five $1.00 bills and place ONE inside each piece of paper

that you just wrote on and fold the piece of paper so the bill will not

be seen in the envelope (otherwise, nosey people who like to steal mail

with money in it will get yours!)  Put one folded note (with your $1.00

bill) inside the envelope and seal it.  Do the same for each of the five

names.  You should now have 5 envelopes sealed, EACH envelope has a

piece of paper with the message asking to be put on the mailing list and

a $1.00 bill hidden inside the paper, right?  This is IMPORTANT... Make

sure you have written the message asking to be put on the paper... by

doing this you are creating a service and keeping everything PERFECTLY

LEGAL... Now, mail the 5 envelopes to each of the 5 addresses listed

below:



1.  K. Doake, P.O Box 54016, Tulsa, OK 74155-0016

2.  J. Johnson, 6930 Oak Valley Lane, Colorado Springs, CO 80919

3.  I. Chow, Suite 607-4944 Dalton Dr. NW, Calgary, Alberta, Canada t3A

2E6

4.  Jun Zhou, 1132 W. Blaine St.  #102, Riverside, CA   92507

5.  Arthur Smilkstinsh, 10 Zemes St. Apr. 36 Riga, Latvia LV-1082



STEP 2:  Now take the #1 name off the list that you see above, move the

other 4 names up (5 becomming 4, 4 becomming 3, etc.) and put YOUR NAME

as number 5 on the list.  You can slightly alter this article if you

need to, editing what you feel you need to edit.



STEP 3:  Post your amended article... with your name as #5... to at

least 250 newsgroups (I'm told that there are close to 18,000 of them!)

and all you need is 250 or so, of them.



HOW TO DO THIS -- If you have Netscape 3.0 do EXACTLY the following:

	A)  Click on any newsgroup like you were going to look at it, then

click on "TO NEWS" which is on the far left when you're in the newsgroup

page.  This will bring up a box to type a message.

	B)  Leave the newsgroup box like it is.  CHANGE the Subject Box to

something flashy like ... "NEED CASH $$$ READ HERE $$$" ... or ... "FAST

CASH!!"

	C)  Tab once, and you should be ready to type.  Now, retype (only once)

this entire article... WORD FOR WORD ... except to insert your name at

#5 and to remove #1 off the list, plus any other small changes you think

you need to make.  Keep almost all of it the same however!

	D)  When you're finished typing the entire article, click on FILE in

THIS box (just above the SEND button... NOT where it says NETSCAPE NEWS

on the first box)  Now click on SAVE AS in the dropdown menu.  Save your

article as a text file to your C: or A: drive.  DO NOT SEND OR POST YOUR

ARTICLE UNTIL YOU HAVE SAVED IT!  Once saved, move on to Step E below.

	E)  If you still have all of your text, send or post to this newsgroup

now by just clicking the SEND button (just below the FILE dropdown menu

and just above the C: button)

	F)  Here's where you're going to post to 250 or more, newsgroups

....OK... click on any newsgroup then click on "TO NEWS" ... again, in

the top left corner of your screen.  Leave the NEWSGROUPS BOX alone

again, put a flashy subject title in the SUBJECT BOX, hit TAB once and

you're in the body of the message.  Now click on the ATTACHMENT button

(just below the Subject Line) Another window will come up... click on

ATTACH FILE ... now find the file that you just saved in the previous

procedure.  Click ONCE on the file and then click OPEN and then OK.  If

you did this correctly you should now see your file name in the

Attachments Box and it will be highlighted.



IF YOU USE IE EXPLORER it's just as easy ... Holding down the left mouse

button, highlight this article.  Then press the "CTRL" key and the "C"

key at the same time to copy the article.  Then print the article for

your records to have the names of those you will be sending the $1.00

bills to.  Next, go to the newsgroups and press "POST AN ARTICLE".  A

window will open... type in your headline in the SUBJECT area and then

click in the large window below.  Press "CTRL" and then "V" and the

article will be placed in the window.  If you want to edit the article

you can do so and then highlight and copy it again (so your edited

article will be copied again and again to each newsgroup)  Now,

everytime you post the article in a new newsgroup all you have to repeat

is "CTRL" and "V" and press POST.



	G)  That's it!  Each time you do this, all you have to do is type in a

different newsgroup so you can post this message to 250 or more,

DIFFERENT, newsgroups.  I know, I know, ... you've still got 249 to go! 

Don't worry, each successive article will only take about 30 SECONDS

once you get the hang of it.  Remember, 250 is the MINIMUM.. the more

you post, the more money you will make!



That's it... THAT'S ALL THERE IS TO IT... JUST THREE EASY STEPS!!!



You are now in the mail order business and will start receiving your $1

envelopes from various people all over the world within days.  REMEMBER

.... the more newsgroups you post to, the more money you will make!  You

may want to rent a P.O. Box enventually because of all the mail.  If you

wish to stay anonymous, you can come up with a name, such as "manager"

or "investor" ... just make sure all the addresses are CORRECT please.



Now... let me tell you WHY this system works...



Out of every 250 postings, let's say I only receive 5 replies... doesn't

seem like much, does it?  However, you will make $5 cash... not checks

or money orders but CASH ... with your name at #5.



Each additional person who sent you $1 now also makes 250 additional

postings with your name at #4... this is 1000 postings.  On average

then, 50 people should send you $1 with your name at #4... that's $50

CASH in your pocket!



Now, these 50 new people will make 250 postings each with your name at

#3... that's 10,000 postings!  Average return would be 500 poeple...

that's $500.  Each of these people make 250 postings now with your name

at #2... that's 100,000 postings.. average 5,000 returns at $1 each is

$5,000!



Finally, 5,000 people make 250 postings each with your name at #1 and

you get a return of $60,000 before your name ddrops off the list!  And

that's only if everyone on the line made only 250 postings each...

REMEMBER ... the more postings you make, the more money you make!



When your name is no longer on the list, you can just take the latest

posting that is appearing in the newsgroups and send out another $5 to

the names on the current list, putting your name at #5 and start posting

again.  The thing to remember is this... thousands and thousands of

people all over the world are joining the Internet and reading these

articles every day... just like you are right now?!!  So can you afford

NOT to send out your $5 just to see if it works?!  I think NOT!



People have said, "What if the plan is played out and no one sends you

the money?"  So what!  What are the chances of that happening when there

are TONS of NEW honest users and NEW honest people who are joinging the

Internet and newsgroups every day and are willing to give it a try? 

Estimates are at 20,000 to 50,000 users, EVERYDAY, with thousands of

those joining the actual Internet.  Remember, play FAIRLY and HONESTLY

and this WILL WORK .. I promise you.  You just have to be honest.  Make

sure you print this article out right now... also... try to keep a list

of eveyone that sends you money and always keep an eye on the newsgroups

to make sure everyone is playing fairly.  REMEMBER ... HONESTY IS THE

BEST POLICY .. YOU DON'T NEED TO CHEAT THE BASIC IDEA TO MAKE MONEY!!

Good luck to all and please play fairly and you will reap hugh rewards

from this!



By the way, if you try to decieve people by postings the messages with

your name on the list and not sending the money to the people already on

the list, YOU WILL NOT GET MUCH RETURN!  Someone I talked to knew

someone who did just that and he only made $150 after 7 or 8 weeks!! 

Then he sent the 5 $1.00 bills out.. people added him to their lists...

and in 4-5 weeks he had OVER $10,000!



THIS IS THE FAIREST AND MOST HONEST WAY I HAVE EVER SEEN TO SHARE THE

WEALTH OF THE WORLD WITHOUT COSTING ANYTHING BUT FIVE DOLLARS AND A

LITTLE OF YOUR TIME!  DO IT LIKE IT'S LAID OUT HERE...



IT WILL WORK!!

IT SHOULD WORK!!
-- 


_______________________________________
My emails are:
rider@stoat.riga.lv
ARTURSS@r1g.edu.lv
If you have some question then email me please!!!

-- 


_______________________________________
My emails are:
rider@stoat.riga.lv
ARTURSS@r1g.edu.lv  
If you have some question then email me please!!!
Article: 5013
Subject: INTERNET ELECTRONICS DIRECTORY
From: Todd Peterson <elab@netins.net>
Date: Sun, 12 Jan 1997 16:50:10 -0600
Links: << >>  << T >>  << A >>
Who says there's no such thing as a free lunch!

A free, comprehensive listing of over 500 Web sites ofinterest to electronics
enthusiasts and engineers, is available on our web site at:

http://www.netins.net/showcase/elab

If you have an electronics-related web site and would like to add a link to our
resource directory from your site, just cut-and-paste the following HTML into
your page's source code:

<CENTER><P><A HREF="http://www.netins.net/showcase/elab">
<IMG SRC="http://www.netins.net/showcase/elab/eed.gif" 
HEIGHT=48 WIDTH=360 ALT="Embedded Electronics Resource Directory">
</A></P></CENTER>

This will place an attractive 'Electronics Resource Directory' logo onto your page
that will hot-linked to our Directory for your and your visitor's convenience and use.

We thank you for your time and hope the Electronics Directory will be useful to you.
Please let us know if your company would like a free listing for your page in our directory!

Todd Peterson
E-LAB Digital Engineering, Inc.
elab@netins.net
(712) 944-5344

http://www.netins.net/showcase/elab

Article: 5014
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 13 Jan 1997 01:03:58 GMT
Links: << >>  << T >>  << A >>
Sorry, I missed the first part of this discussion but I came across an
interesting site for those interested in space-based hardware.  I don't
believe that it is S-class but Omitron offers an FPGA-based version of the
NASA Standard Spacecraft Computer (NSSC).  See the following web page for
more information:

http://webserver.gsfc.nasa.gov/services/Hardware/nssci.html


-- 

Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

David Erstad <erstad@ssec.honeywell.com> wrote in article
<32D7FCB5.B53@ssec.honeywell.com>...
> Honeywell does not currently have a rad-hard FPGA.  There is a strong
> possibility
> of our developing an SRAM-based FPGA becoming available in the future,
> but there is no
> current product offering.
> 
> As far as I know, there is no class-S, rad-hard SRAM FPGA on the market
> today.
> The Harris effort is no longer active.
> 
> Of course, Honeywell (and one or two others) could readily convert a
> Xilinx 
> design to a rad-hard gate array for flight purposes.
> 
> Friedrich Beckmann wrote:
> > 

Article: 5015
Subject: Problems with XILINX sdt2xnf
From: pcclarke@ozemail.com.au (Peter C Clarke)
Date: Mon, 13 Jan 1997 14:35:32 GMT
Links: << >>  << T >>  << A >>
I'm presently using XACT step version 6.0 and Orcad capture version 6
and am experiencing problems with the sdt2xnf program.

As far as I can tell, I am correctly generating .inf files but run
into problems when using sdt2xnf.

The following message is displayed:

inf2xnf: FATAL ERROR

The message set for "msg" does not exist in any of the standard
message files.
The message set must be defined before program execution can continue.

Return code from 'inf2xnf test1 logfile=sdt2xnf.log=3

I do have a c:\axct\msg directory etc but am not sure what defining
the message set entails.

I did have to fudge the installtion a bit as XACT step would not
reconise newer versions of win32s etc.

I would appreciate any help you may be able to provide.

Thanks in advance.

Article: 5016
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: "Rich K." <rich.katz@gsfc.nasa.gov>
Date: 13 Jan 1997 14:53:40 GMT
Links: << >>  << T >>  << A >>
In the near term, there will be an increasing number of NASA missions
flying DRAMs, including some long-term missions like Cassini to Saturn.  

As discussed earlier, making memories 'appear' to be SEU-immune is quite
straightforward using error-correcting codes.  The level of shielding
needed, if any, is dependent upont the part selected, where it is in the
spacecraft, and the environment it's flying in.  But making this work
(without too much trouble) requires two things: the device does not latchup
up from single particles (SEL or single event latchup) and a faborable
internal organization of the memory.  For the first, fortunately, there are
a number of available devices which are sufficiently immune to SEL.  For
the second, the internal architecture of the device is important, and will
effect the overall SEU reliability of system and the type of ECC employed. 
The easiest codes to work with are the Hamming codes, with most
implementations correcting single-bit errors and detecting double-bit
errors.  These codes permit easy correction on the fly and are very simple
to implement (and if one has time it can be done if FPGAs).  For
bullet-proof applications, it should be noted that high-density commercial
RAMs can be susceptible to single-event, multiple upset effects.  In this
case, for the Hamming code, the chip (for those that are not in the x1
organization) would have to have logically related bits physically
separated so that the errors are correctable (and some commercial memories
are 'unfavorable').  If not, then Reed-Solomon or some other code would be
required, which are more difficult to decode.  Another phenomena for
commercial RAMs (static and dynamic) are stuck-bits.  A standard Hamming
code (SECDED) would work just fine if the memory system didn't add delays
for constant corrections (flow-through EDAC) or if the system design
tolerated it; of course, this makes that particular word now susceptible to
SEU's.  Some memory systems may be able to easily map around stuck bits,
making them a non-issue, such as in computer memories (not including some
hardwired locations like interrupt vectors).  For other applications where
the memory is used as 'programmable logic' (i.e., lookup tables) spare
pages may be needed or true rad-hard rams may be required.

Lastly, some memory devices come with ecc built-in (although not for
radiation).  Devices in this class include some EEPROMs and DRAMs.  For SEU
performance, typically the arrays get protection but not temporary storage
(or configuration registers - which, btw, have been shown to upset and put
the device into a non-functional mode) which are not protected.

There are a lot of techniques for working around memory problems or user
memory upsets in FPGA's: the configuration memory of FPGAs appears to be
more of a challenge for non-rad-hard devices.

rk

Henry Spencer <henry@zoo.toronto.edu> wrote in article
<E3woKD.LJo%spenford@zoo.toronto.edu>...
> In article <5attn9$mkg@hearye.mlb.semi.harris.com>
jws@billy.mlb.semi.harris.com (James W. Swonger) writes:
> > You can get SEU-immune SRAMS and digital ASICs from either of the
above.
> >No, you won't like the price. You can also get SEU-immune PROMs to
reload
> >the SRAM-based FPGAs from, ditto on the cost. If you are that concerned
> >with eliminating failure modes, though, you'll pay the prices or you'll
> >stay on the ground. Anything else will net you an unacceptable
probability
> >of failure...
> 
> Actually, there is an alternative, for memory:  error-correcting codes. 
> Even commercial DRAMs have been flown successfully using ECC and a bit of
> shielding, although admittedly they only lasted (as I recall) a year or
> two (in an elliptical orbit that passed through the Van Allen belts
> regularly). 
> -- 
> "We don't care.  We don't have to.  You'll buy     |       Henry Spencer
> whatever we ship, so why bother?  We're Microsoft."|  
henry@zoo.toronto.edu
> 
Article: 5017
Subject: Re: DES Keysearch by FPGA: $10,000 prize
From: trei@ziplink.net (Peter Trei)
Date: 13 Jan 1997 10:47:45 -0500
Links: << >>  << T >>  << A >>
[added for context]
Peter Trei wrote:
RSA Data Security will soon sponsor a 'DES Challenge', in which
participants are asked to attempt to decrypt a message supplied by
RSA. The first person or group to email RSA the correct key and the
decrypted message will receive a $10,000 prize.
[...]
In 1993, Michael J. Wiener of Bell-Northern Research, published a
paper 'Efficient DES Keysearch', in which he gave a detailed
description of such a keysearch engine, based on custom chips, which
could search the entire keyspace in about 7 hours.
[end of context addition]

-----------------

In <32d97e52.96004437@news.alt.net> z80@digiserve.com (Peter) says: 
>I read this paper a while ago, and while it appears to be detailed, it
>in fact does NOT contain a great deal of information.

Did you read my whole letter? Did you read and understand Wiener's
paper?

I'm not an FPGA expert, so I can't really comment on how much information
is needed. I'm AM very familiar with implementing DES in software, and
he does not seem to have missed much. Can you specify what information
is missing? A copy (in postscript) of Wiener's paper can be found at
http://www.aist-nara.ac.jp/Security/doc/

>Sure, it is easy enough to get a big FPGA and stick DES into it, then
>replicate that design X times (where X is a LARGE number), build some
>sort of supervisory PC-based machine to keep stuffing in the keys, and
>off you go. Any half-competent hardware man can do this, in say 6
>months.

Again, I can't comment on the time to develop an FPGA setup to do this,
but my superficial reading is that any number of FPGA development boards
could do this with no HW changes.

>But detecting if you have the right key is easy only if you have the
>exact known plaintext, specifically the first 8 bytes of it. Anything
>else makes it quite complex. If you are given the first "few" bytes
>then you will find many keys which appear to match, and you will need
>circuitry which does statistical analysis on the rest of the 8-byte
>block, to see if it is ASCII or whatever.

As I specified in my note, this IS a 'known plaintext challenge', in
which we DO know the content of the first 8 bytes. My method of 
searching would run 15 DES rounds in the FPGA, producing one key in 2^32
which would need further checking on a general purpose machine.  

For details on the challenge, see:
	http://www.rsa.com/rsalabs/97challenge/

>Then you have the huge cost of this machine which every crypto book
>says is easy to build. Say a FPGA can do a DES decryption in 1us
>(should be possible with a 32-64MHz clock) you will need 1142 years
>(keyspace 2^55). So to do it in 24 hours you will need 417000 of these
>FPGAs.

>An ASIC could do DES in 100ns or less, if the 16 loops were unrolled
>into one fall-through design. This would go into perhaps 50k gates,
>fine by today's standards.

It's a time/expense tradeoff. I certainly agree that a special purpose
machine to do this in one day would be very expensive. But you're 
missing two points. 

1. Wiener's design has each chip testing keys in an 'assembly line'
fashion, with 1 key/cycle/chip being tested once the pipeline is full.
This is 32-64 times as fast as your estimate. (Caveat: I don't know if
if this rate can be managed on an FPGA).  

2. One day is a *lot* faster than needed to win the challenge. I suspect
that a 2 month target is more reasonable. This cuts the speed requirement
by another factor of 60.

This brings down the chip count to 435 - 217, which is a bit more
managable than 417,000.  If you can fit multiple key search pipelines
on a given FPGA, then you can reduce the chip count even further.

I'm not suggesting that anyone go out and cut metal or fab silicon to
do this; I'm suggesting that with the HW you already have on hand, you
have a much better shot at winning the $10k (and a place in the history
books) than you would in the average raffle.

>Peter Trei wrote:
>>There have been theoretical studies done showing that a specialized 
>>computer "DES cracker" could be built for a modest sum, which could 
>>crack keys in mere hours by exhaustive search. However, no one is 
>>known to have built such a machine in the private sector - and nobody 
>>knows if one has been built in any government, either.

>I wonder why??

Because any organization which produced such a machine for
eavesdropping purposes would have a strong motivation to keep the
device's existance secret, so people would continue to use single DES.

>Peter.

(another Peter)
Peter Trei
trei@process.com
Article: 5018
Subject: ANNOUNCE 8051/8052 microcontroller model now available for FPGA
From: "David Baker" <davidb@evolution.co.uk>
Date: 13 Jan 1997 17:03:18 GMT
Links: << >>  << T >>  << A >>

 Available now.  Richard Watts Associates RAW8052 core targeted
to Altera FLEX10K FPGA.

Occupies approx 1/3 of the logic of a 10K100 part.

Netlist (VHDL, Verilog) or VHDL source available for seamless
migration to ASIC.

To obtain a free evaluation version check our page at
www.evolution.co.uk or contact richardw@evolution.co.uk.


Article: 5019
Subject: Any PEEL22CV10A replacements with more capacity?
From: "Thomas C. Jones" <tjones@aspect.com>
Date: Mon, 13 Jan 1997 10:59:22 -0800
Links: << >>  << T >>  << A >>
Does anyone know of a pin-compatible replacement to the PEEL22CV10A 
offering greater routing capacity and resources?

-Tom
tjones@aspect.com
Article: 5020
Subject: Re: DES Keysearch by FPGA: $10,000 prize
From: "David G. Koontz" <koontz@netapp.com>
Date: Mon, 13 Jan 1997 17:16:40 -0800
Links: << >>  << T >>  << A >>
Peter Trei wrote:
> 
> [added for context]
> Peter Trei wrote:
> RSA Data Security will soon sponsor a 'DES Challenge', in which
> participants are asked to attempt to decrypt a message supplied by
> RSA. The first person or group to email RSA the correct key and the
> decrypted message will receive a $10,000 prize.
> [...]
> In 1993, Michael J. Wiener of Bell-Northern Research, published a
> paper 'Efficient DES Keysearch', in which he gave a detailed
> description of such a keysearch engine, based on custom chips, which
> could search the entire keyspace in about 7 hours.
> [end of context addition]
 

> >Sure, it is easy enough to get a big FPGA and stick DES into it, then
> >replicate that design X times (where X is a LARGE number), build some
> >sort of supervisory PC-based machine to keep stuffing in the keys, 

> >Then you have the huge cost of this machine which every crypto book
> >says is easy to build. Say a FPGA can do a DES decryption in 1us
> >(should be possible with a 32-64MHz clock) you will need 1142 years
> >(keyspace 2^55). So to do it in 24 hours you will need 417000 of these
> >FPGAs.
> 
I believe that an ORCA OR2C040A can do superscalar DES (all 16 rounds
unrolled) somewhere around or better than 30 MHz (30M DES_ops/sec)

I'm still evaluating the routing in the ORCA part, and will probably
write a VHDL model of the FPGA, and program it with generics (one
very large configuration).  There is enough info in the datasheets
to generate timing from it.  I originally thought it would be register
bound, but the registers in an S Box cell can be used for R or C/D.

The critical path is Rn --> xor --> SBox LUT --> xor --> Rn+1.

The loads on the first xor also need to be evaluated.

Now, if there was only an editor I could use for hand layout...

(An ASIC should be at least 10 times as fast without resorting to
 replicating chunks of 16 rounds worth of gates.  The limiting factor 
 is thermodynamics.  Call it 8 sets of superscalar DES or 2.4 Billion
 DES ops/second with a 300 MHz clock  (0.35 micron), 3.3V,  
approximately 350K gates.)
Article: 5021
Subject: Software available for distributing CAD applications across workstations
From: davida@shemesh.cit.gu.edu.au (David Abramson)
Date: 14 Jan 1997 12:14:47 +1000
Links: << >>  << T >>  << A >>

Active Tools is announcing the availability of Clustor beta, a program
to manage computationally intensive tasks.

Clustor supports computational experiments where a single program is 
executed with multiple different input parameters. This is often required
when exploring different design options with CAD software.
For such programs, Clustor can save a great deal of time and effort. 

Clustor: 

	can speed up your computation by distributing the  
	load over a network of workstations.

	can help manage your computation by providing an easy to use
	graphical interface for generating the input parameters and 
	for controlling the execution.

Clustor is easy to use with existing programs, since no
changes are required to the code. Clustor is simple to install with 
our installation program, and requires no root privileges. 

A number of case studies in using Clustor are available at our Web site.
In one case study we used Clustor to control the execution of the 
NeoCAD "place-and-route" utility on a multi
FPGA based circuit. Clustor allowed us to experiment with a number of 
design parameters, and to explore different design options. 
The results are visualised and show the effect of varying these parameters.
(Specific details of this study are available from
http://www.activetools.com/neocad/neocad.html)

More details on Clustor and free beta versions of software are available at:

	http://www.activetools.com

------------------------------------------------------------------------------
                           ACTIVE TOOLS Inc.
		          www.activetools.com
                        246 First St, Suite 310 
                        San Francisco, CA 94105
                          Fax: (415) 680 2369
                      E-mail: info@activetools.com



----------------------------------------------------------------------------
David Abramson                        phone: +61 7 3875 5049
Associate Professor                   fax:   +61 7 3875 5051
Deputy Dean (Research)                mobile: 018 191 507
School of Computing & Inf. Technology e-mail: davida@cit.gu.edu.au
Griffith University                   WWW:    http://www.cit.gu.edu.au/~davida
Nathan, Qld, 4111                     
----------------------------------------------------------------------------


Article: 5022
Subject: Re: Efficient DES Keysearch
From: hamilton <hamilton@dimensional.com>
Date: Mon, 13 Jan 1997 19:47:47 -0700
Links: << >>  << T >>  << A >>
> Peter Trei wrote:
> >
> > In 1993, Michael J. Wiener of Bell-Northern Research, published a
> > paper 'Efficient DES Keysearch', in which he gave a detailed
           ^^^^^^^^^^^^^^^^^^^^^^^

Is this paper available on the net somewhere ??

thanks
Article: 5023
Subject: Great Xilinx FPGA Kits & prices
From: "James Fakas" <jjfakas@erols.com>
Date: 14 Jan 1997 03:35:41 GMT
Links: << >>  << T >>  << A >>
These are extremely good deals. They include a PC ISA FPGA test board board
along with the FOUNDATION software from XILINX!

Great deals!!!

Here are other kit prices:

APS-X84-FB X84 board with the Foundation Base Software....$650.00

APS-X84-FBV same with VHDL............$1295.00

APS-X84-FS X84 board with Foundation Standard Software....$1300.00

APS-X84-FSV same with VHDL..............$2500.00

The contacts are at

aaps@erols.com
http://www.erols.com/aaps


Article: 5024
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Tue, 14 Jan 1997 04:37:06 GMT
Links: << >>  << T >>  << A >>
In article <01bc0161$d44246a0$6e0db780@Rich> "Rich K." <rich.katz@gsfc.nasa.gov> writes:
>...[DRAMs in space]  But making this work
>(without too much trouble) requires two things: the device does not latchup
>up from single particles (SEL or single event latchup) and a faborable
>internal organization of the memory.  For the first, fortunately, there are
>a number of available devices which are sufficiently immune to SEL...

Actually, if memory serves, the first requirement isn't quite as stringent
as you might think:  it is typically possible to power-cycle DRAM briefly
to break a latchup without losing the memory contents.  (Particularly if
you are willing to do some testing and selection of parts, commercial DRAMs
generally exceed their specs for data retention and refresh interval by a
fairly wide margin.)  Admittedly, you don't want to do it *too* often.
-- 
"We don't care.  We don't have to.  You'll buy     |       Henry Spencer
whatever we ship, so why bother?  We're Microsoft."|   henry@zoo.toronto.edu


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