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One of our thesis students is designing a GAL programmer as a project. He's been unable to pry loose the timing information from the manufacturers: they only want to give it out to manufacturers of commercial programmers. We have most of it figured out. Anyone know the timing specs? We're especially interested in the 16V8, 20V8 family of devices. Thanks a bunch. Peter -- Peter Hiscocks Phone: (416) 979-5000 Ext 6109 Department of Electrical Engineering Fax: (416) 979-5280 Ryerson Polytechnic University, Toronto, Canada ******************************************************************* * UNIX: the only operating system that requires a 15 page manual * * to describe how to make the delete key work. * *******************************************************************Article: 5076
In article <rogerlo9ovv95.fsf@trout.coelacanth.com>, Roger Williams <roger@coelacanth.com> writes: [snip] > Unfortunately, one important application for the XTL stage was as a > clock recovery VCXOs, which isn't available off the shelf (or for > "around one dollar" either). I agree that oscillator design may be > beyond the capability of some digital designers, but there are > certainly plenty of competent datacomm engineers out here. [snip] Could you please say some more. I can't quite picture how to mix the xtal pins in with digital logic to make a PLL. If you are using them as digital signals, won't normal IOBs on new parts will work just as well? If you are using them in their analog mode how do you control anything from the digital side?Article: 5077
On 20 Jan 1997 14:27:25 GMT, RODNEYM@rodneym.ibm.net (Rodney
Myrvaagnes) wrote:
>On Sun, 19 Jan 1997 09:30:47 +0000, Leon Heller <leon@lfheller.demon.co.uk> wrote:
<Snip>
>He needs something that puts out arbitrary word-length microcode.
>A cross assembler won't do unless his microcode word just happens
>to be 32 bits, for instance.
<Snip>
About a year ago I had a similar need and ordered Cross-32 from
Universal Cross Assemblers (506) 849-8952. The cost was $199.
It allows up to 10 byte data instruction word lengths. I didn't get
much of a chance to play with it, but the documentation was reasonable
and for creating an assembler for a custom processor it's dosn't seem
too bad. Lacks some useful features like a linker (source code linked
only). Output is not relocatable, Numeric constants and instruction
limited to a maximum 32 bit values. Does support macros.
Hope this helps,
Mark A. Adams
us017033@mindspring.com
Article: 5078Hello, I am a P.h.D student at OhioU, I have been assigned to writ a proposal for an FPGA development lab. And since I am new in this field, can any one mail me a list of the most important things that have to bee included in the proposal. we are going to use PC Pentium200 station and Viewlogic's Workview Office. Also what is the best (in terms of compatiblity with other vendors) FPGAs testing borad. Thank you in advanced. aalsolai@homer.ece.ohiou.edu --Article: 5079
Ahmad Alsolaim aa939788@oak.cats.ohiou.edu wrote: > I am a P.h.D student at OhioU, I have been assigned to writ a > proposal for an FPGA development lab. And since I am new in this field, > can any one mail me a list of the most important things that have to bee > included in the proposal. we are going to use PC Pentium200 station and > Viewlogic's Workview Office. If you're gonna use Workview Office, I suggest that you spend the extra bucks and get the monitor-pad option. This is a protective pad that goes around your monitor to prevent injury as you repeatedly beat your head against it.Article: 5080
Denis Lachapelle <sysacom@cam.org> wrote in article <sysacom.36.139EE286@cam.org>... > What would be the cheaper FPGA having more of 2kbyte of internal SRAM > (20ns MAX), and more than 3000 gates? > I have found the Altera EPF10k10 and the Xilinx XC4003, could you suggest > other part? Neither of the above. 2 KB of SRAM is 16,384 bits of SRAM. The XC4003E stores up to 3,200 bits: 10 x 10 CLBs x 32 bits/CLB. The 10K10 stores up to 6,144 bits: 3 EABs x 256x8 bits/EAB. The XC4020E meets your needs: use 2/3 of the device for SRAM (2/3*28*28*32) and 1/3 for logic. According to www.marshall.com, an XC4020E-4 is $169 Q1. The EPF10K40 on up also provide 2 KB of SRAM. An Oct. 28, 1996 Altera press release said "The 50,000-gate 0.35-micron 3.3-V EPF10K50 is sampling now. The North American price is $195 in 100-unit quantities and is projected at $69 in 5,000-piece units by the middle of 1997." Jan GrayArticle: 5081
What would be the cheaper FPGA having more of 2kbyte of internal SRAM (20ns MAX), and more than 3000 gates? I have found the Altera EPF10k10 and the Xilinx XC4003, could you suggest other part? Thank you, Denis Lachapelle, sysacom@cam.org Sysacom R&D plus inc. www.cam.org/~sysacom tel 514 585-6396, fax 514 582-3231Article: 5082
Virtual Computer Corp. announces The First Reconfigurable Processing Unit on a PCI Board
H.O.T. Works -- The Complete PCI-XC6200 Development System.
H.O.T. Works includes:
HARDWARE
* PCI-XC6216 Xilinx Reference Board
-- 512K bytes of fast SRAM
-- PCI Mezzanine Connectors for daughter boards
-- Programmable Oscillator
SOFTWARE
* Xilinx's XACT-6000-- A map, place and route tool set
* A XC6200 VHDL Elaborator
* WEBSCOPE 6200 -- A Java tool for real-time design emulation
using the PCI-XC6200 board.
* Hardware Object Technology Interface Kit --- for insertion of designs
into executable 'C' language programs
* LOLA Programming System -- a complete HDL Tool Set for the
PCI-XC6200 Board & XC6200 including editor, mapper, placer and router.
Price: $995.00 USD
http://www.vcc.com/products/pci6200.html
VCC Training Course Announcement:
Take the Course and Walk Away with the Knowledge and H.O.T.Works
A Two Day Course on Programming the New Xilinx XC6200 Series RPU
March 11-12 & 13-14 in San Jose Seat are Limited -- sign up now
Price: $1995.00 includes two-day course and the H.O.T. Works package
Register Now!! http://www.vcc.com/vcct1.html
-----------------------------------------------------------------------------------------------------------
Virtual Computer Corp.
6925 Canby Ave Suite 103
Reseda CA 91335 USA
tel: 818-342-8294 fax: 818-342-0240
email jas@vcc.com
http://www.vcc.com
Article: 5083Viewlogic ships JED2AHDL with Workview Office 7.2. It is a Data I/O program that will convert the .jed file to an Abel source file. This should give you something that is 'humanly readable'. There is also J2VHDL, but I don't know what it does... If you want to e-mail me the .jed file, I'll run it through JED2AHDL and e-mail you back the results. Austin Franklin ..dakroom@ix.netcom.com.Article: 5084
My thesis is designing an universal GAL programmer. I have got only ONE programming method. Because of internal incompatibility of 16v8s and 20v8s from different manufacturers my method isn't universal. Does anyone know differences between SGS's and AMD's method? Thanks for your help. AttilaArticle: 5085
You have a problem. Take a "16V8". This will use slightly different algorithms, depending on the device speed, suffix, manufacturer, etc. This, as well as some other rather more dubious reasons, is why PLD programming data is not generally available. (The dubious reasons being that e.g. a PLD programmer vendor can wash his hands of a bug in some algorithm, simply by saying that the PLD vendor changed the algorithm...) You could build a programmer for one device, or a small range, e.g. Lattice GAL16V8-15LNC or whatever. Done properly, a programmer must retrieve the electronic device ID, and if it does not identify that *exact* ID to one of its algorithms, it should refuse to program that device. >One of our thesis students is designing a GAL programmer as a project. He's >been unable to pry loose the timing information from the manufacturers: they >only want to give it out to manufacturers of commercial programmers. > >We have most of it figured out. Anyone know the timing specs? We're >especially interested in the 16V8, 20V8 family of devices. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5086
Recently our company had a demonstration of the products from Gatefield, a division of Zycad Corporation. We were very much impressed with the GF100K family of Gatefield's FPGA's that range in capacities from 9,000 to 100,000 Gates. How does this compare to Xilinx and Altera who offer less than Gatefield? ========================================================Article: 5087
We have made evaluation copies of our Report Manager software available
at the website: http://www.ez-synthesis.com.
(Those w/o web access :( :( can email for instructions about how to
access otherwise).
The software runs on Solaris 2.5 (SunOS5.5) and Linux 2.0.
------------------------------------------
Report Manager is a tool for correlating one or more margin/slack timing
reports as generated by the (Synopsys Design Compiler) dc_shell command:
report_timing -path end
Report Manager is valuable for correlating the endpoint timing margin
for
simple modules or entire chips:
o tracking timing convergence through various stages:
1st pass synthesis -> floorplanning -> IPO -> P&R -> ...
o designers can compare "what-if" (different compile) runs
o correlating multiple ASIC vendors' performance
o easily visualizing entire timing performance: too much slack is
not always a good thing !
---
Synthesis Solutions, Inc.
http://www.ez-synthesis.com
vmail: (415) 431-6429
Article: 5088Peter wrote: > Done properly, a programmer must retrieve the electronic device ID, > and if it does not identify that *exact* ID to one of its algorithms, > it should refuse to program that device. I agree, _BUT_ programmers also need some flexibility on this. When you find that the only tube of devices in stores has a subtly different ID, it's 3am in the R+D department and the programmer manufacturer doesn't have a web site with new algorithms, I'd hope there was a button to the effect of "Yes, I know, but give it a go anyway, dammit", possibly followed with extreme verification. Steve. (In the past, I've had to desolder PALs from other projects to satisfy a particlarly obsessive programmer. Not helpful)Article: 5089
We have a XC4013E which should to be configured using asynchronous peripheral mode (and more FPGA which should be configured afterwards). Assume that PROGRAM has been held low for a time long enough in order to start reconfiguration. We do not really understand how the (first) FPGA behaves. According to the data book it 1. passes a phase where configuration memory is cleared, 2. waits for INIT to go high 3. waits for 50 to 250 microsecs 4. samples the mode lines 5. finally reads the first byte of the configuration data stream Question: How can one find out when the first byte can be written to the FPGA for configuration? It seems that according to the description on page 4-74 in the XILINX data book (version 1.02, June 96) RDY/BUSY cannot be used. Can one use the CCLK output of the FPGA? Figure 48 on page 4-59 says that after sampling the mode lines ``Master CCLK goes active''. Does this mean that it goes high and that it is low before? Or is CCLK tristate before? Any hints are very much appreciated. Thanks ThomasArticle: 5090
COMPUTER ENGINEERS AND ELECTRICAL ENGINEERS Join a rapidly expanding electronic design firm working with cutting edge technologies such as ASIC design and WILDFIRE(tm), Xilinx FPGA based reconfigurable computing. We encourage initiative and creativity and offer opportunities for continued development of analytical and technical ability. ASIC DESIGN ENGINEERS work with state-of-the-art design tools to solve challenging analog/digital design problems on the cutting edge of technology. Positions available for entry level as well as senior designers with 3+ years of practical experience in ASIC, FPGA or MCM design. BSEE/CpE/Physics min. WILDFIRE(tm) APPLICATION ENGINEERS create revolutionary new applications and computer architectures. WILDFIRE(tm), Xilinx FPGA Based Reconfigurable High Performance Parallel Processing on WILDFIRE(tm) is the wave of the future in computing technology. Software Designers work with multiple operating systems; device drivers; C /C++ and 68000 embedded programming. Hardware Designers are skilled in VHDL, synthesis and simulation, FPGA design, PCB design. BSCS/CpE/CS/Physics minimum. Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130, Annapolis, MD 21401 email: personel@annapmicro.com http://www.annapmicro.com (410) 841-2514 (301) 970-2672 FAX: (410) 841-2518 Principals Only U.S. citizenship required. January 22, 1997 COMPUTER ENGINEERS AND ELECTRICAL ENGINEERS Join a rapidly expanding electronic design firm working with cutting edge technologies such as ASIC design and WILDFIRE(tm), Xilinx FPGA based reconfigurable computing. We encourage initiative and creativity and offer opportunities for continued development of analytical and technical ability. ASIC DESIGN ENGINEERS work with state-of-the-art design tools to solve challenging analog/digital design problems on the cutting edge of technology. Positions available for entry level as well as senior designers with 3+ years of practical experience in ASIC, FPGA or MCM design. BSEE/CpE/Physics min. WILDFIRE(tm) APPLICATION ENGINEERS create revolutionary new applications and computer architectures. WILDFIRE(tm), Xilinx FPGA Based Reconfigurable High Performance Parallel Processing on WILDFIRE(tm) is the wave of the future in computing technology. Software Designers work with multiple operating systems; device drivers; C /C++ and 68000 embedded programming. Hardware Designers are skilled in VHDL, synthesis and simulation, FPGA design, PCB design. BSCS/CpE/CS/Physics minimum. Annapolis Micro Systems, Inc. 190 Admiral Cochrane Drive, Suite 130, Annapolis, MD 21401 email: personel@annapmicro.com http://www.annapmicro.com (410) 841-2514 (301) 970-2672 FAX: (410) 841-2518 Principals Only U.S. citizenship required. January 22, 1997Article: 5091
IEEE/ACM International Workshop on Logic Synthesis
Granlibakken Resort, Lake Tahoe, California,
May 23-26 (??), 1997
http://www.ee.princeton.edu/iwls97.html
Call for Participation
Logic Synthesis has traditionally focused on optimization techniques
for combinational and sequential circuits through the manipulation of
Boolean equations and state machines. IWLS '97, the sixth workshop in
this series, seeks presentations both on these topics and on new directions
in synthesis-based design methodology. Topics of interest include:
Area, timing, power optimization Logic synthesis systems
CMOS, ECL, GaAs optimization Designer experiences with synthesis
Two-Level logic optimization Interaction with physical design
Multi-Level logic optimization Incremental synthesis / ECO support
FSM optimization Asynchronous logic synthesis
Sequential circuit optimization Formal verification
Retiming and resynthesis Optimization at the RTL level
Technology mapping Timing verification
FPGA and PLD synthesis Testing and synthesis for test
Don't-cares and Boolean Relations Interaction with module generators
Symbolic Synthesis Use of synthesis in new applications
Synthesis in FPGA based emulation
Authors may submit extended abstracts for their proposed presentation.
These must be no less than 1000 words and no more than 2500 words.
These abstracts are *not* intended to be complete papers, but rather should
convey the main ideas of the proposed presentation. We encourage submissions
in the early stages of research which may highlight important new problems
without necessarily providing complete solutions. The abstracts may be
submitted by e-mailing self-contained Postscript files to
iwls-submit@ee.princeton.edu by February 15, 1995. Acceptance notices will
be sent by March 31, 1995. A set of workshop notes will be distributed at
the conference. There will be no published proceedings.
Benchmarks: A benchmark set is being assembled by the CAD Benchmarking
Laboratory. To contribute new benchmarks, or to obtain information
about the existing suite, please write:
benchmarks@cbl.ncsu.edu (??)
About IWLS
IWLS '93 introduced a number of format changes from previous
workshops, which the committee tentatively intends to maintain for
IWLS '97. These include an open program with high acceptance rate,
heavy use of posters and short talks for presentation, and large
amounts of time in the schedule for poster presentations. In addition,
IWLS '97 will emphasize open discussions and ongoing research which
are not provided by the traditional conference format.
About Granlibakken
The Granlibakken Conference Center is located in Tahoe City on the
west shore of Lake Tahoe, 180 miles east of San Francisco. It boasts
160 rooms, clustered into two- and three-bedroom condominiums. Each
bedroom is an attractive hotel room with private bath. Many of the
clusters share a kitchen, living room and dining room -- a miniature
lobby for private meetings. Organizations sending several people to
the workshop may wish to rent entire two- and three-bedroom
townhouses.
The Granlibakken management has reserved space on Tuesday, May 23rd
for organizations who wish to hold private, one-day workshops
immediately preceding IWLS, and have agreed to charge organizations
the IWLS conference rate for these meetings. Contact Mary Brown at
Granlibakken sales (1-800-552-4494) for details.
Granlibakken is within 10 minutes' drive of the West's premier ski
resorts: Alpine Meadows and Squaw Valley USA. When California enjoys
high snowfall, both areas remain open until Memorial Day. A wealth of
hiking trails snake through the area. Weather permitting,
Granlibakken's tennis courts and pool will be open for use.
The weather in late May is variable; warm, sunny days and cool clear
nights are the rule.
Getting There
Granlibakken is easily reached from either the San Francisco Bay Area
or Reno, NV. Take Interstate 80 to Truckee. From there, follow State
Route 89 south to Tahoe City. Turn right at the stop light in Tahoe
City. After 1/4 mile, turn right on Granlibakken road and proceed to
the end.
Contacts/Executive Committee
GENERAL CHAIR:
Patrick C. McGeer
Cadence Berkeley Laboratories
(408) 428-5325
mcgeer@cadence.com
VICE-CHAIR: (??)
John Conover
Bay Microsystems
(408) 321-6416
john@johncon.com
ASSOCIATE CHAIR: (??)
Masahiro Fujita
Fujitsu Laboratories of America
(408) 456-1151
fujita@fai.com
PROGRAM CHAIR:
Sharad Malik
Princeton University
(609) 258-4625
sharad@ee.princeton.edu
ASIAN CHAIR:
Tsutomu Sasao
Kyushu Institute of Technology
+81-948-29-7675
sasao@cse.kyutech.ac.jp
EUROPEAN CHAIR:
Gabriele Saucier
INPG/CSI
+16-76-57-46-87
saucier@imag.fr
BENCHMARK CHAIR:
Franc Brglez
North Carolina State University
(919) 248-1925
brglez@cbl.ncsu.edu
Technical Program Committee
Pranav Ashar NEC
Michel Berkelaar TU-Eindhoven
Robert K. Brayton UC Berkeley
Franc Brglez NCSU
Giovanni DeMicheli Stanford University
Srinivas Devadas MIT
Antun Domic Cadence
Masahiro Fujita Fujitsu
Wolfgang Kunz University of Potsdam
Luciano Lavagno Politecnico Torino
Ken McElvain Synplicity
Rick McGeer Cadence
Sharad Malik Princeton University
Shin-ichi Minato NTT
Massoud Pedram University of Southern California
Richard Rudell Synopsys
Tsutomu Sasao Kyushu Institute of Technology
Gabriele Saucier INPG
Ellen Sentovich Cadence
Fabio Somenzi CU Boulder
Leon Stok IBM
Sponsored by the IEEE Computer Society, Technical Committee on VLSI,
in co-operation with ACM/SIGDA.
--
Sharad Malik sharad@ee.princeton.edu
Associate Profesor 609-258-4625
Dept. of Electrical Engineering 609-258-3745 Fax
Princeton University http://www.ee.princeton.edu/~sharad
Article: 5092In article <19970122140801.JAA03092@ladder01.news.aol.com>, dftxpert@aol.com (Dftxpert) wrote: >Recently our company had a demonstration of the products from Gatefield, >a division of Zycad Corporation. > >We were very much impressed with the GF100K family of Gatefield's FPGA's >that range in capacities from 9,000 to 100,000 Gates. > >How does this compare to Xilinx and Altera who offer less than Gatefield? > >======================================================== I had a friend at Intel using one. He couldn't get speed (he only needed 16 MHz, it ran at 1.7); when they recently changed their architecture to improve speed/routing the part he was in lost something like 80 of it's user I/Os which bumped him out of it for good. Ask them about that change; it sounded pretty funny. WayneArticle: 5093
Hi, I wrote a quite long verilog specification for an FPGA. I have to synthetise it, in order to implement it in a Xilinx xc4025 FPGA. So far I tried to do it with the Synergy tool in the Cadence package, but without any success. Does a package exist with which I can directly synthetise the FPGA, without before translating the verilog specification to vhdl? If not, what tool do you suggest in order to accomplish my task? Thank you, Francesco Vass Institute for Biomedical Engineering, Swiss Federal Institute of TechnologyArticle: 5094
Dftxpert <dftxpert@aol.com> wrote in article <19970122140801.JAA03092@ladder01.news.aol.com>... > Recently our company had a demonstration of the products from Gatefield, > a division of Zycad Corporation. > > We were very much impressed with the GF100K family of Gatefield's FPGA's > that range in capacities from 9,000 to 100,000 Gates. > > How does this compare to Xilinx and Altera who offer less than Gatefield? A signature and a company name would add some extra credibility to these comments. Otherwise, IMHO, it appears to be a commerical advertisement. Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5095
Interesting. What's that in English?
--
--- Chuck Morrill ---
"Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability." (TI data sheet)
Article: 5096
Hi folks:
In article <32E533DE.7645@netcom.com>, vcc <vcc@netcom.com> wrote:
>Virtual Computer Corp. announces The First Reconfigurable Processing Unit
^^^^^
>on a PCI Board
[Rest deleted]
Is this true? What of the DEC Pamette, which (AFAIK) came out last
year:
http://www.research.digital.com/SRC/pamette/
(I don't want to knock VCC; they've got some great stuff. But where's
the truth in advertising?)
Phil
Article: 5097Having long used Altera devices, I grew accustomed to first rate telephone support for their software and device information. Now working on a contract that specifically requires use of a Xilinx part, I am beginning to realize easy it is to take that support for granted. The problem began 8 days ago, as I went to the Xilinx web site to find out what kind of software would be required to read a pile of schematics for an XC5206 design. There was almost no information on the site at all. So I tried calling Xilinx. It took two tries to get an extension of someone that would actually call back. The response ? "Call the local rep, and ask them". It took me another three days for the rep to study the problem and recommend a package. Now purchasing is working with the distributor, to buy a copy of the specific foundation package. Due to some sort of typo in the system, the desired package doesn't exist ! But we can get the closest equivalent for 2X the price, with 2 week delivery !! All this, and then I have to get a Win95 (or 3.1x) computer since the GUI version won't run on NT. If anyone is getting started in the PLD area and is making an Altera vs Xilinx decision, I recommend that they include in their criteria ease of use of the tools and company support. In my case, the www sites foretold a lot about the two organizations.Article: 5098
George Pontis <geo@z9.com> wrote: >Having long used Altera devices, I grew accustomed to first rate >telephone support for... I have no experience with Xilinx. But I can agree that Altera's support is first rate. We jumped into FPGA design about a year ago and I have no regrets about going with Altera.Article: 5099
Hello Max Plus 2 User
I have a Problem with the Software version 7.1
My Problem ocured also with version 7.0
The Problem is: If i compile a 10K design i get an internal error at 5% in the
SNF Extractor.
If i compile the design with a 10KA or MAX 7000 or MAX 8000 it works.
Only with 10K i have those problems.
I send you a small GDF File wit my Problem.
My System : Win 95
Pentium 166 Mhz
90 Mb Ram
If there is anybody out there who knows something about this let me know.
Thanks a lot
#########################################################
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# Fa. IBT Nachrichtentechnik GmbH #
# Tel. ++49 6074/8948-0 #
# Fax. ++49 6074/8948-90 #
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