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Messages from 5125

Article: 5125
Subject: Re: Altera support better than Xilinx
From: George Pontis <geo@z9.com>
Date: Fri, 24 Jan 1997 16:49:26 -0800
Links: << >>  << T >>  << A >>
Brad Taylor wrote:

> Well, it might be that you are just a bit more familiar with Altera than
> Xilinx.  I find it strange to admit it after years of bitching, but
> Xilinx really does have some pretty decent software and support.

As the author of the original posting, I must say that since that time I
have been contacted by several people at Xilinx that were seriously
concerned that I should have had the problems that I reported, and have
helped me get the appropriate software on the way.

Your comments about the differences between the various families
available from Altera and Xilinx are quite interesting. I thank you for
taking the time to share your experience, and know how time consuming it
can be to sort through the consequences of choosing one architecture or
another.
Article: 5126
Subject: Re: FPGA & division
From: Ray Andraka <randraka@ids.net>
Date: Fri, 24 Jan 1997 19:21:54 -0800
Links: << >>  << T >>  << A >>
Vanni FADONE wrote:
> 
> I'm gathering some material about implementing division with FPGAs; in
> particular I'd like to use Xilinx XC40xx.
> Can anybody help me?
> I know there is an article regarding it on the "Journal of VLSI Signal
> Processing" (v 7 n 3 May 1994  p 271-285), but I can't find it. The
> authors of that article are M.E.Louie and M.D.Ercegovac (UCLA).
> 
> If you think you've something of interesting for me, please e-mail it to
> me.
> I would appreciate any help you may be able to provide.
> Thanks in advance.

Well, you can do it using CORDIC.  It is probably not the most efficient
technique, but it does work.  A pipelined parallel solution for a 12 bit
divider takes about half of a 4013 and will run at about 50Mhz in the -2
part.  The pipeline latency is 12 clocks.  

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 5127
Subject: ABEL->AHDL
From: "Gabor V. Gulyas" <gabor@robiomat.com>
Date: Sat, 25 Jan 1997 08:35:07 +0000
Links: << >>  << T >>  << A >>
Hi ,

are there any free ABEL->AHDL translators ?

 Any helps are welcomed, thanked in advance,
			
			Gabor
Article: 5128
Subject: Re: Altera support better than Xilinx
From: Steve Wiseman <steve@sj.co.uk>
Date: Sat, 25 Jan 1997 11:49:04 +0000
Links: << >>  << T >>  << A >>
George Pontis wrote:

> As the author of the original posting, I must say that since that time I
> have been contacted by several people at Xilinx that were seriously
> concerned that I should have had the problems that I reported, and have
> helped me get the appropriate software on the way.

This has been my experience, too. When my vendor stopped black-holing by
questions (by saying "Yes, it's with Xilinx, they'll contact you"), and
I actually got to speak to a Xilinx chap, they were, without exception
competent and helpful. More of a problem were the problems with the
Viewlogic software bundled with the Xilinx tools. This was obviously
well behind what Viewlogic were shipping to 'real' customers, with no
clear path for tech support. Bug-free is not a term I would use.  I've
now defected to Altera, where I'm happy. The tools work, there's one
phone number for tech support, and no passing the buck. I like that. (I
also get about 2-3 times as much VHDL-generated FPGA per GBP, which
seems to make my customers happy, too)

Message to tool-builders. 
If your documentation / manuals are wrong / inadequate then your
customers _will_ require tech support. If that is not available, your
customers will rant.

  Steve
-- 
Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK
Desk +44 1223 578524 (Fax 578524) Group +44 1223 578518   steve@sj.co.uk
Article: 5129
Subject: Re: GAL programming timing
From: zx80@dgiserve.com (Peter)
Date: Sat, 25 Jan 1997 13:00:39 GMT
Links: << >>  << T >>  << A >>

>I agree, _BUT_ programmers also need some flexibility on this. When you
>find that the only tube of devices in stores has a subtly different ID,
>it's 3am in the R+D department and the programmer manufacturer doesn't
>have a web site with new algorithms, I'd hope there was a button to the
>effect of "Yes, I know, but give it a go anyway, dammit", possibly
>followed with extreme verification. 

I agree too with your desire. But I wish it was as simple as this.

Unce upon a time, we used 1000s/month of a particular 16V8-25 (can't
remember whether National or Lattice). The programmer was a big-name
UK firm, also selling in the USA. It was an 8-gang programmer. This
went for years, until that GAL became obsolete. 

We changed to a 16V8-15. We found about 10% failed to program. At
first, we returned them to the supplier, who accepted them without a
word. But later we found out that the programmer did not support the
new device, EVEN THOUGH it was listed in the supported device list for
it. And it should have rejected it - a bug.

When I contacted the programmer vendor with this evidence, they
immediately went into a defensive mode, heading all letters "without
prejudice" - a UK legal term which prevents such a letter being used
in evidence in a court. 

They could probably see the obvious: those which *did* program were
(as we found out even later) over-voltaged, and probably had an
impaired life, with potentially huge liabilities if products started
to fail in the field.

I tried to contact AMD, National, Lattice etc, but came up against a
brick wall, especially when I told them I was gathering evidence
against the programmer vendor. (I would love to name him, but would
have to use a remailer :).

And I could tell you several other horror stories.

So - the PLD programming business really stinks.

With EPROMs, you can (generally) use the old "50ms pulse" algorithm,
and provided you can select 12.5/21/25V Vpp (IIRC) you can program
almost any EPROM, even if the vendor's recommended algorithm is far
more complex. You can also use the much faster "apply 1ms Vpp pulses
until the bit changes to 0, then give it four more" method. You can
even do this at VCC=5.5V, for good measure. And it works. But not so
with GALs. There are so many subtle variations.

This is why I have avoided the small-league programmer vendors - they
cannot possibly even begin to test their products with the "5000
devices supported with manufacturer-certified algorithms" !!

But I have still burnt my fingers, even with the biggest (American)
name in the business. Out of 10 very common devices, 3 did not work.

As I say, the business really stinks. But I cannot think of a solution
to building a "general" programmer for GALs.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5130
Subject: Altera MAX+Plus II 10K timing model changes
From: colley@adi.win.net (Stephen Colley)
Date: Sat, 25 Jan 1997 14:43:01 GMT
Links: << >>  << T >>  << A >>
This is just a heads up on changes in the timing model for 10K
devices in Altera MAX+Plus II from version 7.0 to 7.1.

We have a 10K50 design running at 50MHz which was developed under
7.0 and simulated just fine. Same design simulated under 7.1 went
down in flames with many, dreaded, setup and hold time violations
and put us back to the drawing board.

Heed the warning concerning preliminary timing specifications put
out by the fitter. Altera tech support confirmed the timing model
change. 


--
Stephen Colley
Access Dynamics, Inc.

colley@accdyn.com
voice: 505-345-7637
FAX   :505-345-7831
www.accdyn.com
Article: 5131
Subject: Re: FPGA & division
From: "John L. Smith" <jsmith@univision.com>
Date: Sat, 25 Jan 1997 10:11:26 -0800
Links: << >>  << T >>  << A >>
Jose Paredes wrote:
> 
> Vanni FADONE wrote:
> >
> > I'm gathering some material about implementing division with FPGAs; in
> 
> How fast does the division need to be? Of the top of my head I can think
> of two ways: Newton-Raphson (I don't think I spelled that right) and a
> Cordic algorithm. They are both iterative schemes that are well suited

From "Numerical Recipes",
N-R uses U = 1/V calculated by

Ui+1 = Ui * ( 2 - V * Ui )

iterated to required precision. This is two multiplies and an addition.
For FPGA implementation, rewrite as

Ui+1 = 2*Ui - V*(Ui)**2

which uses a square, a multiply, and an add. Square is cheaper than
multiply in 40xx. CLB requirements depend on precision. Pipeline as
required to acheive desired speed.

Don't know whether N-R is cheaper than CORDIC, maybe Ray Andraka has
looked at it.

-- 
John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
Univision Technologies, Inc. | those who are once-and-a-half witted
6 Fortune Dr.                | with the half-witted, because we
Billerica, MA 01821-3917     | appreciate only a third part of their wit.
jsmith@univision.com         | - Henry David Thoreau
Article: 5132
Subject: Re: Processorless FPGA computer help
From: "John L. Smith" <jsmith@univision.com>
Date: Sat, 25 Jan 1997 10:54:17 -0800
Links: << >>  << T >>  << A >>
David Hobarth wrote:
> 
> Anyone have any ideas on how to "manually" configure an FPGA outside
> of a development environment such as orcad/viewlogic/etc.? I already
> talked to Xilinx and they won't release that kind of data for their
> 4xxxEX series (or for the 3xxx or 4xxx series, for that matter), and
> the 6200 series they recommended has no such data in the data sheet as
> I was told. I understand their position on security, but that doesn't
> get me anywhere. Any solutions?

It is a straightforward, but extremely tedious process to decode
the configuration bit-stream. Use Xact to set up a part, save the bit
stream, change the configuration in a small way, compare the new
bitstream with the old, repeat ad nauseum.

 I was forced into this when I had to fit a programmable comparator
into a 3042, but didn't have the FF's and LUT logic available to
implement it conventionally. By modifying the LUTs directly
through the configuration bitstream, a much more compact circuit
can be acheived.

While it's possible to decode it, Xilinx doesn't recommend it, and
after going through the process, neither do I. If you make a mistake
in modifying the bitstream, you can blow up the part. Maintaining
the configuration software is also a nuisance.

In the 4000E series, Xilinx made the LUTs accessable by including
circuitry to allow their use as RAMs, so it's not necessary to mess
with the bitstream ( at least for the reasons I did ).

An easier approach is to just use the Xilinx back end tools. I don't
know how the folks in the reconfigurable computing business are
handling the issue. Either they've developed their own tools, or licensed
the Xilinx stuff for re-distribution as part of their environment.


-- 
John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
Univision Technologies, Inc. | those who are once-and-a-half witted
6 Fortune Dr.                | with the half-witted, because we
Billerica, MA 01821-3917     | appreciate only a third part of their wit.
jsmith@univision.com         | - Henry David Thoreau
Article: 5133
Subject: ANNOUNCEMENT: New Web Site Dedicated to Programmable Logic
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 25 Jan 1997 20:29:07 GMT
Links: << >>  << T >>  << A >>
There is a new site for designers interested in programmable logic.  The
Programmable Logic Jump Station provides quick and easy access to 

* all major FPGA, CPLD, and PLD device manufacturers
* most EDA companies that support programmable logic design
* books on programmable logic
* university and industry research groups studying programmable logic and
its
  applications
* search engines and links to other sources of information on programmable
logic
* design consultants for programmable logic applications
* conferences and trade shows about programmable logic

Programmable Logic Jump Station: 
http://www.netcom.com/~optmagic/index.html

The Programmable Logic Jump Station was recently named an 'Outstanding
Site' by the PC Webopaedia.


Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic
Article: 5134
Subject: Re: Altera support better than Xilinx
From: "Austin Franklin" <#darkroom@ix.netcom.com#>
Date: 25 Jan 1997 21:26:30 GMT
Links: << >>  << T >>  << A >>
Steve,

> More of a problem were the problems with the
> Viewlogic software bundled with the Xilinx tools. This was obviously
> well behind what Viewlogic were shipping to 'real' customers, with no
clear path for tech support. 

That's odd.  I have been using the Viewlogic/Xilinx tools for years.  For 6
years, Viewlogic has always been the most supported Xilinx front end (for
schematic capture that is), and I have had some problems years ago. But
not today, or for at least the past three years.  What kind of problems
were you having?

Austin Franklin
darkroom@ix.netcom.com

Article: 5135
Subject: Re: Verilog --> FPGA
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 26 Jan 1997 00:40:54 GMT
Links: << >>  << T >>  << A >>
I can suggest a few packages that allow direct Verilog synthesis into
FPGAs.

Exemplar Logic:  http://www.exemplar.com/logicexplorer.phtml

Synopsys FPGA Compiler:  http://www.synopsys.com/products/fpga/fpga.html

Synopsys FPGA Express (Windows-based): 
http://www.synopsys.com/products/fpga_pc/fpga_pc.html

Compass:  http://www.compass-da.com/prodinfo/prodline/des_entr/p_fpga.html

There may be others.  You can find more information in the Synthesis
section of the Programmable Logic Jump Station at

http://www.netcom.com/~optmagic/index.html#Synthesis

-- 
Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Vass Francesco <fpvass@stud.ee.ethz.ch> wrote in article
<32E692AD.6422@stud.ee.ethz.ch>...
> I wrote a quite long verilog specification for an FPGA.
[snip]
> Does a package exist with which I can directly synthetise the FPGA,
> without before translating the verilog specification to vhdl?
[snip]
> Francesco Vass 
> Institute for Biomedical Engineering,
> Swiss Federal Institute of Technology

Article: 5136
Subject: Memory Models for VHDL/Verilog
From: suzanne@world.std.com (suzanne M southworth)
Date: Sun, 26 Jan 1997 17:20:02 GMT
Links: << >>  << T >>  << A >>
Memory modeler is an innovative tool that solves your memory modeling
challenges. Memory Modeler creates models for all of the memories in
your design, delivery fast, accurate, and complete VHDL and Verilog
models. Memory Modeler supports all of the popular VHDL and Verilog
simulators.

You create your own models using our unique parameterizable memory
classes.

The models contain all the functionality of the actual parts and have
complete timing and refresh checks. These models are unparalleled in
speed and capacity.

Memory Modeler uses start-of-the-art client-server technology to give you
graphical debugging tools.

Memory Modeler contains a powerful library of functions to assist in 
regression testing your design.

Memory elements present unique challenges for simulation debuggers. Verilog
and VHDL environments focus on source level debugging and waveforms,
which are unwieldy for large components, like memories. The simulation
and analysis features of Memory Modeler enable you to debug your design
interactively or in batch regressions.

Interactive Graphical Debugger:
Our graphical debugger extends your simulation environment. You invoke
the debugger at any time during your simulation run, and can detach
it at any time. With the debugger you can: view all the memory contents;
edit memory contents;display and save memory access history; and load 
memory contents from a file.

It offers test bench support---

To find out more information; please send an e-mail to: 
suzanne@world.std.com, and provide your phone# and company name, and
we will fax you a more detailed brochure.

Thanks,

Suzanne Southworth
508-851-5515
Article: 5137
Subject: Re: Processorless FPGA computer help
From: Peter Alfke <peter@xilinx.com>
Date: Sun, 26 Jan 1997 14:14:32 -0700
Links: << >>  << T >>  << A >>
Let me clarify one point:
Xilinx does not release information that decodes the complete bitstream,
but we gladly supply the information that pinpoints the content of the
LUTs. All we need is a written request with a convincing explanation of
why you really need it. Then you have to sign a non-disclosure
agreement, and we send you the information. That's the official policy.
( I personally think that any information that can be hacked in a
weekend should be made public, but that's just my personal bias. ) 
Xilinx wants to give all its users the confidence that, while the
bitstream might be intercepted, it is virtually impossible to reverse
engineer the design from it. That's why we are so formal, even regarding
the trivial subset of that information, the LUTs. Believe it or not, we
really are only concerned about the trust and confidence  of our
customers, not about any new start-up analyzing our architecture and
copying us. It's far too late to do that successfully.

Peter Alfke, Xilinx Applications
Article: 5138
Subject: Re: FPGA Lab.
From: John Rible <jrible@quicksand.com>
Date: Sun, 26 Jan 1997 21:39:07 GMT
Links: << >>  << T >>  << A >>
Ahmad Alsolaim wrote:

> included in the proposal.  we are going to use PC Pentium200 station and
> Viewlogic's Workview Office.

I've been using QuickLogic's development system on PC's. It includes
Data I/O's Synario for scematic capture, Silos III for Verilog
simulation, and Symplicity for both Verilog and VHDL synthesis. Pretty
neat package, and they (QuickLogic) support Universities pretty well.
Only drawback is that their (very fast, very dense, VERY routable) FPGAs
are OTP, so need sockets on boards. 
-- 
jrible@quicksand.com   "hardware, software and so forth..."
Article: 5139
Subject: Re: Altera support better than Xilinx
From: zx80@dgiserve.com (Peter)
Date: Sun, 26 Jan 1997 21:48:29 GMT
Links: << >>  << T >>  << A >>

Perhaps you are using the DOS versions of Viewlogic. I too find them
bug-free. The major irritant is the need to maintain a
PC-Mouse-compatible mouse on a serial port!

I think the problems started with the ProView stuff, now dropped by
Viewlogic but still sold by Xilinx AFAIK.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5140
Subject: Re: FPGA Lab. KIT
From: Richard Schwarz <AAPS@EROLS.COM>
Date: Sun, 26 Jan 1997 17:19:45 -0500
Links: << >>  << T >>  << A >>
An excellent choice for FPGA LAB KITS is the APS-X84 series. They use 
industry leading XILINX FPGAs and are priced very reasonablly. They can 
be seen at:

http://www.erols.com/aps
Article: 5141
Subject: Re: Safety Critical Apps -> Xilinx Checker.
From: bny@crl.com (Bradley Yearwood)
Date: 26 Jan 1997 14:21:01 -0800
Links: << >>  << T >>  << A >>
In article <01bc03d8$f3660520$6e0db780@Rich>,
Rich K. <rich.katz@gsfc.nasa.gov> wrote:
>well the xilinx guys just left the office and the amount of damage done
>internally by an illegal configuration they didn't know but i'll be
>following up at the factory with the contact number they left.  a key
>element would be worst-case current densities so there is no metal
>migration problems.  the standard for this is about 2E5 a/cm^2, if memory
>is correct, which is not as big as it looks when you compute the
>cross-sectional area of small metal lines.

I don't know what the maximum extent of damage is for, say, a single bit
flipped in an operating Xilinx device, but I have recently toasted several
5210 devices by selecting a wrong PROM programmer option in programming
the serial EEPROM containing the configuration data.  The 5210s were
permanently damaged.  If I recall correctly, they got quite hot in the
process.  I believe that the option that I mis-selected was the reset polarity.
Article: 5142
Subject: Re: Altera PCI experience anyone?
From: Dean Brown <deankb@popd.ix.netcom.com>
Date: Sun, 26 Jan 1997 20:02:29 -0500
Links: << >>  << T >>  << A >>
Scott D. Davilla wrote:
> 
> In article <32E7C653.3D49@ids.net>, Ray Andraka <randraka@ids.net> wrote:
> > Has any one used Altera's PCI development kit?  If so, I'd like to hear
> > about your experience and opinions.  Specifically, does the Altera kit
> > provide a turn-key PCI interface, or is there alot of development work
> > to make it play?
> 
>    If you're looking to take the free PCI dev kit and turn a quick PCI
> design, forget it. While the design looks ok and will work to understand
> how to do a PCI logic design, there are several holes in the logic states
> that you could drive a truck through.  Be prepared to spend a few weeks or
> months fixing the bugs.  Several of the bugs will not show up until you try
> platforms like dec Alpha. Surprisingly, the really big holes did not show
> up on Macintosh PCI platforms (where the design first came up). Only when
> we crossed checked various Intel platforms did the bottom fall out.
>    That's what we did (simple target, no master). I plan to re-write the
> whole thing from scratch later now that I understand it better.  One
> problem was with IDSEL and configuration cycles. PCI spec (and I missed it
> too first time around) says that IDSEL is only valid during a config cycle.
> IDSEL is not defined for other cycles. The Altera logic design depended on
> the state of IDSEL during other cycles. Sure enough Macintosh PCI always
> left IDSEL deasserted on non-config cycles. On the other platforms, someone
> seems to didling with it on non-config cycles.  Whamm, put card in, no
> boot.

On most systems the IDSEL signal is connected through a 27ohm resistor
to one of the ADXX lines. This means that normal access cycles will
modify the IDSEL line no matter what cycle type is occuring.

>    If I had to do it today, I would pick one of the PCI interface chips
> from PXL or V3. They have matured to a stable point now. When we did the
> design, too many bugs.
>    Also logic analyser is a must for debuging.
> 
> ---------------------------------------------------------------------
> Scott D. Davilla                            Phone: 919 489-1757 (tel)
> 4pi Analysis, Inc.                          Fax:   919 489-1487 (fax)
> 3500 Westgate Drive, Suite 403              email: davilla@4pi.com
> Durham, North Carolina  27707-2534          web:   http://www.4pi.com

-- 
Dean Brown
DKB
Article: 5143
Subject: XACT's fitting speed
From: cong_sp@tky0.attnet.or.jp
Date: Mon, 27 Jan 1997 15:53:54 +0900
Links: << >>  << T >>  << A >>
Hi , all

I'm using Xilinx's XACT . I found it too slowly when fitting . If anyone know
how to let it be faster , please tell me .
Article: 5144
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: gillies@cs.ubc.ca (Donald Gillies)
Date: 27 Jan 1997 01:09:30 -0800
Links: << >>  << T >>  << A >>
ees1ht@ee.surrey.ac.uk (Hans Tiggeler) writes:

>Given the price of S/DRAM memories why not use a majority voting
>system such as TMR (Triple Modular Redundancy). The system can handle
>multiple bit upsets and is very easy to implement. I have currently a
>system running in an Actel1020 (17% used!). Of course the drawback is
>that you have to either triplicate your memory or add a statemachine
>to perform three memory read cycles per CPU read cycle.

>Hans
>Surrey Satellite Technology.

I would suspect that the answer is: power.  Very few spacecraft have
power to burn on triplicated anything, if it can be avoided.


Don Gillies -  gillie_d@motsat.sat.mot.com - Technical Sciences
Inc. (consultants) / Motorola Satellite Division / Iridium Project
2501 S. Price Road, Chandler, Arizona 82548 - phone: 602-732-3077
Adjunct Professor of EE, UBC, Vancouver BC Canada V6T 1Z4
http://www.ee.ubc.ca/home/staff/faculty/gillies/etc/www/index.html
Article: 5145
Subject: Fuzzy Controller in FPGA.
From: "Robert Zajac" <z_robert@mars.aldec.katowice.pl>
Date: 27 Jan 1997 09:27:03 GMT
Links: << >>  << T >>  << A >>
Does anybody have information where can I get something about FPGA and
Fuzzy Controllers.
I am interested in new defuzzification methods and membership functions
storage algorithms.
I am specially concerned about arithmetic algorithms and their
implementation.
Target device is the X40xx.
This is the topic of my thesis, so do answer !

Robert Zajac
Silesian Technical University 
Poland
Article: 5146
Subject: Re: Designing Xilinx with cadence
From: koch@eis.cs.tu-bs.de (Andreas Koch)
Date: Mon, 27 Jan 1997 13:11:50 GMT
Links: << >>  << T >>  << A >>
In article <32E8E779.F37@shef.ac.uk>, J.Mawer <j.mawer@shef.ac.uk> wrote:
>Hi 
>I have cadence 9502 and Xact 5.2.0.  If I follow the design flow for
>xilinx in cadence then I can not simulate with back annotated delays. 
>The
>reason appears to be that Xact produces XNF version 6 while cadence can
>only handle upto version 5.  Is there a way I can force Xact to write
>out an older version of XNF? Alternativley if there is a way to convert
>version 6 to version 5 then I might be able to fool cadence
>
>Thanks in advance for your help
>
>John

Try these quick & dirty hacks, they seem to work for us:

1) In ~dfwii/tools/pic/picdesigner/bin, move xcdsprep to xcdsprep.orig
and install the following script with permission 0755 (modify the path
to 9502 as appropriate for your installation):

#!/bin/csh -f
#
# AHK961015
#
# resets LCANET number from 6 to 5 to allow ancient Cadence utilities
# to process newer .XNF files

sed 's/LCANET, 6/LCANET, 5/' <$1 >${1}.lcanet5

/usrf/9502/tools/pic/picdesigner/bin/xcdsprep.orig ${1}.lcanet5 ${2} $3 \
        $4 $5 $6 $7 $8 $9

#sed 's/LCANET, 5/LCANET, 6/' <${2}.lcanet5 >${2}
rm ${1}.lcanet5 



2) Do a similar procedure for xnf2cds.exe: move xnf2cds.exe to
xnf2cds.exe.orig, install the following as xnf2cds.exe with 0755:

#!/bin/csh -f
#
# AHK961203
#
# resets LCANET number from 6 to 5 to allow ancient Cadence utilities
# to process newer .XNF files

@ argc = $#argv
@ drawingi = $argc 
@ fnamei = $drawingi - 1
set drawing = $argv[${drawingi}]
set fname = $argv[${fnamei}]

set argv[${fnamei}] = ${fname}.lcanet5

sed 's/LCANET, 6/LCANET, 5/' <${fname} >${fname}.lcanet5

/usrf/9502/tools/pic/picdesigner/bin/xnf2cds.exe.orig $*

#sed 's/LCANET, 5/LCANET, 6/' <${2}.lcanet5 >${2}
rm ${fname}.lcanet5 



It might be necessary to apply a similar modification to xnf2cds (you can
modify the script directly). We have such a patch, but I think it
wasn't really necessary.

At least these modifications were easier than the custom netlisters
and libraries I had to write for 9301 and 9401 ...

Good luck & excuse the CSH style ...,
	Andreas Koch

PS:  The unpatched 9502 netlister doesn't export TIMEGRP symbols
correctly.  That seems to be due to a typo:  they export TIMEGROUP
symbols correctly.  However, these are worthless, since XACT expects
TIMEGRP.  Cadence has a patch for this on their FTP site ( accessible
even to otherwise neglected EUROPRACTICE members).
-- 
Andreas Koch                                  Email  : koch@eis.cs.tu-bs.de
Technische Universit"at Braunschweig          Phone  : x49-531-391-2384
Abteilung Entwurf integrierter Schaltungen    Phax   : x49-531-391-5840
Gaussstr. 11, D-38106 Braunschweig, Germany   * PGP key available on request *
Article: 5147
Subject: Re: Altera PCI experience anyone?
From: rminnich@sarnoff.com (Ron G. Minnich)
Date: 27 Jan 1997 15:48:10 GMT
Links: << >>  << T >>  << A >>
William Vollrath (williamv@pacbell.net) wrote:
: We have been looking into PCI on Altera a little bit.  They can supply 
: you with a free minimal core that would require develpoment from you, or 
: hook you up with 3rd party vendors that have synthesized PCI into Altera 
: already and can sell it complete to you.  The altera web page, 
: http://www.altera.com has got info on this.


Do the Altera interfaces now do PCI Master mode? they did not a year ago. 
In fact they were not enough of a pci interface to be that useful -- we had to 
do our own. 

This may have changed, though. 

ron
--
Ron Minnich                |"Failure is not an option" -- Gene Kranz
rminnich@sarnoff.com       | -- except, of course, on Microsoft products
(609)-734-3120             |
ftp://ftp.sarnoff.com/pub/mnfs/www/docs/cluster.html 

Article: 5148
Subject: Re: FPGA & division
From: Jose Paredes <jparedes@vnet.ibm.com>
Date: Mon, 27 Jan 1997 10:46:41 -0600
Links: << >>  << T >>  << A >>
There's a neat way I seem to remember that didn't use multiplication,
but sort of imbedded the multiplication in a bunch of shift-adds (okay
well, that's what mutiplication is anyway..). You can make it pretty
fast by using a sort of modified CLA scheme. I have to look it up if you
like. You set up a Divide Array, similar to a Multiply array and it
performs pretty good. Wow, it's been a long time since I've seen that
stuff, now I really want to look it up... :) Anyway, let me know if you
would like the algorith/hardware layout.

Jose
Article: 5149
Subject: Re: ABEL->AHDL
From: Benjamin D Klass <bdk+@andrew.cmu.edu>
Date: Mon, 27 Jan 1997 13:15:55 -0500
Links: << >>  << T >>  << A >>
Synario, by Data I/O will compile ABEL files for Altera devices. 
Basically, it translates the ABEL into a gate level netlist in AHDL. 
I've used it a few times, and it works pretty well.

The Altera fitter Data I/O sells (they might call it a place and router
tool) is the compiler portion of Altera's Maxplus2.  If you already have
Maxplus2, you don't need the fitter.  If you don't, it might be a good
deal.

ben



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