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Messages from 5300

Article: 5300
Subject: Re: Robust Applications with FPGAs
From: Scott Kroeger <Scott.Kroeger@mail.mei.com>
Date: Wed, 05 Feb 1997 09:44:22 -0600
Links: << >>  << T >>  << A >>
sundberg jeffrey r wrote:

> need to imprelement a cruise control/engine...
>... what is the best target device platform to implement the design on

Hello Jeff,

The auto industry has been doing that job in little single chip
microcontrollers for many years.  Their environment is far harsher than
yours.  The Microchip PIC and National COP-8 family of processors and
tools are available from DigiKey.  Motorola's 68HC05 family and the
various flavors of 8051 from many manufacturers may also be suitable.

If your needs are more sophisticated, I'd check your local Hitachi rep
to see if they still have their $99 SH-1 evaluation board.  This gives
you a very capable RISC microcontroller with 128KBytes of external RAM
and some external EPROM, complete with GNU development toolchain, for
$99.

Regards,
Scott
Article: 5301
Subject: Embedded SRAM in FPGAs
From: Jason.Wright@ebu.ericsson.com (Jason T. Wright)
Date: Wed, 05 Feb 1997 18:31:43 GMT
Links: << >>  << T >>  << A >>
I'm looking at Lucent ORCA2 series & Xilinx 4000E series parts; I also
looked at Flex10k from Altera.  For a previous design I selected a
F10k50 because the memory requirements fit nicely (number of EABs
available, distribution of memory, etc.)

Unfortunately (?), even though this design requires a lot less memory,
it is split up into several small chunks which may (statistically
speaking) need to be accessed concurrently.  The total size is
estimated at about 700 - 800 bytes, which by my calculations should
easily fit in an ORCA2C10A or better, or a Xilinx 4010E or better.  Of
course, how much extra logic is required (5k? 10k? 15k gates?) may
push for a larger part.

I have experience with the X4010, using older DOS Viewlogic and Xact 4
& 5, so I have a feel for the process.  I haven't used ORCA except to
do a trial evaluation (for the 20 kbit design), and I found that
design impossible to route inOR2C40A:  but then, the embedded RAM was
about half of the chip.

This design is expected to migrate to an ASIC, so HDLs are desired
(probably VHDL with Synopsys, which both vendors support.)

I'm interested in people's [recent] experiences with these two
products and the development environment.

Thanks,

Jason T. Wright

P.S.  Is it worth (possible) doing a design for the larger parts on
the PC (under NT)?  I recall long place & route times for the 4010 on
a 486 PC, and don't want to go through that again unnecessarily.


Article: 5302
Subject: Duplicate PLD?
From: cwr@cts.com (Will Rose)
Date: 5 Feb 1997 21:13:07 GMT
Links: << >>  << T >>  << A >>
I have a problem with a 16L8 PLD, and I can't find comp...pld,
so I thought I'd try here - if anyone knows a better source, please
say so.

I need to copy a 16L8 to repair some obsolete equipment; I don't
have a programmer, but can lay my hands on one with some difficulty.
What I don't know is if it's possible to directly copy a PLD using
a programmer, or if it's possible to derive the PLD logic and thus
program another PLD from scratch.

Any thoughts welcome.

Will
cwr@crash.cts.com

Article: 5303
Subject: Re: Duplicate PLD?
From: Jason.Wright@ebu.ericsson.com (Jason T. Wright)
Date: Wed, 05 Feb 1997 22:09:09 GMT
Links: << >>  << T >>  << A >>
On 5 Feb 1997 21:13:07 GMT, cwr@cts.com (Will Rose) wrote:

>I have a problem with a 16L8 PLD, and I can't find comp...pld,
>so I thought I'd try here - if anyone knows a better source, please
>say so.
>
>I need to copy a 16L8 to repair some obsolete equipment; I don't
>have a programmer, but can lay my hands on one with some difficulty.
>What I don't know is if it's possible to directly copy a PLD using
>a programmer, or if it's possible to derive the PLD logic and thus
>program another PLD from scratch.

If the two devices have the same jedec file, it's a no-brainer.  Just
copy them (changing family/pinout codes as necessary); however, if the
manufacturer's parts aren't compatible enough (though I expect all
16L8s will be), then it is a more challenging problem (such as 16L8 to
16V8).

Jason T. Wright
>
>Any thoughts welcome.
>
>Will
>cwr@crash.cts.com
>

Article: 5304
Subject: Re: Back annotation under Workview Office/Xilinx...
From: David Dye <davidd@xilinx.com>
Date: Wed, 05 Feb 1997 15:26:15 -0800
Links: << >>  << T >>  << A >>
Nicholas,

Yes it certainly is possible.  Just follow the instructions in this
Solution Record that can be found on our Web site: 
http://www.xilinx.com/techdocs/789.htm
For more solutions, take a look at our Solution Search Engine:
http://www.xilinx.com/support/searchtd.htm

Hope this information helps you out!

-- 
David Dye
Software Applications Engineer
Xilinx, Inc., San Jose, CA
ph> (800) 255-7778
email> david.dye@xilinx.com


Nicholas C. Weaver wrote:
> 
>         We have Workview office and the XACT tools, but unfortunately
> I don't have the documentation handy.  Is it possible to do back
> annotation from a placed & routed Xilinx design so that the workview
> simulator (speedwave) gives correct timing information?  And how is
> this done?
> 
> --
>    Nicholas C. Weaver             Ash C++ durbatuluk, ash C++ gimbatul,
> nweaver@cs.berkeley.edu       ash C++ thrakatuluk agh burzum-ishi krimpatul!
>                  http://www.cs.berkeley.edu/~nweaver/
> It is a tale, told by an idiot, full of sound and fury, .signifying nothing.
Article: 5305
Subject: Re: DES Challenge
From: Michael Koch <mkoch@earthlink.net>
Date: Wed, 05 Feb 1997 22:31:38 -0500
Links: << >>  << T >>  << A >>
Wasn't there a proposal years ago which used memory/CPU hybrid chips to
break DES [exhaustive search] within a day for around $100k? But the
machine was scalable. Wonder what happened to that...

 MIKE...

Steve Casselman wrote:
> 
> The guy who broke the 40-bit code made the LA times.
> It took 250 workstations 3 1/2 hours. If he had to search
> to the last combination it would have taken 10 hr. I
> figured that a 50MHz engine would have taken 6 hrs.
> The 48-bit key search (which is next) should take
> 256 times longer.
> 
> Steve Casselman
Article: 5306
Subject: Re: Embedded SRAM in FPGAs
From: kenk@teleport.com (Ken Krolikoski)
Date: Thu, 06 Feb 1997 05:46:45 GMT
Links: << >>  << T >>  << A >>
On Wed, 05 Feb 1997 18:31:43 GMT, Jason.Wright@ebu.ericsson.com (Jason
T. Wright) wrote:

>I'm looking at Lucent ORCA2 series & Xilinx 4000E series parts; I also
>looked at Flex10k from Altera.  For a previous design I selected a
>F10k50 because the memory requirements fit nicely (number of EABs
>available, distribution of memory, etc.)
>
>Unfortunately (?), even though this design requires a lot less memory,
>it is split up into several small chunks which may (statistically
>speaking) need to be accessed concurrently.  The total size is
>estimated at about 700 - 800 bytes, which by my calculations should
>easily fit in an ORCA2C10A or better, or a Xilinx 4010E or better.  Of
>course, how much extra logic is required (5k? 10k? 15k gates?) may
>push for a larger part.
>
>I have experience with the X4010, using older DOS Viewlogic and Xact 4
>& 5, so I have a feel for the process.  I haven't used ORCA except to
>do a trial evaluation (for the 20 kbit design), and I found that
>design impossible to route inOR2C40A:  but then, the embedded RAM was
>about half of the chip.
>
>This design is expected to migrate to an ASIC, so HDLs are desired
>(probably VHDL with Synopsys, which both vendors support.)
>
>I'm interested in people's [recent] experiences with these two
>products and the development environment.
>
>Thanks,
>
>Jason T. Wright
>
>P.S.  Is it worth (possible) doing a design for the larger parts on
>the PC (under NT)?  I recall long place & route times for the 4010 on
>a 486 PC, and don't want to go through that again unnecessarily.
>
>
Most of Lucents sales comes from captive AT&T accounts. ORCA is not a
major player in the general marketplace. 

Xilinx offers a version of their foundation sw package which offers
vhdl abel or schematic entry.

The new routing sw that xilinx is releasing now for workstations and
in april for windows NT will significantly improve your route times.
the new 4Kex and 4kxl devices have double the routing resources of the
4ke.

the next three parts available from xilinx will be the 4062(now),
4085(2q97) and 40125(3q97). I found the press release on their web
site. (www.xilinx.com)

Mike Seither 
Xilinx, Inc. 
(408) 879-6557 
mike.seither@xilinx.com

FOR IMMEDIATE RELEASE

                          XILINX ROADMAP FOR HIGH DENSITY FPGAS 

                         CALLS FOR 0.25 MICRON DEVICES DURING 1997

SAN JOSE, Calif., February 3, 1997--Xilinx, Inc., (NASDAQ:XLNX) today
unveiled a product roadmap that points to
delivery this year of high density field programmable gate array
(FPGA) devices manufactured using advanced deep submicron
process technologies. 

In January Xilinx began shipping samples of the company's first FPGA
devices using 0.35 micron process technology: the
XC4062XL, XC4036XL and XC4013XL parts. During the second quarter of
1997 Xilinx expects to have a family of
three-layer metal 0.35 micron devices. The 10-member XC4000XL family
will comprise devices ranging in density from 5,000
to 85,000 gates, all operating at 3.3 volts with 5-volt tolerant I/Os.


In a statement of direction, the company also said its expects to ship
this year products that will be manufactured with more
advanced five-layer metal 0.25 micron technology. Samples are expected
during the summer of 1997 of a 0.25 micron FPGA
device offering 36,000 logic gates, with a 125,000-gate device to
follow shortly thereafter. The devices will operate at 2.5
volts at the core voltage level, while the I/Os will operate at 3.3
volts and 2.5 volts, and tolerate 5-volt signals. 

If technical advancements with CMOS process technology continue at
their current pace, the company said it could be
possible to manufacture FPGA devices with two million gates by the
year 2001. 

Xilinx released a white paper, "The Future of FPGAs," in conjunction
with the company's statement of direction for high density
programmable logic products. Among other topics, the white paper
provides an analysis of the coming voltage migration that
will confront digital designers. For more than 20 years, the white
paper points out, 5 volts has been the standard supply voltage
for most electronic components, including FPGAs. Design engineers
could expect predictable gains in price and performance
without having to change designs to accommodate smaller and faster
versions of an FPGA as the devices were manufactured
with successively finer processes, moving from 3.0 micron to 2.0
micron, then 0.8, 0.6 and finally 0.5 micron. But future
generations of FPGAs, and all other semiconductors manufactured with
0.35, 0.25 and 0.18 micron processes, will require
incremental moves to lower voltages. This will force the issue of
ever-changing supply voltages into customers' design and
product life cycle assumptions. 

Xilinx said that its product strategy calls for devices that will have
voltage compatibility with the previous two generations of
products. The new 3.3-volt Xilinx XC4000XL products which are now
sampling, and the 2.5-volt products slated for
shipment later this year, can co-exist in 5-volt environments. 

Going forward, Xilinx plans to set forth a new methodology, also
detailed in the white paper, for measuring the logic density of
FPGAs. The new density metric is based on logic cells that typically
consist of a 4-input look-up table and one flip flop. The
company said this method will make it possible for customers to make
meaningful comparisons of competing products. The
goal is to end the confusion caused by programmable logic vendors who
include on-chip RAM to arrive at inflated gate
densities. 

Xilinx said the new XC4062XL device, when measured using logic cells,
is currently the industry's largest FPGA device. The
Xilinx XC4085XL device, the flagship product in the company's new
3.3-volt family planned for shipment this summer, is
expected to offer 40 percent more density than the XC4062XL device,
while the denser 2.5-volt device scheduled for
sampling later this year has been designed to offer twice as much
density as the XC4062XL device. 

In addition, Xilinx said its HardWire program will support the
company's new, higher density devices for customers who
require a migration path to a mask programmable solution in order to
achieve the lowest possible cost. The Xilinx roadmap
includes fully compatible 3.3-volt HardWire devices in 1997 and
2.5-volt HardWire devices in 1998. HardWire devices are
guaranteed to be fully logic- and pin-compatible with their FPGA
counterparts at ASIC-like prices, and they eliminate the need
for customers to write test vectors or perform timing simulations as
part of the conversion process. 

Xilinx also plans to announce the general availability of a new
software platform that supports very high density designs and
features ASIC-like design flows and hooks to synthesis. The software,
now in the hands of selected users, is scheduled for
general availability later in 1997. 


Article: 5307
Subject: Re: Q is Xilinx Foundation BASE worth buying?
From: kenk@teleport.com (Ken Krolikoski)
Date: Thu, 06 Feb 1997 05:51:17 GMT
Links: << >>  << T >>  << A >>
On 3 Feb 1997 09:09:40 GMT, pac1@waikato.ac.nz (pac1) wrote:

>I'm trying to decide if it is worth buying Xilinx Foundation BASE as
>oppose to the standard XACT Step package (because its much cheaper).
>
>Can anyone tell me if it is any good, what are its limitations - I've
>looked on Xilinx home page and can't find a good description of what it
>can or can't do!
>
>Thanks Peter.
Peter,
There is also a foundation eval kit available. Call one of the xilinx
distributors, hamilton hallmark, insight or marshall. the limitation
is up to 5000 gates on the base package plus only 3 months support vs
a year for the standard. The base also includes for now an unlimited
site license except for abel. It's a great package for $600.
Article: 5308
Subject: Re: [Q] Xilinx FPGA Resources
From: kenk@teleport.com (Ken Krolikoski)
Date: Thu, 06 Feb 1997 05:59:17 GMT
Links: << >>  << T >>  << A >>
On Sat, 18 Jan 1997 19:01:36 -0500, David Charles Hirschfield
<dch+@andrew.cmu.edu> wrote:

>I'm currently working on a project that requires continuous programming
>and reprogramming of a Xilinx XC4000 FPGA board.
>
>Due to some strange setup requirements, we are not going to be able to
>directly use the xchecker application and cable to program the board.
>
>Does anyone have any information regarding the technical details of
>programming Xilinx boards?
>
>Any help would be greatly appreciated,
>-David Hirschfield
>
>+-===========================================================================-+
>|                                                --== e-mail ==--             |
>|     _/_/_/      _/_/    _/   _/  _/_/_/      dch+@andrew.cmu.edu            |
>|    _/    _/  _/    _/  _/  _/   _/                   or                     |
>|   _/    _/  _/_/_/_/  _/ _/    _/_/       cddch@paleo.giss.nasa.gov         |
>|  _/    _/  _/    _/  _/_/     _/                                            |
>| _/_/_/    _/    _/  _/       _/_/_/             --== WWW ==--               |
>|                                     http://www.contrib.andrew.cmu.edu/~dch/ |
>+-===========================================================================-+
> 
try the www.xilinx.com. You can e-mail a question to them from the web
page.
Article: 5309
Subject: PMC alternative
From: "Jae-Ho Shin" <jhshin@mjl.co.kr>
Date: 6 Feb 1997 06:53:40 GMT
Links: << >>  << T >>  << A >>
Hi,
I am looking for PMC ATM PHY products' alternatives, specially for 155M and
622M.
Is anyone who knows this?

Article: 5310
Subject: PMC alternative
From: "Jae-Ho Shin" <jhshin@mjl.co.kr>
Date: 6 Feb 1997 07:02:18 GMT
Links: << >>  << T >>  << A >>
Hi,
I am looking for PMC ATM PHY products' alternatives, specially for 155M and
622M.
Is anyone who knows this?

Article: 5311
Subject: BIGGER (was Embedded SRAM in FPGAs)
From: eteam@aracnet.com (bob elkind)
Date: Thu, 6 Feb 1997 09:06:59 -0000
Links: << >>  << T >>  << A >>
In article <32f96df6.89153336@news.teleport.com>, kenk@teleport.com says...

> Most of Lucents sales comes from captive AT&T accounts. ORCA is not a
> major player in the general marketplace. 

Agreed that most of Lucent's FPGAs are sold into direct (big)
accounts.  Their pricing and distribution scheme "drove" them
to this condition.  However, in the last year Lucent has
taken steps to broaden distribution of their parts, and
attract more of the "little fish".  Most of this effort is
in the form of part pricing to end users and distributors.
I don't see any reason why Lucent is any less of an FPGA
vendor than Xilinx or Altera, for any size project or
company.

On the subject of "whose xxx is bigger":  If you're going
to use *lots* of gates (list of huge Xilinx FPGAs deleted),
and use them at a high enough bandwidth, then power can become
a limiting factor before you are bound by gates, routing
channels, etc.  Last time I looked, the Lucent 2cA series
had a speed/power advantage of X 4KE, but that may have
changed.  Both the L and the X company have made much-needed
improvements in the thermal characteristics of their packages,
but last time I looked the Lucent 2C40 with its cavity-down
packaging had a definite advantage in the field.

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5312
Subject: Re: DES Challenge
From: kilgallen@eisner.decus.org (Larry Kilgallen)
Date: Thu, 6 Feb 1997 11:52:55 GMT
Links: << >>  << T >>  << A >>
The published work has all been theoretical study (including pricing
of the required hardware fabrication).

The only entities interested in public construction of such a machine
would be non-profit political groups such as the Electronic Privacy
Information Center, and theoretical studies serve their purpose just
as well.

Those with a _real_ use for exhaustive search are served only if
the fact that they have such capability is kept private.  Do not
expect to read about success on Usenet.

Larry Kilgallen

In article <32F9509A.4C2F@earthlink.net>, Michael Koch <mkoch@earthlink.net> writes:
> Wasn't there a proposal years ago which used memory/CPU hybrid chips to
> break DES [exhaustive search] within a day for around $100k? But the
> machine was scalable. Wonder what happened to that...
> 
>  MIKE...
> 
> Steve Casselman wrote:
>> 
>> The guy who broke the 40-bit code made the LA times.
>> It took 250 workstations 3 1/2 hours. If he had to search
>> to the last combination it would have taken 10 hr. I
>> figured that a 50MHz engine would have taken 6 hrs.
>> The 48-bit key search (which is next) should take
>> 256 times longer.
>> 
>> Steve Casselman
Article: 5313
Subject: Problems with SYNOPSYS - XILINX Interface
From: e9125884@stud1.tuwien.ac.at (Gerhard Wiesinger)
Date: 6 Feb 1997 14:28:14 GMT
Links: << >>  << T >>  << A >>
I have troubles using the XILINX Synopsys Interface.

After doing the "compile -map_effort med" the following error 
occours:


  Loading target library 'xprim_4005-5'
  Loading target library 'xprim_4000-5'
  Loading target library 'xgen_4000'
  Loading target library 'xio_4000-5'
  Loading target library 'xfpga_4000-5'
  Loading design 'pld1'
Information: Design 'pld1' has no optimization constraints set. 
(OPT-108)

  Beginning FPGA optimization
  ---------------------------

  Beginning Resource Allocation  (area only)
  -----------------------------
  Allocating blocks in 'pld1'
  Allocating blocks in 'pld1'
Error: The entity 'inc_dec_ub' depends on the package 
'std_logic_arith'
        which has been analyzed more recently.
        Please re-analyze the source file for 'inc_dec_ub' and try 
again. (LBR-2
8)
Information: Compile terminated abnormally. (OPT-100)
Current design is 'pld1'.
0


Source files are:

-------------------------- file pld1_ent.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED."+";

entity pld1 is
  port(
       MAINCLK:in STD_LOGIC;
       RESET:in STD_LOGIC;
       D: inout STD_LOGIC_VECTOR(7 DOWNTO 0)
      );
end pld1;

------------------------- file pld1_arc.vhd

architecture A_PLD1 of pld1 is

begin
  P1:
  process(MAINCLK,RESET)
  begin
    if RESET='1' then
      D <= "00000000";
    else
      if MAINCLK'EVENT and MAINCLK='1' then
        D <= D + "00000001";
      end if;
    end if;
  end process;

end A_PLD1;

----------------------------

Any hints?
Has anyone has had the same troubles and solved the problem?

If you need the scripts and the setup files please tell me.

Ciao,
Gerhard
Article: 5314
Subject: Re: Suggestions how wire wrap mount a Xilinx PG223
From: eteam@aracnet.com (bob elkind)
Date: Thu, 6 Feb 1997 14:44:23 -0000
Links: << >>  << T >>  << A >>
In article <fliptronE4xrqG.n0@netcom.com>, fliptron@netcom.com says...
> I am currently using products from Aries, for both the WW socket and a 
> ZIF that plugs into it.

Aries is on the web at http://www.arieselec.com/

> For the WW socket, their partnumber would be (I think) 224-PGM-18-18005-20
> or -21 or -30 or -31. -2x is two level wrap, -3x is three level wrap.
> -x0 is Gold collet, tin shell, -x1 is Gold collet, gold shell.
> 
> You can order these products through CalSwitch 1-800-225-7924
...
> A suitable ZIF socket is probably 361-PRS-19-001-1-0 which is a 19 by 19 
> array, and will require some modification to match up the WW socket.
> Check with CalSwitch.
...
> Philip

> In article <32F2441F.3A7E@prism.gatech.edu> Scott McIntosh <gtd750a@prism.gatech.edu> writes:
> >Hello,
> >	I'm using a Xilinx 4013E PG223 chip and currently the rest
> >of the hardware is to be mounted with wire wrap sockets.  Problem
> >so far is I'm unable to find an 18x18,223 wire wrap socket.  Are
> >these just not available?  Any other suggestions?
> >
> >Thanks,
> >	Scott McIntosh
> >	gtd750a@prism.gatech.edu

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5315
Subject: Re: Duplicate PLD?
From: zx80@dgiserve.com (Peter)
Date: Thu, 06 Feb 1997 15:02:52 GMT
Links: << >>  << T >>  << A >>

In theory, you should be able to put the 16L8 into a PLD programmer,
read it (assuming the security fuse is not blown) and then put in a
16V8 and just program it with the same data.

When the 16V8 was originally designed, it was done so it is fuse-map
compatible with the PAL devices.

Mot PC-attached programmers can produce a jedec file from a device.

The same jedec file which programmed the 16L8 should produce a 16V8
which functions identically.

Now, some programmers (e.g. Data I/O Chiplab) are fussy about
accepting jedec files which are shorter (in the # of "fuses") than the
device being programmed, and since the ex-16L8 jedec file will define
fewer fuses than the 16V8 has, you may need to load the jedec file
into a not-so-fussy programmer and re-output it for a 16V8. 

The fact that one 16V8 (e.g. AMD PALCE16V8, no user electronic
signature, so 64 fewer bits) can have fewer fuses than another 16V8
(e.g. Lattice) makes life even more fun...


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5316
Subject: Re: Duplicate PLD?
From: sarfati@netvision.net.il
Date: Thu, 06 Feb 97 08:31:19 PDT
Links: << >>  << T >>  << A >>

Hi,

Normally, any programmer can read a PLD as well as write one. However, PLDs 
have a security fuse, intended exactly to prevent copying them. If the 
security fuse is blown, you can't read the PLD - you get an empty fuse-array.
I suggest you try and hope that  whoever had programmed the original PLD 
wasn't paranoid...

			Regards
			Assaf Sarfati


Article: 5317
Subject: Re: Embedded SRAM in FPGAs
From: coffin@teleport.com (Eric Coffin)
Date: 6 Feb 1997 09:34:09 -0800
Links: << >>  << T >>  << A >>
In article <32f96df6.89153336@news.teleport.com>,
Ken Krolikoski <kenk@teleport.com> wrote:

>Most of Lucents sales comes from captive AT&T accounts. ORCA is not a
>major player in the general marketplace. 

Ken, I assume that you work for Thorson Pacific, a Xilinx sales
representative.  As such perhaps you provide some numbers (market
share) to support your claims.

Eric





-- 
coffin@teleport.COM  Public Access User -- Not affiliated with Teleport
Public Access UNIX and Internet at (503) 220-1016 (2400-28800, N81)
Article: 5318
Subject: Re: Embedded SRAM in FPGAs
From: peter@xilinx.com (Peter Alfke)
Date: Thu, 06 Feb 1997 10:53:59 -0700
Links: << >>  << T >>  << A >>
In article <32f8ce58.179159657@cnn.exu>, Jason.Wright@ebu.ericsson.com
(Jason T. Wright) wrote:


> 
> I have experience with the X4010, using older DOS Viewlogic and Xact 4
> & 5, so I have a feel for the process.  I haven't used ORCA except to
> do a trial evaluation (for the 20 kbit design), and I found that
> design impossible to route inOR2C40A:  but then, the embedded RAM was
> about half of the chip.
> 
> 
Jason, if you have experience with XC4010, you may be interested in the
functional improvements made in the XC4000E family ( and also carried
forward into the XC4000EX and XC4000XL families ).
The 16 x1, or 16 x 2, or 32 x 1 RAMs can now be configured for synchronous
writing by a low-skew Global clock. The signals for address, data-in, and
write-enable only have to meet a set-up time requirement with respect to
that clock.
The CLB can also implement a dual-port memory with synchronous write.

These two features make it much easier to design with, and increase the
performance significantly. Gone are the days of requiring a
double-frequency clock, or implementing a glitch-maker, or worrying about
the necessary overlap of address and data over write enable. Now you can
pretend that the RAM is just a flip-flop or register.
I wrote an app note on using these features to implement fast, efficient
and fully asynchronous FIFOs, which was a pretty tough task with the old
XC4000 structure.
These FIFOs now now run with overlapping asynchronous read and write, up
to 60 MHz on the present silicon, even faster in the upcoming faster
parts. And the control logic keeps track of FULL and EMPTY through some
neat logic tricks.

XC4000EX has additional routing resources and faster clocks. XC4000XL is
the same design, but optimized for 3.3 V. Technology is really moving
ahead, much more rapidly than in the recent past.
Of course I am enthusiastic. I work for the company.

Peter Alfke, Xilinx Applications
Article: 5319
Subject: Re: DES Challenge
From: Aaron Spink <spink@blazin.pa.dec.com>
Date: 06 Feb 1997 19:06:21 +0100
Links: << >>  << T >>  << A >>
Michael Koch <mkoch@earthlink.net> writes:

> 
> Wasn't there a proposal years ago which used memory/CPU hybrid chips to
> break DES [exhaustive search] within a day for around $100k? But the
> machine was scalable. Wonder what happened to that...
> 
I actually know a friend at the Univ. of Michigan who designed a chip for
such a system based off of the proposal.  I forget what he projected the
price for the system to be, but I think it was more than $100k for the
performance you quote.  I'm pretty sure it used roughly 20 stages in
.8um cmos to get to 200mhz per chip.  Pretty cool project for a grad 
level VLSI design class.
Article: 5320
Subject: Re: Reconfigurable Logic Query
From: Brad Hutchings <hutch@ee.byu.edu>
Date: 06 Feb 1997 11:14:17 -0700
Links: << >>  << T >>  << A >>
Ed Vogel <epv@pcsi.cirrus.com> writes:

> 
> Steve Casselman wrote:
>  
>  Well....:) I just read a simular paper where the design was
>  reconfigurable  switches and 2-bit processors. You want to prototype a 
> FPGA in an FPGA. Sounds very feasible for a small device.
> 
> Thanks Steve,
> 	     that sounds like a very reasonable approach. Is this perhaps 
> a BYU "nanoprocessor" paper?

No. :)

-- 
Brad L. Hutchings                                         VOICE: (801) 378-2667
Dept. of Elec. & Computer Eng.                              FAX: (801) 378-6586
459 Clyde Building                                      EMAIL: hutch@ee.byu.edu
Brigham Young University 
Provo, Utah 84602                http://www.ee.byu.edu/faculty/hutch/hutch.html


Article: 5321
Subject: Xilinx Xact Step Software
From: axliu@cecil.EECS.Berkeley.EDU (ALLAN LIU)
Date: 6 Feb 1997 21:10:22 GMT
Links: << >>  << T >>  << A >>
I am using Xilinx's Xact Step software 5.2.  I ran xmake in a dos session and it gives me the error that it can't find the .wir files created by workview office from Viewlogic.  I can see the files and they are in the same directory where I ran xmake.  Any ideas? Email me an suggestions.  Thanks.



-Allan
axliu@cory.eecs.berkeley.edu
Article: 5322
Subject: Re: Xilinx Xact Step Software
From: Jason.Wright@ebu.ericsson.com (Jason T. Wright)
Date: Thu, 06 Feb 1997 21:40:50 GMT
Links: << >>  << T >>  << A >>
On 6 Feb 1997 21:10:22 GMT, axliu@cecil.EECS.Berkeley.EDU (ALLAN LIU)
wrote:

>I am using Xilinx's Xact Step software 5.2.  I ran xmake in a dos session and it gives me the error that it can't find the .wir files created by workview office from Viewlogic.  I can see the files and they are in the same directory where I ran xmake.  Any ideas? Email me an suggestions.  Thanks.
>
>
>
>-Allan
>axliu@cory.eecs.berkeley.edu
My first guess is that you are running xmake from within the .\wir
subdirectory--i.e., they should NOT be in the same directory as you
run xmake.

I believe that their are properties in a file (don't remember which
one) that might point to where the files are; Xilinx tech support will
be able to answer that.

The general tree structure (as I remember it):

home\
	this is where your xnf, abl, etc. files are; you run xmake,
	 ppr, etc., here

home\sch
	this is where Viewlogic stores the schematic files, format
	$name.sheet#

home\wir
	this is where Viewlogic stores the wirelist files; same format
	as for the schematics.

There are backup directories, and I don't remember what all else.

Jason T. Wright
Article: 5323
Subject: Re: Xilinx Xact Step Software
From: Paulo Dutra <paulo@xilinx.com>
Date: Thu, 06 Feb 1997 18:07:48 -0800
Links: << >>  << T >>  << A >>
I'm assuming that some of your files exceed the DOS naming convention
of (8.3).  The Xilinx core tools are still DOS base and therefore are
limited to the 8.3 rule.

ALLAN LIU wrote:
> 
> I am using Xilinx's Xact Step software 5.2.  I ran xmake in a dos session and it gives me the error that it can't find the .wir files created by workview office from Viewlogic.  I can see the files and they are in the same directory where I ran xmake.  Any ideas? Email me an suggestions.  Thanks.
> 
> -Allan
> axliu@cory.eecs.berkeley.edu

-- 
/ 7\'7 Paulo Dutra (paulo@xilinx.com)
\ \ `  Xilinx                              hotline@xilinx.com
/ /    2100 Logic Drive                    (800) 255-7778
\_\/.\ San Jose, California 95124-3450 USA (408) 879-6797
Article: 5324
Subject: Re: DES Challenge
From: Michael Koch <mkoch@earthlink.net>
Date: Thu, 06 Feb 1997 22:28:37 -0500
Links: << >>  << T >>  << A >>
Larry Kilgallen wrote:
> 
> The published work has all been theoretical study (including pricing
> of the required hardware fabrication).
 
Well, that's why I said proposal... 

> Those with a _real_ use for exhaustive search are served only if
> the fact that they have such capability is kept private.  Do not
> expect to read about success on Usenet.

Yup... so the crime/public/covert/military intelligence agencies around
the world would be interested/or have them. I have no data whatsoever
that columbian cocaine dealers encrypt their pick-up schedules w/ DES,
nor if forgein intel/milit. uses DES for anything. Not sure if the fact
that Unix boxes use it is compelling enough to merit multi-million
dollar expenditures.... opps... hold it... we're talking government
here... make that a yes!

 Laters, MIKE...


> 
> Larry Kilgallen
> 
> In article <32F9509A.4C2F@earthlink.net>, Michael Koch <mkoch@earthlink.net> writes:
> > Wasn't there a proposal years ago which used memory/CPU hybrid chips to
> > break DES [exhaustive search] within a day for around $100k? But the
> > machine was scalable. Wonder what happened to that...
> >
> >  MIKE...


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