Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 5400

Article: 5400
Subject: Special issue of TVLSI on FPGA Technology
From: hauck@eecs.nwu.edu (Scott A. Hauck)
Date: Thu, 13 Feb 1997 12:24:02 -0600
Links: << >>  << T >>  << A >>
==================================================================

                        CALL FOR PAPERS

         SPECIAL ISSUE ON RECENT ADVANCES IN FPGA TECHNOLOGY

            IEEE TRANSACTIONS ON  VLSI SYSTEMS


Field-Programmable Gate Arrays (FPGAs) have become  an  important
technology  for  the  implementation of VLSI circuits and systems
due to the steady increase in FPGA density and speed. Aside  from
main-stream  use in reasonably high volume production, the field-
programmability and re-programmability of FPGAs enable many novel
and  promising  applications, including rapid system prototyping,
reconfigurable system designs, rapid system prototyping,  circuit
emulation, and reconfigurable custom computing.  This special is-
sue will be devoted to recent advances in all  areas  related  to
the FPGA technology.

Topics of interest include, but not limited to:

o Advances in FPGA architectures, including design  of  programm-
  able logic blocks, programmable interconnects, programmable I/Os,
  and  development of new FPGAs and field-configurable memories.

o Novel applications of FPGAs, including rapid prototyping, logic
  emulation, reconfigurable custom computing, and dynamically
  reconfigurable applications.

o New CAD algorithms and tools for FPGAs,   including  new  algo-
  rithms for sequential and combinational logic  optimization,
  technology mapping, partitioning, placement, routing, and de-
  velopment of new FPGA synthesis or layout systems.

o Advances in field-programmable technology, including  new  pro-
  cess and fabrication technologies, and  field-programmable
  analog arrays.

Authors of papers accepted for the 1997  ACM/SIGDA  5th  Interna-
tional  Symposium on Field-Programmable Gate Arrays (FPGA'97) are
especially encouraged to submit an extended version of their  pa-
pers for possible inclusion in the special issue.  Submissions of
relevant work not presented at FPGA'97 are  also  welcome.   This
special issue is being coordinated by Guest Editors Jason Cong of
Univ. of California, Los Angeles (UCLA) and Carl Ebeling of Univ.
of Washington.

Prospective authors should submit postscript  versions  of  their
papers electronically using the www no later than March 31, 1997,
and indicate they should be considered for this special issue:

         http://microsys6.engr.utk.edu/~tvlsi

Alternatively, email may be used by contacting:

         tvlsi@microsys6.engr.utk.edu

If neither of the electronic means is available to authors, trad-
itional paper manuscripts should be sent to:

     IEEE Trans. on VLSI Systems
         c/o Prof. Bing Sheu
         Electrical Engineering
         Powell Hall, Room 604
         University of Southern California
         Los Angeles, CA 90089-0271

==================================================================
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of ECE                        Voice: (847) 467-1849                |
|  Northwestern University             FAX: (847) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@ece.nwu.edu             |
|  Evanston, IL  60208                 WWW: http://www.ece.nwu.edu/~hauck   |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
Article: 5401
Subject: Re: [Q].FIFO in FPGA XILINX
From: zx80@dgiserve.com (Peter)
Date: Thu, 13 Feb 1997 19:02:33 GMT
Links: << >>  << T >>  << A >>
Yes, using an external RAM. Far cheaper, too.

>I am currently designing 106 Bytes(848 bits)FIFO in XILINX 4000E.
>Is there any other more efficient way rather than using RAM cell macros?


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5402
Subject: Re: Serial Communication Controller Design
From: zx80@dgiserve.com (Peter)
Date: Thu, 13 Feb 1997 19:03:19 GMT
Links: << >>  << T >>  << A >>

>Doing such designs in schematic is a waste of designer's time. This is
>so much easier accomplished in a HDL.

Some people would differ.

It may be easier for *you* (if you are a VHDL expert) but it sure as
hell is harder for me if I am not a VHDL expert (and one does have to
be quite good at VHDL to avoid getting into a right mess, which means
using it a lot) or if I cannot afford to cough up $Xk for a new Xilinx
FPGA design suite with VHDL capability.

OTOH schematics are always readily translatable into any toolset, now
or in 10 years' time. One just draws the circuit ("schematic capture"
methodology, in the USA :) )

>Why would you want the 16450/16550 with all the overhead (and limited)
>functionality? If you start with my compact UART, then you could easily
>add a FIFO buffer if you need it, and your design will consume very
>little FPGA space.

Why does anyone use a 16550 with its "limited" functionality? The IBM
PC also has a limited functionality, but for some reason seems to be
quite popular nowadays.

Let me tell you: a UART is very rarely useful without a microprocessor
around. The micro needs to be able to set the baud rate. So one had a
baud rate generator. It needs to get interrupts. So one has circuitry
for that. And so on.

I don't see that the 16550 has a particularly "limited" functionality.
They should have provided IRQ capability from *all* the status bits,
but again it would be easy to add that if one had a circuit.

But as its free, one should not complain I suppose :)


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5403
Subject: Re: [Q].FIFO in FPGA XILINX
From: Steve Wiseman <steve@sj.co.uk>
Date: Thu, 13 Feb 1997 19:57:40 +0000
Links: << >>  << T >>  << A >>
Peter wrote:

> >I am currently designing 106 Bytes(848 bits)FIFO in XILINX 4000E.
> >Is there any other more efficient way rather than using RAM cell macros?

> Yes, using an external RAM. Far cheaper, too.

It's served me well, but I'm not sure where the breakpoint is. For two
cells of FIFO, you may be better off using an external 'real' FIFO, to
get the pin-count down. Some cunning multiplexing ought to get you down
to 8 data pins and a handful of strobes. Small synchronous FIFOs (IDTs
Supersync?) make life easier, too. 32K*8 12/15nS SRAM is incredibly
cheap, but don't expect to be able to sustain cycles at 80MHz.... (16MHz
is comfortable, though, in ALtera 8k series, YMMV)

Hope that helps,
  Steve
Article: 5404
Subject: Re: Gate level Simulation with Mentors Quicksim from Galileo
From: Lance Gin <c43lyg@dso.hac.com>
Date: Thu, 13 Feb 1997 14:44:43 -0800
Links: << >>  << T >>  << A >>
Duncan Davis wrote:

> I am convinced I read a posting from someone regarding the topic of
> simulating at the gate level on Quicksim, having syntheised from Galileo.
> I seem to remember it involved EDIF. I think it appeared about a month or
> two ago.
> 
> Does this ring any bells with anyone or can anyone comment on methods for
> going from a VHDL entered design via, Galileo/Leonardo and simulating the
> result.

yes, i recall that thread from back last month. someone wanted to create an
eddm db for a design synth'd by galileo using its edif output. enread wasn't
able to read the edif properly (lib element problems as i recall). someone
suggested a workaround - resyn in al2, then run sg (eg. write eddm) to get
the schematic (should work ok) which can be sim'd.

you should be able to find the thread by using dejanews.

--

Lance Gin                            "Off the keyboard, over the bridge
Delco Systems-GM Hughes Electronics   through the gateway,
C43LYG@dso.hac.com                    nothing but NET!"
Article: 5405
Subject: Re: Anyone for Linux ?
From: jeffh@oakhill-csic.sps.mot.com (Jeff Hunsinger/RZXZ30/)
Date: 13 Feb 1997 23:23:08 GMT
Links: << >>  << T >>  << A >>

In article fsf@manocska.bendor.com.au, Zoltan Kocsi <zoltan@bendor.com.au> () writes:
> Hi,
> 
> It was very great news that Exemplar released Leonardo for Linux.
> The benchmark posted here also showed very pleasant results.
> So I rang the local Exemplar supplier.
> Now he told me that for a mere AUD37,000 I could have it (basic stuff).
> I'm not (yet) that rich, I'm afraid.
<SNIP> ...
> 
> So, I wonder if any of those family-specific cheap tools would ever be
> released under Linux ? The Exemplar release should be indicative that there's
> a potential market. Is it really that hard to port a HP or a Sun version
> to Linux ? Or, is it shameful to have a Linux version ?

I don't think it requires much effort to port the tools, but there's still cost
involved in paying people to support the platform. The Exemplar release is really
just testing the waters to see if Linux users are really willing/able to pay for their
tools. From your comment above, I guess not.

It's a catch-22. Software vendors don't want to support a platform with few
customers and customers aren't likely to switch platforms without software support.
Generally, it's the software vendors who take the lead. 

----------------------------------------------------------------------
Jeff Hunsinger
jeffh@oakhill-csic.sps.mot.com

Article: 5406
Subject: Mealy/Moore state machines
From: P Nibbs <pnibbs@icd.com.au>
Date: Fri, 14 Feb 1997 12:23:43 +1100
Links: << >>  << T >>  << A >>
Hi All,

I was wondering if someone could point out the advantages/disadvantages
and reasons between choosing between Mealy or Moore state machines.

How does it affect the performance of the state machine, and when
synthesised, what are the effects on the resulting circuitry?

Thanks in advance for any advice,

Cheers,

Phil.

Article: 5407
Subject: Re: PCI Prototyping board with a XC4013E or XC4013EX
From: Jim McManus <jamesm@xilinx.com>
Date: Thu, 13 Feb 1997 19:37:48 -0800
Links: << >>  << T >>  << A >>
Peeters wrote:
>even pci@xilinx.com never replied.

I don't recall seeing your e-mail come through, so I don't
know what happened. 

We are trying to phase out the pci@xilinx.com alias. Any 
technical questions, including PCI questions, should be 
addressed to hotline@xilinx.com.

To answer your question, I'm not aware of anyone who is 
marketing a PCI prototyping board with a Xilinx chip as the 
interface. 


------------------------------------------------------------------------
 / 7\'7 Jim McManus                       mailto:jim.mcmanus@xilinx.com 
 \ \ `  Xilinx PCI Applications Engineer  1-800-255-7778 (toll-free)    
 / /    2100 Logic Drive                  1-408-879-4729 Fax            
 \_\/.\ San Jose, California 95124                                      
        http://www.xilinx.com/products/logicore/lounge/pci/pci.htm      
------------------------------------------------------------------------
Article: 5408
Subject: Installation Problem with ACTEL Designer 3.1 on SunSolaris
From: koch@mikro.uni-stuttgart.de (Michael Koch)
Date: 14 Feb 1997 07:33:27 GMT
Links: << >>  << T >>  << A >>

Hi there, 

I'm currently installing Designer 3.1 in a networked license and
networked environment for ACTEL FPGAs on Sun-Workstations running Solaris. 
It seems to me, installation is a nightmare. Thus I would like to 
know if there is anybody out there having the same experience
and may be some hints or workarounds. 

Copying data from CD-ROM is quite a nice job, but starting the 
license server is terrible.

Any suggestions will be welcome.


Thanx in advance.



-----------------------------------------------------------------
name:    Michael Koch			   __    ____
depart:  Design Tools			  |  \  |_______ 
company: IMS 				  -   \_________|
adress:  Allmandring 30a	       ____
         70569 Stuttgart 		  |     /\    /\
         Germany			  |    /  \  /  \
phone:   xx49-711-685 5897		 _|___/   _\/   _\
fax:     xx49-711-685 5930
e-mail:   koch@mikro.uni-stuttgart.de
-----------------------------------------------------------------


Article: 5409
Subject: Re: Random Number Generators with Xilinx FPGA xc4000 series
From: "Richard Schwarz" <aaps@erols.com>
Date: 14 Feb 1997 08:25:50 GMT
Links: << >>  << T >>  << A >>
CHRISTOS,

CHECK OUT THE LINEAR RECURSIVE SEQUENCES TUTORIAL IN PDF FORMAT 
IN THE SPREAD SPECTRUM SECTION OF MY SITE AT:

http://www.erols.com/aaps

I wrote it several years ago for an article which appeared in RF Design
magazine. It tells you the basics on generating the sequences and gives
auto correlation trade offs for maximal and non maximal length codes. Also
you might want to check out the PN SIM program which is an older DOS
application based in Turbo Vision, but it has tables of at up to 100
different TAP weight settings for each family (register length) of
sequences. 

http://www.erols.com/aaps/spsp.htm   This takes you to the Spread Spectrum
page.

Also I am completing a VHDL example program which will run in the APS-X84
test FPGA board which will have a detailed analysis of writing PN/LRS/RNGs.
It can be
found on the same web server at:

http://www.erols.com/aaps/prog.htm

Then click the choice for the X-Files (X84 examples) I think you will enjoy
the motiff  as well as the up coming examples. I would be glad to send you
some preliminary stuff if you are in a bind.



Good Luck,

Richard Schwarz

John L. Smith <jsmith@univision.com> wrote in article
<3300E873.6AEF@univision.com>...
> Christos Dimitrakakis wrote:
> > 
> > Anyone got any info on RNGs?
> > Since I'm only generating a 6-bit number with it
> > I could just use a simple counter scheme for it that runs @8Mhz
> > while using one of the other clock outputs provided in the chip,
> > say the 490Hz one, for the rest of the circuitry.
> > Will that reduce the decorrelate the timing of the RNG from the
> > rest of the chip?
> > 
> > Is there any better way that does not take up a lot of chip area?
> > [I considered using a Fibonacci series, but it takes up too much space
> > if sufficient randomness is required]
> > 
> 
> Peter Alfke at Xilinx put together a good app note on compact
> long linear feedback shift registers for the 4000 family,
> available in pdf @
> 
> http://www.xilinx.com/apps/counter.htm
> 
> Use a long enough one, and you probably don't have to
> worry about correlation.
> 
> 
> 
> -- 
> John L. Smith
> Univision Technologies, Inc.
> 6 Fortune Drive
> Billerica, MA 01821-3917
> jsmith@univision.com
> 
Article: 5410
Subject: Re: Serial Communication Controller Design
From: Rune Baeverrud <r@acte.no>
Date: Fri, 14 Feb 1997 10:11:29 +0100
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> >Doing such designs in schematic is a waste of designer's time. This is
> >so much easier accomplished in a HDL.
> 
> Some people would differ.
> 
> It may be easier for *you* (if you are a VHDL expert) but it sure as
> hell is harder for me if I am not a VHDL expert (and one does have to
> be quite good at VHDL to avoid getting into a right mess, which means
> using it a lot) or if I cannot afford to cough up $Xk for a new Xilinx
> FPGA design suite with VHDL capability.

I'm not an VHDL expert. I'm just learning how to exploit another
language, the Altera Hardware Description Language (AHDL). I was also,
until recently, a schematic addict, but it is only now I start to
realize how much more power I have in such a language, it is extremely
easy to learn and understand!. Also, I would not have been able to
complete the design in schematics, because I don't have all the
parameterizable features there. In AHDL, I can generate a fancy kind of
register of any length based on a parameter input, so easy, so readable,
so powerful! The Altera PLS-ES package shouldn't set you back by more
than about $500.

> Why does anyone use a 16550 with its "limited" functionality? The IBM
> PC also has a limited functionality, but for some reason seems to be
> quite popular nowadays.
> 
> Let me tell you: a UART is very rarely useful without a microprocessor
> around. The micro needs to be able to set the baud rate. So one had a
> baud rate generator. It needs to get interrupts. So one has circuitry
> for that. And so on.
> 
> I don't see that the 16550 has a particularly "limited" functionality.
> They should have provided IRQ capability from *all* the status bits,
> but again it would be easy to add that if one had a circuit.

The limitations of the 16550 is this:

1) You can't make an 11-bit UART. How do you do that? With programmable
logic, of course!

2) Why would I want all the 16550 fancy registers to consume valuable
space in my FPGA, when a basic functionality UART will do everything I
need at a fraction of the space requirements?

3) By using the 16550, the interface is designed for a microcontroller.
This make it harder to use if you want to interface with programmable
logic instead.

Of course, with a basic functionality UART you may have to twiddle some
bits to get the interrupt conditions you want, but this really PEANUTS!
You are working with programmable logic, so what's the problem?!?
 
> But as its free, one should not complain I suppose :)

I guess :)
-- 
Rune Baeverrud <r@acte.no>           
Field Application Engineer                    |\      _,,,---,,_
ScandComp, ACTE NC Norway AS            ZZzz  /,`.-'`'    -.  ;-;;,_
P.O. Box 190, N-2020 Skedsmokorset, Norway   |,4-  ) )-,_..;\ (  `'-'
Tel: +47 6389 8969   Fax: +47 6389 8979     '---''(_/--'  `-'\_)
Article: 5411
Subject: Lucent Foundry (PC) bug
From: eteam@aracnet.com (bob elkind)
Date: Fri, 14 Feb 1997 11:31:05 -0000
Links: << >>  << T >>  << A >>
In case you didn't know, the latest version (9.0x) of
Lucent (Orca) Foundry has the following minor bug:

Epic (EditLCA equivalent :-) ) won't display the guts of
the edited device if your Windows display is configured
for more than 256 colours.

This is a minor annoyance, easily circumvented.  But you
might spin your wheels lots looking for the answer (hint:
it's not on the support website yet!).

-- Bob

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5412
Subject: Re: [Q].FIFO in FPGA XILINX
From: Scott Kroeger <Scott.Kroeger@mail.mei.com>
Date: Fri, 14 Feb 1997 08:25:34 -0600
Links: << >>  << T >>  << A >>
Steve Wiseman wrote:
> 
> Peter wrote:
> 
> > >I am currently designing 106 Bytes(848 bits)FIFO in XILINX 4000E.
> > >Is there any other more efficient way rather than using RAM cell macros?
> 
> > Yes, using an external RAM. Far cheaper, too.
> 
> It's served me well, but I'm not sure where the breakpoint is. For two
> cells of FIFO, you may be better off using an external 'real' FIFO, to
> get the pin-count down. Some cunning multiplexing ought to get you down
> to 8 data pins and a handful of strobes. Small synchronous FIFOs (IDTs
> Supersync?) make life easier, too. 32K*8 12/15nS SRAM is incredibly
> cheap, but don't expect to be able to sustain cycles at 80MHz.... (16MHz
> is comfortable, though, in ALtera 8k series, YMMV)

A vague recollection of the 7200 FIFO family from 1993:

7200 (256 x 9 @ 10MHz) = $3.  @30MHz = $6.

Regards,
Scott
Article: 5413
Subject: CFP: Int. Wkshp. on Logic Synthesis (IWLS) 97: Deadline Extended
From: sharad@new-delhi.Princeton.EDU (Sharad Malik)
Date: 14 Feb 1997 15:46:56 GMT
Links: << >>  << T >>  << A >>
           1997 IEEE/ACM International Workshop on Logic Synthesis

		http://www.ee.princeton.edu/iwls97.html

                 Granlibakken Resort, Lake Tahoe, California

                              May 18-21 , 1997


                           Call for Participation

		Submission Deadline extended to March 1, 1997

(Papers submitted to IWLS are eligible for submission to ICCAD.)

Contents

  1. Synopsis
  2. Benchmarks
  3. About IWLS
  4. About Granlibakken
  5. Executive Committee
  6. Technical Program Committee
  7. Sponsored by...

Synopsis

Logic Synthesis has traditionally focused on optimization techniques for
combinational and sequential circuits through the manipulation of Boolean
equations and state machines. IWLS '97, the sixth workshop in this series,
seeks presentations both on these topics and on new directions in
synthesis-based design methodology. Topics of interest include:

   Area, timing, power optimization              Logic synthesis systems

   CMOS, ECL, GaAS Optimization       Designer Experiences with Synthesis

   Two-level Logic Optimization          Interaction with physical design

   Multi-level Logic Optimization       Incremental Synthesis/ECO Support

   FSM Optimization                          Asynchronous Logic Synthesis

   Sequential Circuit Optimization                    Formal Verification

   Retiming and resynthesis                 Optimization at the RTL Level

   Technology Mapping                                 Timing Verification

   FPGA and PLD Synthesis                  Testing and Synthesis for test

   Don't-Cares and Boolean Relations   Interaction with module generators

   Symbolic Synthesis                Use of synthesis in new applications

   Synthesis in FPGA-Based Emulation                  Applications of SAT

Authors may submit extended abstracts for their proposed presentation. These
must be no less than 1000 words and no more than 2500 words. These abstracts
are not intended to be complete papers, but rather should convey the main
ideas of the proposed presentation. We encourage submissions in the early
stages of research which may highlight important new problems without
necessarily providing complete solutions. The abstracts may be submitted by
e-mailing self-contained Postscript files to iwls-submit@ee.princeton.edu by
March 1, 1997.  Acceptance notices will be sent by March 31, 1997. A set
of workshop notes will be distributed at the conference. There will be no
published proceedings.

Benchmarks

A benchmark set is being assembled by the CAD Benchmarking Laboratory. To
contribute new benchmarks, or to obtain information about the existing
suite, please write: benchmarks@cbl.ncsu.edu.

About IWLS

IWLS '93 and IWLS '95 introduced a number of format changes from previous
workshops, which the committee tentatively intends to maintain for IWLS '97.
These include an open program with high acceptance rate, heavy use of
posters and short talks for presentation, and large amounts of time in the
schedule for poster presentations. In addition, IWLS '97 will emphasize open
discussions and ongoing research which are not provided by the traditional
conference format.

About Granlibakken

The Granlibakken Conference Center is located in Tahoe City on the west
shore of Lake Tahoe, 180 miles east of San Francisco. It boasts 160 rooms,
clustered into two- and three-bedroom condominiums. Each bedroom is an
attractive hotel room with private bath. Many of the clusters share a
kitchen, living room and dining room -- a miniature lobby for private
meetings. Organizations sending several people to the workshop may wish to
rent entire two- and three-bedroom townhouses.

The Granlibakken management has reserved space on Thursday, May 22 for
organizations who wish to hold private, one-day workshops immediately
preceding IWLS, and have agreed to charge organizations the IWLS conference
rate for these meetings. Contact Mary Brown at Granlibakken sales
(1-800-552-4494) for details. Granlibakken is within 10 minutes' drive of
the West's premier ski resorts: Alpine Meadows and Squaw Valley USA. When
California enjoys high snowfall, both areas remain open until Memorial Day.
A wealth of hiking trails snake through the area. Weather permitting,
Granlibakken's tennis courts and pool will be open for use.

The weather in late May is variable; warm, sunny days and cool clear nights
are the rule.

Getting There

Granlibakken is easily reached from either the San Francisco Bay Area or
Reno, NV. Take Interstate 80 to Truckee. From there, follow State Route 89
south to Tahoe City. Turn right at the stop light in Tahoe City. After 1/4
mile, turn right on Granlibakken road and proceed to the end.

Contacts/Executive Committee

 General Chair   Rick     Cadence       mcgeer@cadence.com      (408)
                 McGeer   Berkeley Labs                         428-5325
 Tech. Program   Sharad   Princeton                             (609)
 Chair           Malik    University    sharad@ee.princeton.edu 258-4625
 Benchmark       Franc                                          (919)
 Chair           Brglez   NCSU          brglez@cbl.ncsu.edu     248-1925
 Conference      Kris     Cadence                               (408)
 Coordinator     Lamanno  Berkeley Labs krisl@cadence.com       894-2479

Technical Program Committee

      Pranav Ashar         NEC
      Michel Berkelaar     TU-Eindhoven
      Robert K. Brayton    UC Berkeley
      Franc Brglez         NCSU
      Giovanni de Micheli  Stanford
      Srinivas Devadas     MIT
      Ewald Detjens        Mentor Graphics
      Antun Domic          Cadence
      Masahiro Fujita      Fujitsu Laboratories of America
      Wolfgang Kunz        University of Potsdam
      Luciano Lavagno      Politecnico di Torino/Cadence Berkeley Labs
      Ken McElvain         Synplicity
      Rick McGeer          Cadence Berkeley Labs
      Sharad Malik (chair) Princeton University
      Shin-ichi Minato     NTT
      Massoud Pedram       USC
      Richard Rudell       Synopsys
      Tsutomu Sasao        Kysushu Institute of Technology
      Gabriele Saucier     INPG
      Ellen Sentovich      Cadence Berkeley Labs
      Fabio Somenzi        University of Colorado
      Leon Stok            IBM TJ Watson Research Center

Sponsor

Sponsored by the IEEE Computer Society, Technical Committee on VLSI. In
co-operation sponsoship by ACM/SIGDA is being sought.
-- 
Sharad Malik                            sharad@ee.princeton.edu
Associate Profesor                      609-258-4625
Dept. of Electrical Engineering         609-258-3745 Fax
Princeton University                    http://www.ee.princeton.edu/~sharad
Article: 5414
Subject: Lucent Orcas ...
From: John Smith <tepa1@solx1.susx.ac.uk>
Date: Fri, 14 Feb 1997 17:09:58 +0000
Links: << >>  << T >>  << A >>
Hello,

If anyone is using Lucent Orcas with a download cable or
with EPROMS could you please answer a couple of question.

1) The pin-out of the download cable is not consistent
   between the manual and the actual device. Any 
   suggestions ?

2) What should the baud rate be ?

Regards

John Smith
University of Sussex
Article: 5415
Subject: Re: Altera BitBlaster
From: Iakovos Stamoulis <I.Stamoulis@Sussex.ac.uk>
Date: Fri, 14 Feb 1997 18:21:52 +0000
Links: << >>  << T >>  << A >>
Hello,

I was annoyed by the price of the bitblaster but he had no other
choice. However, I think, my bitblaster is dying so I would 
prefer to use your program that being ripped-off twice.
Can I have a copy please.

Why do you load the *.TTF file and not the *.SBF file ?

Thanks

Iakovos Stamoulis
University of Sussex
Article: 5416
Subject: Re: Gate level Simulation with Mentors Quicksim from Galileo
From: James Cleary <jec@kato.si.com>
Date: Fri, 14 Feb 1997 14:20:01 -0500
Links: << >>  << T >>  << A >>


Lance Gin wrote:
> 
> Duncan Davis wrote:
> 
> > I am convinced I read a posting from someone regarding the topic of
> > simulating at the gate level on Quicksim, having syntheised from Galileo.
> > I seem to remember it involved EDIF. I think it appeared about a month or
> > two ago.
> >
> > Does this ring any bells with anyone or can anyone comment on methods for
> > going from a VHDL entered design via, Galileo/Leonardo and simulating the
> > result.
> 
> yes, i recall that thread from back last month. someone wanted to create an
> eddm db for a design synth'd by galileo using its edif output. enread wasn't
> able to read the edif properly (lib element problems as i recall). someone
> suggested a workaround - resyn in al2, then run sg (eg. write eddm) to get
> the schematic (should work ok) which can be sim'd.
> 
> you should be able to find the thread by using dejanews.
> 
> --
> 
> Lance Gin                            "Off the keyboard, over the bridge
> Delco Systems-GM Hughes Electronics   through the gateway,
> C43LYG@dso.hac.com                    nothing but NET!"

We got dumped with Galileo by Mentor when they took away FPGA capability
with Autologic. After checking Galileo out we decided that it was 
unacceptable. A few of the main capabilities we had with Autologic were
not available in their (or Exemplar's) Galileo tool. No hierarchy, etc.
So we decided to go with Synopsys FPGA tools.

If you plan on using the latest Mentor software (B.3) then you can't use
Autologic to resyn because FPGAs are no longer supported.

The problem i saw with Galileo EDIF output was that the component names 
are uppercase. You end up with something like 
		cell INV
I believe a quick perl script could lowercase the component name and 
after setting a link to the xilinx libs the EDIF will read in
successfully.

Before the link is created i get can't find library xi5.
Set the link    
		ln -s /home/xxx/xilinx_5.2.1/xc5200 xi5   
(replace /home/xxx/... with correct path,  i am using 5200 library)

Run the attached perl script on your EDIF file and save it away to 
a new file.
		edif_fix yourEDIFfile > newEDIFfile

Then run enread on the new file.

		setenv MGC_WD `pwd`
		enread newEDIFfile

This will create an eddm database which you can run schematic generator
on
to create the schematics and then you can invoke quicksim on the design.


James Cleary
CAD Application Support Wizard

>>>>>>>>>>>>   filename="edif_fix"

#! /usr/local/bin/perl
$edif_file = shift;
open(INFILE,$edif_file);
while (<INFILE>) 
{
	$line = $_;
	@temp = split(/\(/,$line);

	foreach (@temp)
	{
		if(grep(/cellRef/,$_))
		{
			$_ =~ s/cellRef//g;
        		$_ =~ s/\s//g;    
        		$_ =~ tr/A-Z/a-z/;
			$line =~ s/cellRef \w+/cellRef $_/;
		}
		elsif (grep(/cell /,$_))
		{
			$_ =~ s/cell//g;
			$_ =~ s/\s//g;
			$_ =~ tr/A-Z/a-z/;
			$line =~ s/cell \w+/cell $_/;
		}
	}
	print $line;
}
close INFILE;




Article: 5417
Subject: Re: Altera support better than Xilinx
From: waynet@goodnet.com (Wayne Turner)
Date: Fri, 14 Feb 97 20:05:20 GMT
Links: << >>  << T >>  << A >>

Actually, you're wrong.  I already posted info from Intel's FlexLogic data 
sheet that stated their FlexLogic parts were FLASH-based.  Altera just bought 
them that way.  If you have data to the contrary, please post it.

Wayne

In article <01bc16d5$34c4f760$97e12399@default>, "Rhondalee Rohleder" 
<Rhondalee_Rohleder@msn.com> wrote:
>Actually, you're *both* right.  The devices available in the Intel
>FLEXlogic line at the time it was sold were EPROM-based.  But Intel had
>planned from the outset to convert the line to FLASH, beginning with the
>introduction of subsequent devices -- Altera just followed through on
>Intel's plans after acquiring the line.  At the same time, the line was
>renamed FLASHlogic to avoid confusion with FLEX.
>
>Rhondalee Rohleder
>Pace Technologies (Scottsdale, AZ)
>
>Dean Brown <deankb@popd.ix.netcom.com> wrote in article
><32F2B2A7.568F@popd.ix.netcom.com>...
>> Wayne Turner wrote:
>> > 
>> > In article <5cs4oq$cf5@borg.svpal.org>, garyk@svpal.svpal.org (George
>Noten) wrote:
>> > >Wayne Turner (waynet@goodnet.com) wrote:
>> 
>> > 3.  Converted?  What the hell are you talking about?  It was FLASH when
>Intel
>> > owned it, it was just called FlexLogic.  When Altera bought it they had
>to
>> > change the name because they already had the FLEX 8000 family and
>didn't want
>> > it to be confused.  So they named the part according to what it really
>was:
>> > FLASH.  Hence the name FlashLogic.
>> 
>> The Intel part was EPROM based, Altera re-engineered it to Flash, then
>> dropped it less than a year later. The Flash based EPX880 was a direct
>> drop in replacement for the IFX780, so customer support shouldn't be
>> based on the 880 part but on the 780 as well which was available for 4-5
>> years.
>> 
Article: 5418
Subject: Re: Lucent Orcas ...
From: wen-king@myri.com (Wen-King Su)
Date: 14 Feb 1997 17:41:41 -0800
Links: << >>  << T >>  << A >>
In a previous article John Smith <tepa1@solx1.susx.ac.uk> writes:
:
;Hello,
:
;If anyone is using Lucent Orcas with a download cable or
:with EPROMS could you please answer a couple of question.
;
:1) The pin-out of the download cable is not consistent
;   between the manual and the actual device. Any 
:   suggestions ?

My download cable works.  Pinout is:

1 Vdd
2 CCLK
3 DATA
4 DONE
5 PGM-
6 GND
7 NC

:2) What should the baud rate be ?

9600 works just fine.
Article: 5419
Subject: Xilinx programming...
From: David Charles Hirschfield <dch+@andrew.cmu.edu>
Date: Fri, 14 Feb 1997 21:07:18 -0500
Links: << >>  << T >>  << A >>
Can anyone answer some questions I have about programming a Xilinx
XC4003A FPGA board?

I'm working on a project that would allow students to program a Xilinx
board remotely over a network. Without going into the gory details of
the design we're using, we have come to the conclusion that we cannot
use the Xilinx XChecker cable or XChecker (the download program) to do
the downloading of bit files to the board.

We were able to get some xchecker replacement code that works with
XC3000 and XC2000 series FPGA boards written by Scott Kroeger.
Unfortunately we have been unsuccessful in programming XC4000 boards
with that code.

In the rather meager documentation we have we've uncovered some
information about the cable connections and programming cycle...but not
nearly enough.

Does anyone know of in depth documentation on programming xilinx boards,
making your own download cables or anything else even remotely related
to what's in this post?

Thanks in advance,
-David Hirschfield

PS: The web page for the project is at: http://srv.res.cmu.edu/xilinx/


+-===========================================================================-+
|                                                --== e-mail ==--             |
|     _/_/_/      _/_/    _/   _/  _/_/_/       dch@andrew.cmu.edu            |
|    _/    _/  _/    _/  _/  _/   _/                   or                     |
|   _/    _/  _/_/_/_/  _/ _/    _/_/       dhirschfield@giss.nasa.gov        |
|  _/    _/  _/    _/  _/_/     _/                                            |
| _/_/_/    _/    _/  _/       _/_/_/             --== WWW ==--               |
|                                          http://srv.res.cmu.edu/~dch/       |
+-===========================================================================-+
 
Article: 5420
Subject: HELP: XC4000 download cable
From: David Charles Hirschfield <dch+@andrew.cmu.edu>
Date: Fri, 14 Feb 1997 21:33:17 -0500
Links: << >>  << T >>  << A >>
I'm trying to build an xchecker cable replacement and an xchecker
program replacement for programming Xilinx XC4003A Demo boards, I have
some documentation on the pin connections needed but I need some
clarification.

The documentation says that for the XC4000 the programming/downloading
process is as follows:

Raise the PROG line, wait some indeterminate time, and then lower it to
begin programming the board.

Toggle the CCLK line while feeding data to the DIN line until all the
bits in the .bit file have been sent.

If everything went OK, the DONE line should go high, signaling that the
board got the program.

Have I got this routine right?
Are all my high/low signals correct?
Does anyone have more information on this process? Specifically, does
anyone know exactly what timings and settings the board requires?

Thanks for any help,
-David Hirschfield

+-===========================================================================-+
|                                                --== e-mail ==--             |
|     _/_/_/      _/_/    _/   _/  _/_/_/       dch@andrew.cmu.edu            |
|    _/    _/  _/    _/  _/  _/   _/                   or                     |
|   _/    _/  _/_/_/_/  _/ _/    _/_/       dhirschfield@giss.nasa.gov        |
|  _/    _/  _/    _/  _/_/     _/                                            |
| _/_/_/    _/    _/  _/       _/_/_/             --== WWW ==--               |
|                                          http://srv.res.cmu.edu/~dch/       |
+-===========================================================================-+
 
Article: 5421
(removed)


Article: 5422
Subject: Financial Aid
From: John Little <jmlittl@clemson.edu>
Date: Sat, 15 Feb 1997 01:04:47 -0600
Links: << >>  << T >>  << A >>
If you are reading this now, you, like me, are
badly in need of money. Believe me, I understand.
If the United States had debtor's prison, I'd have
been in it years ago. However, there is a way out.
All you have to do is use the follow program.
You can make HUNDREDS, if not THOUSANDS OF DOLLARS.

Mail a single dollar bill to each of the following
people, along with a note which says:

"Please add me to your list. My name
and address is (include your name and address)."

(1)	Ralph
     	7439 Hwy 70 S. #268
     	Nashville, Tn. 37221

(2)	Bob Sullivan
       	4553 Atascadero Dr.
       	Santa Barbara, Ca. 93110

(3)	Bill Gray
       	8114 SW 104th Way
       	Gainesville, FL  32608

(4)	Y. Yuksel
       	1561 Mesa Dr. #123
       	Santa Ana, CA 92707

(5)	J. M. Little
	Clemson University
	P.O. Box 3669
	Clemson, SC  29632-3669

Then copy this message, and re-post it to as many
newsgroups as you can, but with the following changes:

Erase the first person's address.
Move each of the remaining addresses up one number. 
	(#2 becomes #1, #3 becomes #2, etc.)
Add your name and address as the fifth one.


What will happen is this. Others who, like you, are
in need of money, will read your message, just as
you are reading this one, and decide that they need
the extra cash. They will send you their one dollar
bill, and repost the message, making the same changes
you did. You will still be on the list as #4. Someone
will read their message, send money to everyone on the
list, including you, and post another message, making
the changes. You will still be on the list as #3. This
will continue until you are off the list, but by the time
you are off the list, AT LEAST five people will send you
money. There's the five dollars you sent. I cannot
confirm them, but there are continuous statements about
how people have made hundreds, thousands, and even tens
of thousands of dollars with this plan. Remember, the
more places you put this, the more money you make.

Does this seem unreasonable? It shouldn't. There are
millions of people in the United States just like you,
who need money, and are looking for a solution.
Thousands of people are getting on the internet for the
first time, every day, and each of them wants to make
money. Is it so unbelievable that they, like you, will
follow this plan, hoping for a big return? At most, it
will cost you ten dollars:  one dollar for each person,
and five for the pen, stamps, and envelopes.

Is it impossible for you to imagine there are ten people
somewhere in America who want to make money?

If there are, then you've only lost a little time. But
in fact, there are MILLIONS of people who NEED the money,
and they are looking for ANY chance to make some. You
will more than make up for any time or money you spend.

Is this program illegal? No. There's nothing illegal, or
even shady, about this. Do you want proof?

1.  The inclusion of the message "Add my name to your
	list." makes this a service, just like any TV
	advertisement or 1-900 number. Are those illegal?

2.  Does the federal government police the internet? No.
	Do they open your mail? No. THAT would be illegal.

3.  If this were illegal, do you really think I'd be dumb
	enough to give the police my address?

Please, support this program. There is the potential for
both you and I to make a LOT of money together. Thank you.
Article: 5423
Subject: Re: Inversion 1/T with registers
From: Tom Burgess <Tom_Burgess@bc.sympatico.ca>
Date: Sat, 15 Feb 1997 00:50:45 -0700
Links: << >>  << T >>  << A >>
bergeon wrote:
> 
> Can someone tell me where I can find a structure of a system which can do a
> 1/T
> (T is in BCD) with registers.
> 
> Yves B.

To provide both frequency and period readings from a counter, one can 
simply swap the count and gate inputs. For example, with an unknown
input clock and a 1 second gate, you get frequency in Hz.
With a fixed 1 MHz clock and an unknown gate (divided by two to get a 
constant high for the entire period) you get the reciprocal period (in 
microseconds). Perhaps your problem can be similarly restructured to
avoid division? (the use of T for the quantity to be inverted seemed 
suggestive)

	regards, tom
Article: 5424
Subject: Re: Gate level Simulation with Mentors Quicksim from Galileo
From: Kayvon Irani <kirani@cinenet.net>
Date: Sat, 15 Feb 1997 00:37:58 -0800
Links: << >>  << T >>  << A >>
James Cleary wrote:

> We got dumped with Galileo by Mentor when they took away FPGA capability
> with Autologic. After checking Galileo out we decided that it was
> unacceptable. A few of the main capabilities we had with Autologic were
> not available in their (or Exemplar's) Galileo tool. No hierarchy, etc.
> So we decided to go with Synopsys FPGA tools.


	Did you guys consider Leonardo? It does support hierachical designs and 
	a lot more bells and whistles than Galelio.

	Regards,
	Kayvon Irani
	Los Angeles


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search