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Messages from 5500

Article: 5500
Subject: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
From: peter@xilinx.com (Peter Alfke)
Date: Thu, 20 Feb 1997 17:41:03 -0700
Links: << >>  << T >>  << A >>
In article <330ffbe3.915085@149.174.214.137>, r.m.muench@ieee.org (Robert
M. Muench) wrote:

> Hi,
> 
> I'm interested in the set of functions which get mostly implemented
> using FPGAs? And in any information where are the biggest problems
> faced when using FPGAs.
> 
Robert, you did not get a meaningful response the first time. I suppose
that's because the question is too general. FPGAs vary in complexity from
1000 gates to astronomical 100 k gates or more, depending on where
marketing puts the upper limit.
SRAM-based FPGAS are flip-flop rich, but interconnect delays are not
negligible. So they lend themselves to pipelined designs. Some have
dedicated carry, so they can count and add efficiently. Most of them are
not as good as CPLDs at decoding wide inputs and encoded state machines.
But basically, FPGAs can implement any type of logic, although they don't
do asynchronous logic very well or very reliably. Too much variability in
the interconnect delay.
FPGA limitations are mainly in size, speed and cost. And their use and
usefulness is heavily influenced by the production volume, where
high-volume designs tend towards ASICs. But there is also the issue of
original time-to-market ( design time ) and the (in)stability of the
design, the market and the standards that drive that market.  The latter
must be the reason for the present love affair between telecom and FPGAs.
Then there is the very young field of reconfigurable logic and
reconfigurable computing, where SRAM-based FPGAs are the only game in
town. 
With the very fast and accelerating progress in FPGA size and speed and
the associated price reductions, and with better software, FPGAs will
gobble up more and more of the logic market. 
Don't use them for very well standardized functions, like microprocessors,
memory, and certain dedicated pripherals, and don't them for appplications
well above 100 MHz. Use them everywhere else.

The biggest obstacle seems to be the unfamiliarity of some hardware
designers with the more sophisticated tools that are needed to design with
FPGAs. Tool simplicity and similarity to PALs are, in my mind, the reasons
for the still very healthy growth rate of CPLDs. But that may be personal
bias.

As the salesman says: Consider FPGAs. If you don't, your competitor does.

Greetings und Alles Gute,

Peter Alfke, Xilinx Applications
Article: 5501
Subject: Re: State Diagram Tools
From: "Stephen J. Singer" <sjsinger@ix.netcom.com>
Date: Thu, 20 Feb 1997 18:31:07 -0800
Links: << >>  << T >>  << A >>
Kevin D. Drucker wrote:
> 
> Sorry about the psuedo-spam...
> 
> I am looking for a tool to assist me in documenting state machines.
> Something similar to Rational Rose (which is a C++ tool), but
> specifically geard towards digital logic design.  It would be nice if it
> allowed you to show the diagrams either as a mealy or moore type
> machine.
> 
> Any one know of such a tool?  If there is a shareware program out there
> that'd be great.  Windoze 95 or HP-UX...
> --
> -Kevin
> 
> Kevin D. Drucker        |  email: kdrucker@hns.com
> Member Technical Staff, |  work:  (301) 601-4167
> Hardware Development    |  fax:   (301) 601-4275
> Hughes Network Systems  |

Have you looked at StateCAD by Visual Software Solutions,
1-800-208-1051, www.statecad.com/ae10.
Article: 5502
Subject: Q: Anyone bought APS-X84 FPGA board?
From: <dnk@io.com>
Date: 21 Feb 1997 02:35:26 GMT
Links: << >>  << T >>  << A >>
More accurately, has anyone ordered and received the board + software?

	http://www.erols.com/aaps/X84price.htm

I've ordered the board + Xilink software almost 5 weeks ago and have
yet to see anything.  (Apparently they are waiting on the Xilink
software.)  Maybe I've been spoiled by mail order companies like
MacMall and MicroWarehouse, but 5 weeks seems like an eon (is this
typical of FPGA related companies?).  At least I'd expected the board
shipped right away, and the Xilink software delivered as soon as they
got it.  At least there are some pluses: they haven't charged my credit
card yet, they are prompt in replying to email and are updating their
web pages....

Thanks for your time,

Danny Kumamoto

mailto:dnk@pobox.com   http://www.pobox.com/~dnk     TEL: +1 512-918-3640
Postal: 13492 Research Blvd., Suite 120-295, Austin, TX 78750-2254, U.S.A.
Article: 5503
Subject: Re: Q: Search Engines for Electronic Parts?
From: David R Mulligan <skipper@interlog.com>
Date: Thu, 20 Feb 1997 21:59:53 -0500
Links: << >>  << T >>  << A >>
Try http://www.scruznet.com/~gcreager

and

http://www.hitex.com/~chipdir/chipdir.htm

David
skipper@interlog.com

Lance Gin wrote:
> 
> I'm wondering if there are any internet search engines out there
> exclusively for looking up commercial electronic parts?
> 
> I envision an engine that would allow searching by part numbers,
> manufacturers, or functional catagory. Manufacturer and datasheet
> info would be nice.
> 
> The only engines I've seen so far are the ones proprietary to
> distributors like Hamilton/Avnet and Marshall. I believe for-fee
> databases are also available (eg. on CDROM) but I'm not sure who
> these companies are.
> 
> Thanks in advance,
> 
> --
> 
> Lance Gin                            "Off the keyboard, over the bridge
> Delco Systems-GM Hughes Electronics   through the gateway,
> C43LYG@dso.hac.com                    nothing but NET!"
Article: 5504
Subject: Re: [Q] Xilinx FPGA Resources
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 21 Feb 1997 00:27:49 -0500
Links: << >>  << T >>  << A >>
Check at http://www.erols.com/aaps


Article: 5505
Subject: Re: Q: Search Engines for Electronic Parts?
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 21 Feb 1997 00:55:55 -0500
Links: << >>  << T >>  << A >>
Take at look at the favorite links section at http://www.erols.com/aaps

Article: 5506
Subject: Re: State Diagram Tools
From: please@no.junk.mail.com (Mike Williams)
Date: Fri, 21 Feb 1997 07:47:39 GMT
Links: << >>  << T >>  << A >>
On Thu, 20 Feb 1997 18:31:07 -0800, "Stephen J. Singer"
<sjsinger@ix.netcom.com> wrote:

>Kevin D. Drucker wrote:
>> 
>> Sorry about the psuedo-spam...
>> 
>> I am looking for a tool to assist me in documenting state machines.
>> Something similar to Rational Rose (which is a C++ tool), but
>> specifically geard towards digital logic design.  It would be nice if it
>> allowed you to show the diagrams either as a mealy or moore type
>> machine.
>> 
>> Any one know of such a tool?  If there is a shareware program out there
>> that'd be great.  Windoze 95 or HP-UX...
>> --
>> -Kevin
>> 
>> Kevin D. Drucker        |  email: kdrucker@hns.com
>> Member Technical Staff, |  work:  (301) 601-4167
>> Hardware Development    |  fax:   (301) 601-4275
>> Hughes Network Systems  |
>
>Have you looked at StateCAD by Visual Software Solutions,
>1-800-208-1051, www.statecad.com/ae10.

Yes. Checkout StateCad.

I've been using StateCad for awhile now and find it a great tool.
I enter bubble diagrams and it generates the Verilog. I'm currently
evaluating a beta version that includes a state machine simulator. 

Mike Williams

mcw"at"lightlink.com

Article: 5507
Subject: Re: Mealy/Moore state machines
From: Albrecht Ditzinger <albrecht.ditzinger@isdata.de>
Date: Fri, 21 Feb 1997 09:03:13 GMT
Links: << >>  << T >>  << A >>
rtekumal@visakha.ecs.umass.edu (Ramesh C. Tekumalla) wrote:
>
>I am not sure why a moore machine would require "more states". I think it
>is only necessary to have a different output combination for each state.
>From the circuit point of view, the inputs in the output logic of a moore
>machine are only present state variables. When synthesizing a sequential
>circuit, we may end up with the above situation even if the outputs are
>specified on the state transitions. Also, since the output is totally
>dependent on the state variables, testing of such circuits may be
>complicated and hence they may have poor performance in complex systems.
>

There is one more aspect: When a Moore FSM is implemented, there will be some logic 
*behind* the flops which decodes the states to the outputs. This logic might generate 
spikes again.

To avoid this, some synthesizers can be instructed to move this logic in front of the 
flop and merge it with the state transistion logic (use Z-VALUES for our LOG/iCxx tools). 
The result has the same timing as the originally defined Moore FSM, in fact it is a 
little faster because there is no output decoding, but has absolutely clean outputs.

This is only possible, if each state has a unique output vector. If not, you have, or the 
software has, to add additional flops to make it unique. But that is the only price you 
will have to pay.

IMHO this is the best solution for CPLDs (saves MCs) and most likely also for FPGAs (No 
glitches, no logic behind the flop).

Albrecht

-- 
Albrecht Ditzinger
ISDATA GmbH Karlsruhe   WWW: http://www.isdata.de

A very old bavarian saying says: Saving on design tools 
means paying a fortune for devices.


Article: 5508
Subject: Re: State Diagram Tools
From: bdstoehr@ise.ipvr.informatik.uni-stuttgart.de (Bernd Stoehr)
Date: 21 Feb 1997 09:17:04 GMT
Links: << >>  << T >>  << A >>
Hi,

there is also a graphical FSM tool for designing hierarchical FSMs. You can
also describe parallel FSMs. The tool can generate syntheziable VHDL-Code (flat 
or hierarchical). You need Win 95, NT to run the FSM-Editor.


Look at www.isdata.de/english/rel50.htm 




Article: 5509
Subject: Re: Q: Search Engines for Electronic Parts?
From: Tim Forcer <tmf@ecs.soton.ac.uk>
Date: Fri, 21 Feb 1997 09:33:26 +0000
Links: << >>  << T >>  << A >>
Lance Gin wrote:
> 
> I'm wondering if there are any internet search engines out there
> exclusively for looking up commercial electronic parts?
> 
> I envision an engine that would allow searching by part numbers,
> manufacturers, or functional catagory. Manufacturer and datasheet
> info would be nice.
> 
> The only engines I've seen so far are the ones proprietary to
> distributors like Hamilton/Avnet and Marshall. I believe for-fee
> databases are also available (eg. on CDROM) but I'm not sure who
> these companies are.

If you don't mind the search "engine" being your mouse wandering around
a Web browser, try Chip Directory.  Main site is 

http://www.xs4all.nl/~ganswijk/chipdir/chipdir.html

but there are also mirrors all over.

Chip Directory includes numerically-ordered IC info, links/addresses for
manufacturers/distributors, and lots of other IC-related stuff.  There's
also an associated mailing list for queries (email version of a
help-wanted newsgroup).

This suggestion is based on my personal experience of a very useful
site.

-- 
Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University, Southampton, SO17 1BJ     UK
Article: 5510
Subject: replicating structure in MaxPlus
From: seamang@westminster.ac.uk (Graham Seaman)
Date: 21 Feb 1997 09:42:00 -0000
Links: << >>  << T >>  << A >>
Hi all,

I'm trying to implement a cellular structure using Altera's
MaxPlus software; that is, I have a simple basic 'cell' of
about 10 gates which I need to replicate many times across
the FPGA (connections are mostly NEWS style; ie. to 4 nearest
neighbours of each cell).
 If I was doing this in VHDL, I'd just use the 'generate'
statement in a nested for loop. But I don't have VHDL, only
AHDL, and can't work out a good way of doing this. Or am
I better off sticking to schematic entry (lots of cut-and-paste)?

Anyone got any ideas?
Thanks for any help
Graham

-- 
--------------------------------------------------------------------
Graham Seaman, School of Computer Science, 
University of Westminster, 115 New Cavendish St.  London W1M 8JS 
email:  seamang@wmin.ac.uk www: http://www.scsise.wmin.ac.uk/~seamang
Article: 5511
Subject: Re: Xilinx or Altera?
From: eteam@aracnet.com (bob elkind)
Date: Fri, 21 Feb 1997 10:44:13 -0000
Links: << >>  << T >>  << A >>
In article <330b7df1.111451498@news-s01.ny.us.ibm.net>, aquantz@ibm.net 
says...

     <SNIP> 
> Sounds like a sales pitch to me. I used Xilinx and found the tools
> cumbersome and ackward. No good connection between ORCAD and the
> Xilinx tools. After one of our engineers spent the better part of 4
> months jumping between Xilinx and Orcad tech support, we bought the
> Altera tools and have had no need to call tech support. We have had no
> problems with locking pins, as a matter of fact, I have had no need to
> even look at the physical aspects of layout and such, just design and
> go! The LPM blocks (similar to XBLOX are FULLY configurable. All in
> all I'd have to say the switch from Xilinx has been the best move for
> our application. For what its worth. (these opinions are mine and not
> the fault of the company).

There was a time, not so long ago, when Orcad and Xilinx were
both "churning" their design libraries (Xilinx) and their
schematic capture tools (orcad).  The result was a messy
interface between the two.  Aaron's recounting stirs some
not-so-fond memories...

Things have improved dramatically.  Orcad now has complete
control and responsibility for everything up to and including
the generation of .XNF netlists.  All tech support is now
handled by orcad, not xilinx; and orcad does a good job
with support. I'm using the current version of Orcad Capture
(still only $995!), and I'm happy.

Altera *does* have a good toolset.  Why use orcad?  For me, I
very much appreciate the multi-vendor/technology support.
From the orcad front end, I can get to Altera, Actel, AMD,
Lattice, Xilinx, and Lucent/Orca; in some cases from the
same schematic set.  And the results are good.

Your mileage will vary.  Ask me about ViewLogic, the other
major player in PC-based FPGA design entry... but you'd better
stand back!

I've done work for orcad professionally, but I don't think
that has changed my opinions a whole lot.  You be the judge!

-- Bob Elkind

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5512
Subject: Fifth International Symposium on FPGAs
From: "Kevin D. Drucker" <kdrucker@hns.com>
Date: Fri, 21 Feb 1997 08:02:23 -0500
Links: << >>  << T >>  << A >>
Can any one suggest who/what the responsible organization for
publishing the papers presented at the recently concluded 5th
International Symposium on FPGAs and how I can legally obtain a copy?
-- 
-Kevin

Kevin D. Drucker        |  email: kdrucker@hns.com
Member Technical Staff, |  work:  (301) 601-4167  
Hardware Development    |  fax:   (301) 601-4275  
Hughes Network Systems  |
Article: 5513
Subject: Re: Q: Search Engines for Electronic Parts?
From: Peter Hazenberg <falco@pi.net>
Date: Fri, 21 Feb 1997 14:21:30 +0100
Links: << >>  << T >>  << A >>


Richard Schwarz wrote:
> 
> Take at look at the favorite links section at http://www.erols.com/aaps

The one i like the most : 
http://homepage.cistron.nl/~nctnico/databook.htm



Article: 5514
Subject: Re: replicating structure in MaxPlus
From: Rune Baeverrud <r@acte.no>
Date: Fri, 21 Feb 1997 15:36:52 +0100
Links: << >>  << T >>  << A >>
Graham Seaman wrote:

> I'm trying to implement a cellular structure using Altera's
> MaxPlus software; that is, I have a simple basic 'cell' of
> about 10 gates which I need to replicate many times across
> the FPGA (connections are mostly NEWS style; ie. to 4 nearest
> neighbours of each cell).
>  If I was doing this in VHDL, I'd just use the 'generate'
> statement in a nested for loop. But I don't have VHDL, only
> AHDL, and can't work out a good way of doing this. Or am
> I better off sticking to schematic entry (lots of cut-and-paste)?

This is how you do it in Altera AHDL:

PARAMETERS
(
  LENGTH = 13,
  WIDTH = 17
);

SUBDESIGN Cells
(
  sysclk, in[WIDTH-1..0]: INPUT;
  out[WIDTH-1..0]: OUTPUT; 
)

VARIABLE
  reg[LENGTH-1..0][WIDTH-1..0]  : DFF;

BEGIN
  reg[][].clk = sysclk;

  reg[0][] = in[];
  out[] = reg[LENGTH-1][];

  FOR i IN 0 to WIDTH-1 GENERATE
    FOR j IN 1 to LENGTH-1 GENERATE
      reg[j][i] = reg[j-1][i];
    END GENERATE;
  END GENERATE;

END;

This function is also made parameterized, so you can instantiate it the
same way as any LPM function!

Send 1 dollar to:
-- 
Rune Baeverrud <r@acte.no>           
Field Application Engineer                    |\      _,,,---,,_
ScandComp, ACTE NC Norway AS            ZZzz  /,`.-'`'    -.  ;-;;,_
P.O. Box 190, N-2020 Skedsmokorset, Norway   |,4-  ) )-,_..;\ (  `'-'
Tel: +47 6389 8969   Fax: +47 6389 8979     '---''(_/--'  `-'\_)
Article: 5515
Subject: Re: Xilinx or Altera?
From: "Austin Franklin" <#darkroom@ix.netcom.com#>
Date: 21 Feb 1997 15:37:59 GMT
Links: << >>  << T >>  << A >>
Paul,

Given what you say, then it is impossible to meet the PCI requirements for
a master in an Altera part?  The CEs are required in the IOB in case the
master disconnects, or stalls.

Well, then the only answer for a PCI interface is Xilinx...

Thanks for the info...

Austin


Paul S Secinaro <pss1@hopper.unh.edu> wrote in article
<5eilsq$7g@mozz.unh.edu>...
> "Austin Franklin" <#darkroom@ix.netcom.com#> writes:
> 
> >Since the topic of this thread was PCI designs, which is both complex
and
> >high speed, I would use the Xilinx tools because they give better contol
> >over the resource mapping, placement and utilization.  Also, the
internal
> >tri state bus of the Xilinx is excellent for PCI designs.  For a burst
> >master implementation, it is essential to have a CE in the IOB, and the
> >Xilinx does.  You can't meet PCI spec without it.  I don't know if the
> >Altera does or doesn't.
> 
> Are you kidding?  The Altera FLEX 8K doesn't even have a CE in the
> *CLB* (or logic cell in Altera jargain), let alone the IOB.  The
> problem I've had with the FLEX architecture is that it has
> fine-grained, simple logic cells, but doesn't seem to have the routing
> resources to deal with that (if your LC's are simple, you will need to
> use more of them, which means you'll need more interconnect
> resources).  They are reasonably fast and cheap, though.  FLEX 10K is
> a bit better to be better, but I haven't had the occasion to use any.
> Also, the Altera IOB's only have one flop, so you can't have a
> registered bidirectional I/O.  This dropped them from consideration in
> the last design I did (ended up using an Actel ACT3).
> 
> -Paul
> 
> -- 
> Paul Secinaro (pss1@christa.unh.edu)
> Synthetic Vision and Pattern Analysis Laboratory
> UNH Dept. of Electrical and Computer Engineering
> 
Article: 5516
Subject: Re: Fifth International Symposium on FPGAs
From: Mike Butts <mbutts@realizer.com>
Date: Fri, 21 Feb 1997 10:00:38 -0800
Links: << >>  << T >>  << A >>
Kevin D. Drucker wrote:
> 
> Can any one suggest who/what the responsible organization for
> publishing the papers presented at the recently concluded 5th
> International Symposium on FPGAs and how I can legally obtain a copy?


The FPGA '97 symposium was sponsored by the ACM SIGDA.  Copies will be available
from the ACM Order Dept., 1-800-342-6626 in the US, http://www.acm.org ,
email acmpubs@acm.org.  The ACM order number is 480970, and the ISBN is 
0-89791-801-0.  

The FPGA '97 web page is http://www.ece.nwu.edu/~hauck/fpga97 .  Since it
was so well attended, I heard they ran out of proceedings, so there may be
some delay in publishing more.

   --Mike
Article: 5517
Subject: Re: Xilinx or Altera?
From: Yost@fsd.com (Robert S. Yost)
Date: Fri, 21 Feb 1997 18:38:08 GMT
Links: << >>  << T >>  << A >>
One point that seems to be missed in the preceding messages is that
because the FPGA architecture (i.e Xilinx) is rich in flip-flops, they
are much more suitable for complex state machines.  You can really get
good performance by using One-Hot encoded machines in a Xilinx or any
other FPGA for that matter.  The CPLDs are more suited for decoding
functions, since their gate delay is small, and their number of
flip-flops is limited.

 I have done several designs that use both FPGAs and PLDs, where the
PLD decoded incoming signals and fed them into a big state machine in
an FPGA.  This has resulted in substantial improvement in performance
over using one type or the other

B. Yost

Article: 5518
Subject: help!newbie question!
From: Umesh Nair <nair@ee.tamu.edu>
Date: Fri, 21 Feb 1997 17:19:48 -0600
Links: << >>  << T >>  << A >>

hi!

i just wanted to know how multiple faults are tested in fpga blocks?
ignore my ignorance but i am just interested in doing a project at school

thanks for your time
umesh nair 

Article: 5519
Subject: Re: Reverse Engineering FPGAs
From: peter@xilinx.com (Peter Alfke)
Date: Fri, 21 Feb 1997 16:57:58 -0700
Links: << >>  << T >>  << A >>
In article <5eii65$399@pelican.cs.ucla.edu>, harding@pelican.cs.ucla.edu
(John A. Harding) wrote:

> Hello-
>  
> Are there any ways to prevent SRAM FPGAs from being
> reversed engineered. Or copied.

There's a difference between copying and reverse engineering.

Copying an FPGA with a readable bitstream is obviously trivial. Catch the
bitstream, buy the FPGA, and bingo.
Reverse engineering is far more difficult. It is almost impossible to
deduce the FPGA design from the bitstream. Yes, we know that hacking the
LUTs is easy, that's why you can get that information also directly from
Xilinx if you sign a Non-Disclosure-Agreement,- but the 90% of the bits
that control the interconnect are far less obvious and regular.
So you can assume that nobody will really understand the design when he
has intercepted the bitstream. Then you can call in the lawyers and sue
the bastard.

Your safest bet is to hide the bitstream by pulling out the SPROM or
disconnect the download device, and then keep the configuration alive with
a battery. XC3000 devices are best, since they can have very low standby
current, just a few microamps. This method is used by quite a number of
users who are concerned about design security. Not just the spooks, but
also manufacturers of set-top boxes that protect enormous amounts of
intellectual property ( that may be an overly generous name for some of
the movies ) with a cheap piece of hardware.

As with any other lock, you have to decide what the protection is worth.
Do you only want to keep honest people honest ( as bicycle-, ignition- and
house-keys do) or do you want to withstand a million-dollar weeklong
attack ? Have you read about the recent successful cracking of 40- and
48-bit codes in a matter of hours, given a fertile brain and a few hundred
workstations?

Peter Alfke, Xilinx Applications
Article: 5520
Subject: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
From: erikd@zip.com.au (Erik de Castro Lopo)
Date: 22 Feb 1997 02:17:06 GMT
Links: << >>  << T >>  << A >>
Peter Alfke (peter@xilinx.com) wrote:
: In article <330ffbe3.915085@149.174.214.137>, r.m.muench@ieee.org (Robert
: M. Muench) wrote:

: > Hi,
: > 
: > I'm interested in the set of functions which get mostly implemented
: > using FPGAs? And in any information where are the biggest problems
: > faced when using FPGAs.
: > 
: Robert, you did not get a meaningful response the first time. I suppose
: that's because the question is too general. FPGAs vary in complexity from
: 1000 gates to astronomical 100 k gates or more, depending on where
: marketing puts the upper limit.

I'd agree with what Robert has to say. FPGAs and CPLD are just means of 
replacing 74XX series logic and small PALs (ie Lattice 22v10).

One of my recent designs used one each of Xilinx XC3164 and XC3190 to 
implement a highly non standard graphics card for a specific product. 

The XC3164 contained some address decoding, a number of counters (some 
loadable, some bidirectional), a number of separate state machines, a 
fast 6 bit adder and a rather large multiplexer. 

The XC3190 contained nine 8bit parallel to serial converters, and 9 copies 
of a rather wide combinational function, some 8 into one multiplexers as 
well as two small state machines.

The design also called for an 32bit into 8bit bus sizer. Unfortunately, the
bus sizer could not acheive the speed requirements if placed in the Xilinx 
parts so it was instead placed in a Lattice ispLSI 2064 CPLD device.

Hope this helps,
Erik.
Article: 5521
Subject: Re: Xilinx or Altera?
From: Bill Harris <wmharris@cisco.com>
Date: Sat, 22 Feb 1997 00:32:23 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> In article <01bc1d01$a2930c50$550886c2@jan>, "Jan Humme"
> <humme@euronet.nl> wrote:
> 
> > => is there a good comparison (FAQ?) for Xilinx and Altera (strong and weak
> > points) anywhere on the Web?
> >
> This looks like a wide-ranging question, and there will be lots of
> opinions and biases.
> 
> The first big choice is between CPLDs and FPGAs.
> CPLDs are smaller and simpler. Their software is easier to understand, and
> compile times are shorter. But power consumption is relatively high, and
> the number of flip-flops is quite limited, max a few hundred. On-chip
> delays can be quite short, and it is relatively easy to predict the
> performance of even a complex design. With their wide fan-in, these
> devices implement encoded state machines nicely.
> Besides limited complexity and high power consumption, many CPLDs have one
> more drawback: they cannot be programmed on the board, which means
> additional handling, etc. Some CPLDs can be programmed only once.
> There is a strong trend to In-System-Programming, which eliminates these
> drawbacks. Lattice was first, Xilinx now offers the very attractive XC9500
> family which is in-system programmable, and can cope with design changes
> while maintaining a given pin assignment ( pc-board layout ). This is
> called "Pin-locking capability", an important, but often overlooked
> necessity.
> Altera is the biggest supplier of CPLDs, but not necessarily of the most
> modern and most attractive versions. 

If they are so unattractive, why does Xilinx's 9500 stuff look so much like them architecturally?  The first time 
I saw a 9500 data sheet I thought I was looking at a 7K Altera part.  The macrocell is virtually identical.  You 
make a big deal about "Pin-locking capability", and Altera 7K parts definitely had problems with that a few years 
ago. However, their software has vastly improved since then and pin-locking issues on their 7K parts are virtually 
non-existant in my experience.  The partially populated interconnect mux that they use results in smaller die 
sizes than Xilinx is ever going to get with the 9500's fully populated structure, not to mention the speed 
advantage that it offers.  If you want to see an unattractive, unmodern EPLD family, look no farther than those 
PlusLogic throwbacks that Xilinx has been trying to hawk for the past couple of years.

> Lattice pioneered
> In-system-Programming, but everybody has jumped on that bandwagon.
> 
> Most FPGAs use Latches to customize ( configure ) the device. Such FPGAs
> cover a wide range in complexity, from 1000 gates to 100,000 gates, and
> rapidly increasing to even loftier heights. The devices are configured on
> the board ( no programming equipment, no marking, no lead-bending
> insertions ) and can be reconfigured an unlimited number of times, which
> offers exciting possibilities in "reconfigurable logic" or reconfigurable
> computing". Logic functions are implemented in 4-input look-up tables,
> which is generally ackknowledged to be the most efficient method for this
> technology.
> The devices are flip-flop rich, having one flip-flop for every 10 or 12
> claimed gates. Power consumption is low and entirely dynamic.
> The software is more complex and takes longer to compile, and the user
> must pay attention to the delays in the interconnect structure.
> Xilinx is the pioneer and the biggest player, AT&T competes in this field,
> and Altera has two families ( 8k and 10k ) that also use latches and
> look-up tables, but use a more rigid interconnect structure, which has
> both advantages and disadvantages compared to the conventional
> hierarchically segmented interconnct structure. For reasons too complex to
> explain here, Altera does not call their 8k and 10k devices "FPGAs".

Its not complex at all.  Altera defines an FPGA as a device which has a segmented interconnect structure which is 
pieced together to make connections, ala Xilinx, AT&T, Actel, et al.  They define a CPLD as having a continuous 
(relatively anyway) interconnect structure similar to that found in EPLDs.  Delays are much easier to predict 
since there are fewer levels of interconnect than in a segmented structure.

> 
> Actel and Quicklogic offer FPGAs where the configuration is implemnted
> with antifuses, which makes these devices non-volatile, but
> one-time-programmable.

Hummmmm, I seem to remember something about a Xilinx 8100 anti-fuse family..........

> 
> This is about as unbiased an overview that you will get from one of the
> involved parties.
> After this you have to cope with the marketing and applications messages
> of each manufactureer. The web is a gold mine in this respect. But be
> aware that everybody always puts his best foot forward. And here in this
> newsgroup we shy away from blatant competitor-bashing.

Define "blatant"....

Bill Harris
Cisco Systems

"My opinions are my own and do not necessarily reflect those of my employer"
Article: 5522
Subject: Re: Xilinx or Altera?
From: Bill Harris <wmharris@cisco.com>
Date: Sat, 22 Feb 1997 02:00:58 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> In article <01bc1d85$40de5620$a20886c2@jan>, "Jan Humme"
> <humme@euronet.nl> wrote:
> 
> > We believe that both Altera and Xilinx are good products. In order to make
> > a choice for the one that fits us best, I would like to hear more from
> > people that have experiences with one or both.
> >
> Let me see whether I can make a case here for Xilinx without losing my
> reputation.

Oh, I wouldn't worry about that...

<snip>

> 
> Xilinx power consumption is lower, everything else being equal. This is
> the result of the different interconnect structure, and no marketing
> posturing can defy the laws of physics. ( The Altera message that the "sum
> of internal power is proportional to the percentage of blocks toggling at
> the clock rate" is wrong. It's tough to respect people who publish this
> kind of nonsense ).

Lets talk about nonsense.  Lets look at the Xilinx app note located at

http://www.xilinx.com/partinfo/3volt.pdf

Lets see, on page 6-3 there is a long drawn out explanation of how its okay to drive devices operating at 3.3 volts 
with a Xilinx 4000E part operating at 5.0 volts.  Lots of really precise language like "nominal", "typical", "track 
reasonably".  How about: "A worst-case analysis of the interface might assume the (unrealistic) condition...".  I 
really like the sentence that says: "Under these conditions, the interface violates the conventional 
specification...", yet the note goes on in great detail about how it really OK anyway.  If its really OK, then why 
does Xilinx themselves publish absolute maximum ratings for some of their own devices that are the same as the 
"conventional specification" (3000L for example)?  This is really great: "Although this input condition is not 
covered by the conventional specification, it does not cause any harm and does not affect reliability."  That jewel 
is followed shortly by a warning about the possibility of latch-up, but not to worry, everything will be OK.

If Xilinx thinks that it is OK to drive a 3.3 volt input from from a 4KE device operating off a 5.0 volt supply, 
then why don't they guarantee a maximum Voh for the 4KE?

Tell me Mr. Alfke, would you put your family on an airplane whose fight control systems were designed using these 
Xilinx recommendations?

Your right, it really is tough to respect people who publish this kind of nonsense.

BTW, are you saying that power consumption in CMOS logic is NOT proportional to the switching frequency of the 
circuit?

Bill Harris
Cisco Systems

"My opinions are my own and do not necessarily reflect those of my employer".
Article: 5523
Subject: Re: Q: Anyone bought APS-X84 FPGA board?
From: Mark Garaway <mgaraway@deltanet.com>
Date: Fri, 21 Feb 1997 23:33:15 -0800
Links: << >>  << T >>  << A >>
dnk@io.com wrote:
> 
> More accurately, has anyone ordered and received the board + software?
> 
>         http://www.erols.com/aaps/X84price.htm
> 
> I've ordered the board + Xilink software almost 5 weeks ago and have
> yet to see anything.  (Apparently they are waiting on the Xilink
> software.)  Maybe I've been spoiled by mail order companies like
> MacMall and MicroWarehouse, but 5 weeks seems like an eon (is this
> typical of FPGA related companies?).  At least I'd expected the board
> shipped right away, and the Xilink software delivered as soon as they
> got it.  At least there are some pluses: they haven't charged my credit
> card yet, they are prompt in replying to email and are updating their
> web pages....
> 
> Thanks for your time,
> 
> Danny Kumamoto

I have just received my order from APS for the APS-X84-FBV which is the
X84 board and the XILINX Foundation Base System.  The order was placed
on 1/27/97 and delayed by the XILINX software.  I found Richard to be
responsive to my e-mail and accurate on the shipping date when he got
the XILINX stuff from a distriutor.  He also offered to do a partial
shippment to me of the board before he got the software.  The card looks
fine (haven't fired it up yet) and the software was in a sealed original
XILINX box.  It took a little while but APS delivered what I ordered.

Regards,
Mark Garaway
mgaraway@deltanet.com
Article: 5524
Subject: Re: Xilinx or Altera?
From: szamos@pacifier.com (szamos)
Date: 22 Feb 1997 08:18:30 GMT
Links: << >>  << T >>  << A >>
Austin Franklin (#darkroom@ix.netcom.com#) wrote:
: 
: The Altera design environment is not any industry standard.  They have
: their own schematic capture and HDL.  To me, this means the engineer has to
: learn 'yet another proprietary schematic capture and HDL' to get the job
: done. 

While they do have their own HDL, Max+Plus II also takes .edf which 
can generated from Verilog, VHDL, etc.



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