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Messages from 5725

Article: 5725
Subject: Re: Xilinx FPGA & SIMMs
From: peter@xilinx.com (Peter Alfke)
Date: Mon, 10 Mar 1997 18:43:41 -0700
Links: << >>  << T >>  << A >>
In article <33245D4C.2811@ids.net>, Ray Andraka <randraka@ids.net> wrote:

there was an app note in the 1994 Xilinx data book on building a
> deep fifo using DRAM.  Perhaps you can use that for some hints.  I
> beleive that design used an LFSR for the address counters and a cute
> shift scheme to get the row and column addresses.
> 
I was the one who came up with this addressing trick in 1989, but it
really works only for FIFOs where the binary address sequence is
irrelevant, as long as write and read port follow the same sequence. 
Memories of a distant past...

The additional question is refresh of the DRAMs. If the refresh
requirement is anything like it was in the olden days, you need to at
least control it, at worst even apply part of the refresh address.
That again chews up a few CLBs. But the whole design is not very complicated.

Peter Alfke, Xilinx Applications
Article: 5726
Subject: Re: Galileo... Leonardo... Renoir... ?
From: thomasr@xtek.com (Thomas Rock)
Date: Mon, 10 Mar 1997 19:58:51 -0600
Links: << >>  << T >>  << A >>
In article <qDednAArrEJzMA5V@vizef.demon.co.uk>, steveb@vizef.demon.co.uk 
says...
> In article <5g176i$694$1@info1.fnal.gov>, Don Husby <husby@fnal.gov>
> writes
> >Renoir Support  renoir@em-wv03.wv.mentorg.com wrote:
> >> Introducing Renoir for VHDL/Verilog Graphical Entry

Starting to sound like the "Teenage Mutant Ninja Tools"....
Article: 5727
Subject: Re: Timing simulator for Warp 4.1 that works under Win NT 4.0
From: "Henry Thomas" <dont_spam@me.thanks>
Date: 11 Mar 1997 01:59:55 GMT
Links: << >>  << T >>  << A >>
Based on the most common reccomendation I have decided to try out
ModelTech's V-System for Windows NT, which should arrive sometime this
week. Thanks for your input and replies to my post.

BTW: I was actually using the View Logic tool chain before trying out Warp
4.1, but since they ported it to windows it has just got sucessively worse.
I didn't even bother upgrading...

-- 
        - h 

<< return address is bogus, getting spammed too much - henry at odo dot com
>>


Article: 5728
Subject: Re: Reverse Engineering FPGAs
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Tue, 11 Mar 1997 04:43:20 GMT
Links: << >>  << T >>  << A >>
In article <331DD299.7A28@emf.net>, Brad Taylor  <blt@emf.net> wrote:
>> Does this realization mean that Xilinx will be releasing documentation on
>> the contents of its bit streams? ... No, I'm not seriously expecting it...
>
>I'm just curious. What would you do with it? (the bitsream information)

Freely-redistributable programming software.  Distributed free, in source
form, portable to any POSIX environment, with no copy protection.  At least
for starters, something very simple in which the user has to do almost all
the work -- a tool for people who can spare time more than cash, and are
willing to do placing and routing themselves to save money.

It's not like I don't have *enough* projects to fill my copious spare time
already, but this one would be very much worth doing.  Alas, it does require
not just access to the bitstream info, but public release of same.
-- 
Committees do harm merely by existing.             |       Henry Spencer
                           -- Freeman Dyson        |   henry@zoo.toronto.edu
Article: 5729
Subject: Re: Reverse Engineering FPGAs
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Tue, 11 Mar 1997 04:55:01 GMT
Links: << >>  << T >>  << A >>
In article <33208CDD.4563@xilinx.com>,
Eric Dellinger  <ericd@xilinx.com> wrote:
>Why do you want the bitstream format? Do you really 
>need the bitstream itself, or can you settle for 
>inexpensive or free means of controlling the 
>contents of the bitstream?  Is the real issue
>the cost of tools, or do you need quicker
>ways than guided ppr to munge the bitstream?

Six of one and half a dozen of the other.  The cost of the tools could
certainly stand to be reduced.  However, I'm also interested in things
that want to do dynamic reconfiguration, where *my* software has to be
able to generate the bitstream -- selecting among a handful of pre-built
possibilities, or telling the user to carry a floppy over to an MSDOS
machine, wait two hours, and carry it back, is not good enough.  (This
is not an Official Project of a Big Institution, so the usual "we can
negotiate a special deal, provided your name is Thomas Edison" is no help.)
-- 
Committees do harm merely by existing.             |       Henry Spencer
                           -- Freeman Dyson        |   henry@zoo.toronto.edu
Article: 5730
Subject: Re: Introducing Renoir
From: Uwe Bonnes <bon@hertz.ikp.physik.th-darmstadt.de>
Date: 11 Mar 1997 08:32:59 GMT
Links: << >>  << T >>  << A >>
In comp.lang.verilog Renoir Support <renoir@em-wv03.wv.mentorg.com> wrote:

: Introducing Renoir for VHDL/Verilog Graphical Entry

: Full information on a brand new HDL graphical entry tool can be found
: at:

:  http://www.renoir.com/

: You can also download an evaluation copy for Windows, SUN and HP
: platforms.

Will there be a version for Linux too?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.th-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 5731
Subject: Re: Introducing Renoir
From: Nick Weavers <weav@apollo.havant.ibm.com>
Date: Tue, 11 Mar 1997 10:22:29 +0000
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:
> 
> In comp.lang.verilog Renoir Support <renoir@em-wv03.wv.mentorg.com> wrote:
> 
> : Introducing Renoir for VHDL/Verilog Graphical Entry
> 
> : Full information on a brand new HDL graphical entry tool can be found
> : at:
> 
> :  http://www.renoir.com/
> 
> : You can also download an evaluation copy for Windows, SUN and HP
> : platforms.
> 
> Will there be a version for Linux too?
> 

And AIX 4.1 perhaps...?

-- 
Nick Weavers, IBM SSD, Havant, PO9 1SA, UK. e-mail: weav@hursley.ibm.com
Tel: 011-44-(0)1705-486363 ext 5121  Fax: 011-44-(0)1705-499278
Article: 5732
Subject: Re: Instatiation of Xilinx Primitives in VHDL?
From: blaquiere.yves@uqam.ca (Yves Blaquiere)
Date: 11 Mar 1997 13:26:20 GMT
Links: << >>  << T >>  << A >>

I read your replies about instantiation and maybe you have an answer
to my problem. I know that a hdl description in Synopsys can
instantiate (for synthesis) XILINX primitives and designs generated
with xbloxgen or memgen, .

My question is:

How can these designs, generated with xbloxgen and memgen, be
simulated in Synopsys. I think that instantiation is useless if their
behavior cannot be simulated before place and route.

Article: 5733
Subject: viewoffice compatibility - dumb question
From: "Rich K." <rich.katz@gsfc.nasa.gov>
Date: 11 Mar 1997 15:16:38 GMT
Links: << >>  << T >>  << A >>
hi,

i have upgraded a bunch of viewlogic 'seats' to the viewoffice stuff and
got them all at the exact same revision.  seems like a good idea.  now,
some seats were upgraded from workview plus and others from pro series. 
this REALLY seems like a good idea since at one time i was using three
different user interfaces during the 'transition' phase and while waiting
months and months for s/w and correct license files.

anyways,

now that they are all the same,

i am having trouble (like can't do it) reading files on 'heritage' pro
series seats from former workview plus seats, although they are just simple
schematics that i can easily create on either computer.  and going from the
former pro series to the former workview plus seems to work just fine.

suggestions? comments?

thanks for any help,

rk
Article: 5734
Subject: Re: Introducing Renoir
From: Rudolf Simbuerger <rudolf.simbuerger@pn.siemens.de>
Date: Tue, 11 Mar 1997 08:32:18 -0800
Links: << >>  << T >>  << A >>
suzanne M southworth wrote:
> 
> Jim,
> 
> It's a tool developed by Mentor Graphics.
                        ^^^^^^^^^^^^^^^^^^
                        by Exemplar


Rudi
Article: 5735
Subject: How to tell number of or name of Viewlogic users on PC network under site license?
From: Daniel Alley <dana@xetron.com>
Date: Tue, 11 Mar 1997 16:43:28 GMT
Links: << >>  << T >>  << A >>
Our office has a limited number of licensed PC/Windows viewlogic
'seats', and we often have people being locked out while other users are
not actively using the tools (but have it up on their PC).   My question
is how to have the VL software on our server pass some information down
while locking out the extra users, specifically so someone can call
other users to see if they can close the VL tool down if not actively in
use...  Currently, we all have to phone around the building to search
for the available 'seats'.

Thanks in advance,  Dan Alley  Xetron Corporation
Article: 5736
Subject: Re: Xilinx FPGA & SIMMs
From: "John L. Smith" <jsmith@univision.com>
Date: Tue, 11 Mar 1997 09:59:50 -0800
Links: << >>  << T >>  << A >>
Christos Dimitrakakis wrote:
> 
> I am considering the usage of a Xilinx FPGA as a DSP chip that also
> controls memory access to a single SIMM. The FPGA will be the only
> device accessing the memory.
> Are there any app notes/example designs on using the Xilinx as memory
> decoders?
> Furthermore, I have no knowledge of SIMM operation, so if anyone could
> fill me in on that I would be very grateful :)
> --
> Christos Dimitrakakis
> ---------------------
> mailto:mbge4cd1@fs4.eng.man.ac.uk
> mailto:mbge4cd1@afs.mcc.ac.uk
> http://www.man.ac.uk/~mbge4cd1

SIMMs typically have timing spec's identical to the parts with which
they're built, which are generally DRAMs, although SRAM SIMMs are also
available. If you are using DRAM SIMMs and doing DSP inside the Xilinx,
you may find that your throughput is limited by the high access penalty
attached to the RAS (Row Address Strobe) and RAS precharge sections of
the memory cycle. To overcome this, pay close attention to data formats
in memory, and try to keep your algorithms structured so that the DRAMs
may be operated in Fast Page Mode most of the time. If the data is
structured in blocks spread across different row of memory, Fifo's
can be built inside the Xilinx to buffer data between memory and your
processing engine. 

-- 
John L. Smith
Univision Technologies, Inc.
6 Fortune Drive
Billerica, MA 01821-3917
jsmith@univision.com
Article: 5737
Subject: COURSE: High Level Design Using VHDL, March 31 - April 4
From: lindab@qualis.qualis.com (Linda Boyd)
Date: 11 Mar 1997 18:38:43 GMT
Links: << >>  << T >>  << A >>

                            A N N O U N C E

Qualis Design Corporation is offering another session of our popular course
"High Level Design Using VHDL" at our Beaverton, Oregon, Training Center.

This course presents a comprehensive introduction to the VHDL
language while teaching you how to approach complex design tasks using
High Level Design methods.  Through our advanced presentation methods,
we teach cutting-edge knowledge in a way that sticks -- graduates of the
course are immediately ready to tackle large scale VHDL-based designs
including ASICs and FPGAs.

For additional information about the material covered in this leading-edge
course, see the course description below.

This course can also be held at your facilities in a private, one-on-one
setting -- contact us for more information.

Schedule
--------
The March 1997 schedule for this class follows:

       Course Title                        Course Date       Status
       -------------------------------------------------------------------
       High Level Design Using VHDL:       Mar 31 - Apr 4    Open


The Qualis Difference
---------------------
We know what it's like to work under the pressure of aggressive schedules and
immense technical challenges.  We believe that High Level Design methods
and technology, such as HDL-based verification and synthesis, are the key
to tackling those challenges and conquering today's design problems.
Our courses can make a real difference in your day-to-day work life
by showing you the high leverage points of VHDL and High Level Design.
Here's how we do it:

 -- The Qualis "Best In Class" Instructor Team draws upon the absolute best
    VHDL and Verilog consultants in the industry -- our people!  Your
    instructor regularly tackles 500,000+ gate ASICs, and is ready to
    share his in-depth knowledge with you.  Synthesis, verification,
    design methodology -- it's all there.  You won't find instructors
    of this caliber anywhere else.

 -- Our courses are intense, hands-on events using the latest EDA tools
    and hardware.  Everything you need to learn quickly and efficiently is
    provided -- you supply the brain, we'll supply everything else.

 -- Our courses are like no other in the EDA industry.  Engineers and
    Managers who attend our courses will learn what's important and why, and
    where to focus their time and resources for maximum leverage from HDLs
    and design tools.  And, unlike other vendor courses, our courses are
    *dynamic* -- we constantly update our material with the latest in
    High Level Design techniques and information, so you're assured of
    learning the latest in the field.

--  Our courses are respected in the industry.  We have taught our
    High Level Design courses to many Fortune 500 companies and
    hundreds of Engineers and Managers.  Our student references attest
    to the outstanding quality and real-world usefulness of our classes.
    Just ask and we'll prove it.

About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of Elite Consulting and Training
Services.  The company provides services to leading-edge
high technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, and Northern Telecom.  Qualis' corporate
headquarters are located in Beaverton, Oregon.

Don't miss this opportunity to learn the latest in High Level Design
from the best in the industry.  For course syllabi and registration
information, contact us at:

                        Linda Boyd, Training Registrar
                           Qualis Design Corporation
                       8705 SW Nimbus Avenue, Suite 118
                          Beaverton, Oregon 97008 USA

                            Phone: +1-503-644-9700
                             FAX: +1-503-643-1583
                          mailto:training@qualis.com

Brief Course Description
--------------------------

                    High Level Design Using VHDL

                          Course Overview

        Copyright (c) 1995, 1996, 1997 Qualis Design Corporation

"High Level Design Using VHDL" is a fast paced, five-day hands-on,
multimedia course designed to make class participants immediately productive
in a VHDL-based design environment using state-of-the-art simulation and
synthesis tools.

After an introduction to VHDL, the course deviates from the traditional
bottom-up, gates-to-behavioral modeling presentation of other VHDL courses
and reverses the flow, teaching top-down design practices, with early
special emphasis on coding guidelines, efficient testbench generation and
advanced design verification techniques. These skills are reinforced
throughout the week while teaching VHDL from a top-down perspective.

The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences.  All students
complete the main part of the lab and an optional part is for students
who finish early and want to learn additional material.  This lab structure
caters to all student skill levels and provides excellent opportunities
to expand one's knowledge of VHDL simulation and modeling techniques.

Each day of class includes interactive lectures with four or five lab
sessions.  Students will have access to individual Sun Sparcstations,
the Synopsys VSS and Model Technology V-System / Workstation simulation
environments, and the Synopsys DC Expert synthesis environment for use
during the laboratory sessions.  The instructor presents the material
using a projection system that allows 30% more material to be presented
in a given amount of time with vivid, interest-grabbing color slides.

Full Course Syllabus Available
------------------------------
A full course syllabus listing all topics covered in this course
is available.  Contact us for more information.

------------------------------------------------------------------------------

                           Qualis Design Corporation
                       8705 SW Nimbus Avenue, Suite 118
                          Beaverton, Oregon 97008 USA

                            Phone: +1-503-644-9700
                             FAX: +1-503-643-1583
                          mailto:training@qualis.com

"DC Expert" is a trademark of Synopsys, Inc.
"Verilog" is a registered trademark of Cadence Design Systems, Inc.

Copyright (c) 1995, 1996, 1997, Qualis Design Corporation.  All Rights Reserved.

Article: 5738
Subject: Re: Reverse Engineering FPGAs
From: Eric Dellinger <ericd@xilinx.com>
Date: Tue, 11 Mar 1997 11:37:36 -0800
Links: << >>  << T >>  << A >>
szamos wrote:
 
< Eric Dellinger (ericd@xilinx.com) wrote:
< :
< : [I had written a lengthy posting espousing my
< : personal philosophy that Xilinx should provide
< : freeware for programming the parts,
< 
< Do you mean the software just to download the config data into
< the FPGA's, or you mean the whole development system?

The former, at the very least.  Preferably the latter.

==eric
Article: 5739
Subject: Re: Reverse Engineering FPGAs
From: wen-king@myri.com (Wen-King Su)
Date: 11 Mar 1997 11:44:27 -0800
Links: << >>  << T >>  << A >>
In a previous article Henry Spencer <henry@zoo.toronto.edu> writes:
:
;In article <331DD299.7A28@emf.net>, Brad Taylor  <blt@emf.net> wrote:
:>> Does this realization mean that Xilinx will be releasing documentation on
;>> the contents of its bit streams? ... No, I'm not seriously expecting it...
:>
;>I'm just curious. What would you do with it? (the bitsream information)
:
;Freely-redistributable programming software.  Distributed free, in source
:form, portable to any POSIX environment, with no copy protection.  At least
;for starters, something very simple in which the user has to do almost all
:the work -- a tool for people who can spare time more than cash, and are
;willing to do placing and routing themselves to save money.
:
;It's not like I don't have *enough* projects to fill my copious spare time
:already, but this one would be very much worth doing.  Alas, it does require
;not just access to the bitstream info, but public release of same.

One question is does the biggest customers of Xilinx want to be challenged
in their market by a swarm of little guys armed with free or affordable
softwares?  It is all market driven, even though at times the strategy
may seem counter-intuitive to some of us.  Another example -- why isn't
PCI spec designed so to make it easy to build a high-performance interface
out of FPGA (eg, IRDY and TRDY should have been made to mean readiness
to transfer data in the NEXT clock cycle).  Could it be that the consortium
members want no challenges from those who are not big enough to do hardwired
gate arrays? 
Article: 5740
Subject: Re: ACTEL RAM BASED FPGAs
From: Jaap Mol <jhmol@a1.nl>
Date: Tue, 11 Mar 1997 21:01:13 +0100
Links: << >>  << T >>  << A >>
Richard Schwarz wrote:
> 
> Anybody had any experience with the ACTEL RAM BASED FPGAs? 

I have heard that there are several beta customers in the US, testing
this new technology and
its new design software, but I believer no parts are commercially
available yet. 
Please refer to the ACTEL homepage (http://www.actel.com) for the latest
news.

> I think this is a smart move on their part but haven't heard much about them.

I fully agree with you. I believe this technology will be the first
SRAM-based technology on the marktet
having a fine-grained (synthesis-friendly!) architecture. I'm very
curious what ACTEL comes up with
within the next few months.

P.S. I am NOT an ACTEL employee, but our company has been using ACTEL
anti-fuse technology, as well
as XILINX and ALTERA SRAM-based technology. 

Best regards,


Jaap Mol

> 
> Richard Schwarz
Article: 5741
Subject: Re: Introducing Renoir
From: Paolo Spazzini <paolo_spazzini@mentorg.com>
Date: Tue, 11 Mar 1997 13:31:54 -0800
Links: << >>  << T >>  << A >>
Uwe Bonnes wrote:

  In comp.lang.verilog Renoir Support <renoir@em-wv03.wv.mentorg.com>
  wrote:

  : Introducing Renoir for VHDL/Verilog Graphical Entry

  : Full information on a brand new HDL graphical entry tool can be
  found
  : at:

  :  http://www.renoir.com/

  : You can also download an evaluation copy for Windows, SUN and HP
  : platforms.

  Will there be a version for Linux too?

  --
  Uwe Bonnes                bon@elektron.ikp.physik.th-darmstadt.de

  Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
  --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

 At the moment there are not plan for a Linux version of Renoir.
thanks

Article: 5742
Subject: Fatal exception under Win95 & XACT v6.0.1
From: shantanu@curie.ece.neu.edu (Shantanu Tarafdar)
Date: 11 Mar 1997 21:35:45 GMT
Links: << >>  << T >>  << A >>
Hi,

I was wondering if anyone has had this problem with XACT under
Windows 95. We get a system error and have to reboot the PC.
We are running on a Dell Pentium 133 system with 32MB of memory.
The version of XACT is v6.0.1.

This happens when we try to "implement" from an XNF file.
The error message:

Fatal Exception 0D occurred at 00a700000c9e

And then the PC hangs. Has anyone seen this before or offer any
suggestions?

Please reply to shantanu@ece.neu.edu. 

Thanks!
Shantanu...


Article: 5743
Subject: VHDL & ABEL synthesis tools on 95/NT
From: "Todd A. Kline" <Todd.Kline@gsnetworks.gensig.com>
Date: Tue, 11 Mar 1997 13:45:45 -0800
Links: << >>  << T >>  << A >>
We are currently using ViewSynthesis and ViewPLD for FPGA and PLD/CPLD
designs.  
We find ViewSynthesis optimizes the Xilinx FPGAs very poorly and ViewPLD
is buggy, unstable, and poorly supported.  I would be very grateful for
any feedback on the following products:

1) Exemplar

2) Synario

3) Minc (PLD/CPLD) + Synplicity (FPGA).

I have done some benchmarking on Synplicity and found that it optimized
better then ViewSynthesis, but I'd prefer a unified VHDL/ABEL solution.  

I also must say that I have a GREAT prejudice against Synario.  I have
found DataIO support to be on a par with VIEWlogic, that is to say
horrible.  I also have doubts about DataIO's commitment to EDA
products.  Does any one remember FutureNet/Gates?  

For these reasons I find my self leaning to Exemplar but only because I
know next to nothing about them.  Ignorance is, after all, bliss.  

Your feedback is eagerly anticipated.

Todd
Article: 5744
Subject: Re: ACTEL RAM BASED FPGAs
From: Ray Andraka <randraka@ids.net>
Date: Tue, 11 Mar 1997 17:41:49 -0500
Links: << >>  << T >>  << A >>
Jaap Mol wrote:
> I fully agree with you. I believe this technology will be the first
> SRAM-based technology on the marktet
> having a fine-grained (synthesis-friendly!) architecture. I'm very
> curious what ACTEL comes up with
> within the next few months.

Atmel has had a fine-grained SRAM based FPGA on the market since the
early '90s.  The AT6005 has 3136 cells.  Each is basically a half adder
with a register on the sum output and a couple of and gates and muxes to
allow most 2 and a few 3 input functions. 

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 5745
Subject: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 11 Mar 1997 16:54:56 -0700
Links: << >>  << T >>  << A >>
Stuart Summerville wrote:

> I am trying to fit a current design into an XC5204-160PQ.  I am
> curious as to how much other designers utilise the I/O capabilities of
> pins used in the configuration sequence of such devices.
> 

> so far I have managed to restrict usage of I/O pins to dedicated I/O
> pins, but I'm not really sure how far I should go in also using the
> multi-purpose ones.
> 
> Thanks for any advice.

You can be sure that the guys who designed the chip had your problem in
mind. Nobody wants to waste pins. In the XC2000 and XC3000 the PROGRAM
and DONE function were even combined in one pin, which may not have been
so smart but it demonstrates the concern.
So, we care. And we describe the pin function very carefully. Please
read the appropriate page, in your case it is 4-197. Which pins are
critical depends on the configuration mode, with Master Serial being the
least restrictive. 
If you use the mode pins as outputs during the normal operation, then
you can easily, for configuration, establish the Low level with a
pull-down resistor ( make it 2.7 kilohm to get a nice low voltage )
Aside from a little wasted current, these resistors cause no harm during
operation.

HDC and LDC may of course not be driven during configuration ( to be
precise: they may not be driven the wrong way ), so it makes sense to
use them as outputs later on.
RDY/BUSY, RCLK,CS,WS,RS,the 18As and the parallel data inputs are all
3-stated with weak pull-up, like all the other I/Os.
DOUT is active and DIN is being driven during configuration, so they are
best used as outputs during system operation.
These recommendations assume that you don't use external multiplexers or
Quickswitch devices. With them, full flexibility is restored.

So, it is not impossible to use these pins, but it is advisable to read
the verbal pin desciptions. They are carefully written and do not try to
hide anything. If they do confuse you, I did something wrong, give me a
holler, and I will fix it. I am the resident wordsmith :-)

Peter Alfke, Xilinx Applications
Article: 5746
Subject: Re: Fatal exception under Win95 & XACT v6.0.1
From: "Paul Taylor" <p.taylor@ukonline.co.uk>
Date: 12 Mar 1997 00:22:23 GMT
Links: << >>  << T >>  << A >>
As far as I am aware, XACT 6.0.1 doesn`t work in windows 95.
eg Prom File Formatter allows you to go up directories but not back down 
etc.
We have two "Lab PC`s" at work which are still Windows 3.11 in order to run
XACT.
I have heard that the Win95 Xilinx software is currently being beta tested
- but our maintenance just expired.  :-(

Paul.



Shantanu Tarafdar <shantanu@curie.ece.neu.edu> wrote in article
<slrn5ibk05.lhv.shantanu@rosalind.ece.neu.edu>...
> Hi,
> 
> I was wondering if anyone has had this problem with XACT under
> Windows 95. We get a system error and have to reboot the PC.
> We are running on a Dell Pentium 133 system with 32MB of memory.
> The version of XACT is v6.0.1.
> 
> This happens when we try to "implement" from an XNF file.
> The error message:
> 
> Fatal Exception 0D occurred at 00a700000c9e
> 
> And then the PC hangs. Has anyone seen this before or offer any
> suggestions?
> 
> Please reply to shantanu@ece.neu.edu. 
> 
> Thanks!
> Shantanu...
> 
> 
> 
Article: 5747
Subject: Re: Galileo... Leonardo... Renoir... ?
From: husby@fnal.gov (Don Husby)
Date: 12 Mar 1997 14:09:28 GMT
Links: << >>  << T >>  << A >>
Steve Bird  steveb@vizef.demon.co.uk wrote:
> I guess you didn't like it...

I haven't tried it.
This was supposed to be humor.  Here's the smiley :)

For the humor impaired:
Galileo and Leonardo are products from Exemplar logic
Renoir is a is a product of Mentor Graphics
This was not intended to cast aspersions on any these products.

Here's some more smiley's :) :)


Article: 5748
Subject: Re: VHDL & ABEL synthesis tools on 95/NT
From: Richard Schwarz <aaps@erols.com>
Date: Wed, 12 Mar 1997 10:34:19 -0500
Links: << >>  << T >>  << A >>
Todd A. Kline wrote:

  We are currently using ViewSynthesis and ViewPLD for FPGA and
  PLD/CPLD
  designs.
  We find ViewSynthesis optimizes the Xilinx FPGAs very poorly and
  ViewPLD
  is buggy, unstable, and poorly supported.  I would be very grateful
  for
  any feedback on the following products:

  1) Exemplar

  2) Synario

  3) Minc (PLD/CPLD) + Synplicity (FPGA).

  I have done some benchmarking on Synplicity and found that it
  optimized
  better then ViewSynthesis, but I'd prefer a unified VHDL/ABEL
  solution.

  I also must say that I have a GREAT prejudice against Synario.  I
  have
  found DataIO support to be on a par with VIEWlogic, that is to say
  horrible.  I also have doubts about DataIO's commitment to EDA
  products.  Does any one remember FutureNet/Gates?

  For these reasons I find my self leaning to Exemplar but only
  because I
  know next to nothing about them.  Ignorance is, after all, bliss.

  Your feedback is eagerly anticipated.

  Todd

 Todd,

I have used all the synthesis tools you have described. I also sell the
the Foundation tool set for XILINX. The tool kits are priced very
reasonably and come with VHDL and SCHEMATIC and ABEL synthesis, and an
ISA FPGA test board and VHDL and C code examples. see:
http://www.erols.com/aaps
We are advertising in the Marketplace of Personnal Engineering &
Instrumentation with a list of current prices.

Exemplar is a good VHDL tool. I have Galileo and use it for many of my
non XILINX projects. The support people are very good. I have had less
experience with Synplicity --but have used it-- they seemed very good
too. Exemplar had some advantages in certain areas while Synplicity had
advantages for others. They both were well supported.

Please feel free to ask me specifics about any of the above products

Richard Schwarz

Pres. APS

Article: 5749
Subject: Re: DEVICE SELECTION
From: Richard Schwarz <aaps@erols.com>
Date: Wed, 12 Mar 1997 10:43:09 -0500
Links: << >>  << T >>  << A >>
Samir Marc Falaki wrote:

  Hi,

  I need to make a decoder and demultiplexer with at least 64 outputs
  each + related logic.  I have used Xilinx FPGAs with Mentor and
  Synopsys but would prefer a device that is more straightforward to
  program and with inexpensive tools (personal project).  I have
  considered using CPLDs that would be one-time programmable and it
  seems
  to be a good idea.  Does anyone have some suggestions.  I don't have

  $millions so I would like something that is inexpensive to program,
  lot's of i/o, and tools that don't require patches and work-arounds.

  Thanks,

  Sam Falaki

 Sam,

Check our XILINX tool sets at http://www.erols.com/aaps they are very
low cost!!

But if even they are too much, You could check out Cypress anf AMD 84
pin PLCC in circuit programmable parts. I have used the AMD and Cypress
version of the MACH 230. The old PALASM compiler is free. Also Cypress
sells a $99.00 VHDL compiler for its PLDs. I have it and it works fine.
But they really don't match the flexibility and power of the XILINX
stuff.

Feel free to call and ask any questions on the above stuff.

Richard Schwarz

Pres. APS



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