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Messages from 5800

Article: 5800
Subject: Re: Accolade
From: "David Pellerin" <pellerin@seanet.com>
Date: 16 Mar 1997 16:32:31 GMT
Links: << >>  << T >>  << A >>
Hi Joel (and others),

I'm not sure why a follow-up response "fell through the cracks", but since
your query back in January we have released a new version of the product
(and the demo) that is designed specifically for Windows NT 4.0 and 95. We
encourage you to visit our Web site and download this latest software for
evaluation. The new version is must faster, much more stable and has better
features (for both simulation and synthesis) than the earlier products.

Regards,

-- David Pellerin (pellerin@seanet.com)

-- Accolade Design Automation, Inc.
-- 26331 NE Valley, Suite 5-120, Duvall, WA 98019
-- (800) 470-2686, (206) 788-1802, FAX (206) 788-3768
-- Visit http://www.acc-eda.com for a free PeakVHDL/PeakFPGA demo CD-ROM!!

Joel Kolstad <Joel.Kolstad@Techne-Sys.com> wrote in article
<01bc30ac$e2c746b0$0307e38f@zimbo>...
> > any experience with Accolade-Tools (VHDL-Simulation and FPGA-Synthesis)
?
> 
> I downloaded their demo and it died a horrible death under NT 4.0.
> 
> Initially their tech support was helpful, but they never did deliver on
> their promise to get back to me regarding their investigations into why
it
> died.
> 
> 							---Joel Kolstad
> 
> 
Article: 5801
Subject: Re: VHDL & ABEL synthesis tools on 95/NT
From: "David Pellerin" <pellerin@seanet.com>
Date: 16 Mar 1997 17:00:34 GMT
Links: << >>  << T >>  << A >>


> Synplicity is a very fast synthesis tool but gives almost no
> feedback about what it has done (at least in last years release 2.99).
> Exemplar gave a very good impression in a demo.
> You might also want to check the accolade tools (I believe their address
> is http://www.acc-eda.com) or synopsys fpga express.

Accolade Design Automation does indeed have FPGA tools to offer. Visit our
Web site for complete product details. We have just released version 3.10,
and evaluation software can be downloaded from the web site.

Regards,

-- David Pellerin (pellerin@seanet.com)

-- Accolade Design Automation, Inc.
-- (800) 470-2686, (206) 236-9598, FAX (206) 788-3768
-- http://www.acc-eda.com

Article: 5802
Subject: Re: ACTEL RAM BASED FPGAs
From: peter@xilinx.com (Peter Alfke)
Date: Sun, 16 Mar 1997 10:50:29 -0700
Links: << >>  << T >>  << A >>
In article <5gb56l$b8d@info-server.surrey.ac.uk>, ees1ht@ee.surrey.ac.uk
(Hans Tiggeler) wrote:

> I have just, and with me probably 10000 of engineers, received then ES 
> datasheets. In their FAQ sheet they say that Actel and Xilinx cross licensed 
> their patents, thus Xilinx has access to anti-fuse and Actel to SRAM
technology. 
> Did Xilinx loose out on this deal, or are they still working on a
antifuse part?
> 

Xilinx cancelled the XC8100 amorphous antifuse-based project last year,
concentrating its efforts on SRAM and FLASH-based programmable logic.

Peter Alfke, Xilinx Applications
Article: 5803
Subject: Re: Reverse Engineering FPGAs
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Sun, 16 Mar 1997 20:37:08 GMT
Links: << >>  << T >>  << A >>
In article <5g4cmr$ht7@neptune.myri.com>,
Wen-King Su <wen-king@myri.com> wrote:
>...Could it be that the consortium
>members want no challenges from those who are not big enough to do hardwired
>gate arrays? 

In fairness, while complex, hard-to-meet standards certainly do serve the
interests of large, established companies by making it difficult for little
startups to compete, one need not assume actual malice.  There is always a
tradeoff between performance and easy implementation, and big companies can
cope with implementation difficulties relatively easily, so naturally their
design ideas are biased strongly toward maximum performance.

"Never ascribe to malice what can be explained by stupidity."
-- 
Committees do harm merely by existing.             |       Henry Spencer
                           -- Freeman Dyson        |   henry@zoo.toronto.edu
Article: 5804
Subject: Re: A viewlogic story
From: z80@dserve.com (Peter)
Date: Sun, 16 Mar 1997 22:04:00 GMT
Links: << >>  << T >>  << A >>

>Protel for Windows Advanced Schematic is worth looking at.  Its not expensive
>and will export netlists in a dozen formats.  One thing to check is for NT
>compatability problems.  Aparently there are a few with the Adv. PCB package
>but I'm not sure about the Schematic because its newer than the PCB package.
>
>P.S. I think Protel don't support NT 4.0 yet. But neither do a lot of Windows
>3.11 CAD suppliers so don't be too surprised if they can't help if something
>strange happens in NT 4 that doesn't happen in older versions of NT
>you can but ask about such things.

I briefly evaluated Protel Schematic 3.2 (the latest currently) under
NT4 and did not find any problems, other than one serious bug which
was also present in all earlier versions, namely that doing a Select
All followed by Move/Drag crashed the program if the file/block was
over a certain size, about 200k. But this might have been caused by
other factors.

The latest Protel stuff is said to have been written in Borland Delphi
2, and in my experience there should be no NT-specific problems with
that compiler. Still leaves a few areas for incompatibility though,
through sloppy programming.

Personally I am sticking with Orcad SDT/386 (DOS) - this is far
superior in simple usability to any Windows-based sch. cap. prog I
have tried. I have not used it for FPGA work though because that needs
a simulator (which I don't have for Orcad). I still use Workview 4.1
(Viewdraw+Viewsim) (DOS) for Xilinx work, and this has no apparent
bugs except the damned dongles.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5805
Subject: Re: ACTEL RAM BASED FPGAs
From: Richard Schwarz <aaps@erols.com>
Date: Sun, 16 Mar 1997 21:21:02 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

  In article <5gb56l$b8d@info-server.surrey.ac.uk>,
  ees1ht@ee.surrey.ac.uk
  (Hans Tiggeler) wrote:

  > I have just, and with me probably 10000 of engineers, received
  then ES
  > datasheets. In their FAQ sheet they say that Actel and Xilinx
  cross licensed
  > their patents, thus Xilinx has access to anti-fuse and Actel to
  SRAM
  technology.
  > Did Xilinx loose out on this deal, or are they still working on a
  antifuse part?
  >

  Xilinx cancelled the XC8100 amorphous antifuse-based project last
  year,
  concentrating its efforts on SRAM and FLASH-based programmable
  logic.

  Peter Alfke, Xilinx Applications

 Smart move!

Richard

Article: 5806
Subject: Re: Xilinx/NeoCAD software vs. XC4KE question
From: Richard Schwarz <aaps@erols.com>
Date: Sun, 16 Mar 1997 21:47:19 -0500
Links: << >>  << T >>  << A >>
bob elkind wrote:

  In article <3326D5D9.6F67@pa.msu.edu>, gross@pa.msu.edu says...
  > Hi,
  >
  > I have a dilemma regarding Xilinx software, NeoCAD (OK, Xilinx
  also)
  > software, and XC4KE devices.
  >
  > I am an XACT Foundry V7.0 (aka NeoCAD FPGA Foundry) user.  I am
  > have spent a lot of time getting to know this software and I like
  > it a lot.  But it doesn't support XC4KE features.
  >
  > I also have XACTstep XC4000E Pre-Release V1.0.0, which does
  support
  > XC4KE features, but which I have so far not attacked in earnest.

    <snip>

  > What I *want* (but have been told is not going to happen) is for a

  > new version of XACT Foundry to appear at my doorstep, with XC4KE
  > support rolled in.
  >
  > What I will settle for is just a straight answer on when the
  merged
  > toolset will be released, so that I can make a rational decision
  > between my alternatives.  Anybody with a crystal ball, a buddy at
  > Xilinx, or a boss at Xilinx want to help?

  > -Steve Gross  gross@pa.msu.edu

  When it comes time to Xilinx tools software, the wisest course
  is to not depend on a specific release/availability date.
  I don't mean this as a swipe at Xilinx, please don't misunderstand.
  Would you want Xilinx to release a package that wasn't fully
  tested and wrung out, in order to meet a specific availability
  date?  I don't think that is what you really want.  Xilinx
  has had problems in the past with SW releases that were
  buggy.  I think Xilinx is trying hard to correct that practice,
  even though additional testing adds time to the development/release
  schedule.

  In the engineering spirit, you should make do with the tools
  that are available and that you can make work today. If something
  better comes along, then you can always consider a switch (and
  the risk of a new learning curve) at that time.  Depending upon
  the circumstances, many designers won't even consider major
  tools changes in the middle of a project, unless they are
  really desperate.  The risk is usually too great.

  -- Bob Elkind

  ****************************************************************
  Bob Elkind                              mailto:eteam@aracnet.com
  7118 SW Lee Road               part-time fax number:503.357.9001
  Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
  ****** Video processing, R&D, ASIC, FPGA design consulting *****


I must concur on the XILINX schedules. I am a big fan of XILINX, and
will continue to be, but I have waiting for the NEO-CAD router for over
a year, and have had at least four release dates discussed.
--
__________________________________________________________
Richard D. Schwarz, President
Associated Professional Systems (APS)
3003 Latrobe Court, Abingdon, Maryland 21009
Phone: 410-569-5897   Fax: 410-661-2760
Email: aaps@erols.com   Web site: http://www.erols.com/aaps
--- FPGA Solutions/Test Boards/ EDA Software ---
--- SIGTEK Spread Spectrum & Communications Equipment ---

Article: 5807
Subject: PLC
From: "Apolonio B. Sanches" <paulsan@asti.dost.gov.ph>
Date: Mon, 17 Mar 1997 19:09:00 +0800
Links: << >>  << T >>  << A >>

To all


I'm making a survey regarding the limitations in features of PLCs.

I would like to have your comments on what improvements or added features 
should be added or improved in today PLC.


What are the important things you look for in choosing a PLCs?


Thank you for your positive inputs or comments.


Paul






Article: 5808
Subject: Synopsys -> Altera (maxplus2) interface
From: Kari Laiholuoto <kari.laiholuoto@martis.fi>
Date: Mon, 17 Mar 1997 14:42:27 +0200
Links: << >>  << T >>  << A >>
Hi
I have a problem in synopsys-maxplus2-interface. I would appreciate
if someone who has solved the problems would share the knowledge with
me.

If I am using LUT's in synopsys, is it possible to produce an edif
netlist
file so that the maxplus2 would accept the LUT's in it?

I have not found a method to do so  - it seems to me that I have to run
the replace_fpga command (and lose the mapping information) and
'resynthesize' the design once again in maxplus2 which will give much
worse area estimate. If the design is allready mapped into LUT's in
synopsys phase it would be nice to use that information in maxplus2
directly.

Yours  Kari Laiholuoto
--

Kari Laiholuoto                          Tellabs Oy
Tel. 358-9-4131 2795               Sinikalliontie 7
Fax. 358-9-4131 2200               FIN-02630  ESPOO
Email: Kari.Laiholuoto@tellabs.fi           FINLAND
Article: 5809
Subject: Reminder: Reed-Muller 97 -- Int. Workshop on Function Representations
From: Jon.Saul@comlab.ox.ac.uk (Jon Saul)
Date: Mon, 17 Mar 97 15:30:30 GMT
Links: << >>  << T >>  << A >>

A reminder that the deadline for papers is April 4th. 

	Jon





			   Call For Papers
                                                                               
 
      	   3rd International Workshop on Applications of the
                Reed-Muller Expansion in Circuit Design 
			   (Reed-Muller 97)

		  In Cooperation with IFIP WG 10.5.

                                                                          
Place: Oxford University, Oxford, UK.
Date:  September 19-20, 1997
	just after ESSCIRC 97 (European Solid-State Circuits Conference)
		Southampton, UK, September 16-18 . 
	just before EuroDAC 97 (European Design Automation Conference)
		Dusseldorf, Germany, September 22-26 . 
 	

This workshop focuses on the application of new techniques in the
representation and realization of discrete functions. AND-EXOR based
representations are often simpler than AND-OR based representations,
and have other important properties. Decision diagrams are being
extensively studied, and have offered powerful new techniques for
verification and synthesis.  The goal of the workshop is to bring
together researchers in these and related fields to discuss new
approaches and results. The first workshop was held in September 1993,
in Hamburg, and the second in August 1995, in Tokyo.

A non restrictive list of interest includes the following topics:
	* Graph-based representation of logic functions 
           Binary decision diagrams,  Functional decision diagrams etc.
	* EXOR-based logic synthesis
           Reed-Muller expressions, Kronecker expressions,
           Exclusive-OR Sum-of-Products Expressions (ESOPs), 
	   Multi-level circuits
	* Spectral techniques
	* New representations for discrete functions
	* Complexity theory
           AND-OR vs. AND-EXOR 
	* Easily testable circuits using EXORs
	* Implementation in silicon (FPLDs, FPGAs,...)
	* Applications, both inside and outside circuit design. 

Chairman:                              	Co-Chairman:
Jonathan Saul                         	Udo Kebschull
Oxford University,			FZI 
UK.					Germany.

Authors are invited to submit, by April 4, 1997, 10 copies of draft
papers not exceeding 20 pages, together with a signed statement that
if the paper is accepted the author will present it at the
workshop. Notifications of acceptance will be sent by June 20, 1997. A
workshop handout will be distributed to the workshop attendees, and it
is planned to publish selected papers in a more widely distributed
form. The camera-ready paper must be received by August 1, 1997.

Submissions should be sent to:
Jonathan Saul, Oxford University Computing Laboratory, Wolfson Building, 
Parks Road, Oxford OX1 3QD, UK.						
or
Udo Kebschull, Forschungszentrum Informatik (FZI),
Haid-und-Neu-str. 10-14, 76131 Karlsruhe, Germany

Enquiries :
Miss Frances Page
Oxford University Computing Laboratory
Wolfson Building
Parks Road
Oxford OX1 3QD, UK.
Tel: +44 1865 283505/273838
Fax: +44 1865 273839

Further details will become available on the website: 
http://www.comlab.ox.ac.uk/oucl/users/jon.saul/ReedMuller97.html

Program Committee:

Bernd Becker        	University of Freiburg, Germany.
Jon T. Butler       	Naval Postgraduate School, USA.
Olivier Coudert		Synopsys, USA.
Rolf Drechsler		University of Freiburg, Germany. 
Masahiro Fujita     	Fujitsu Laboratories of America, USA.
Kiyoshi Furuya      	Chuo University, Japan. 
Udo Kebschull       	Forschungszentrum Informatik (FZI), Germany.
Tomasz Kozlowski	University of Zielona Gora, Poland. 
GueeSang Lee		Chonnam National University, Korea. 
Margaret Marek-Sadowska	University of California, Santa Barbara, USA.
Christoph Meinel    	University Trier, Germany.
Michael Miller		University of Victoria, Canada.
Shin-Ichi Minato    	NTT LSI Laboratories, Japan.
Marek A. Perkowski  	Portland State University, USA.
Tsutomu Sasao       	Kyushu Institute of Technology, Japan.
Jonathan Saul 		University of Oxford, UK.
Endric Schubert		Exemplar Logic, USA.
-- 
Jonathan Saul,                             Tel: +44 1865 273842
Oxford University Computing Laboratory,    Fax: +44 1865 273839
Wolfson Building, Parks Road,            Email: Jon.Saul@comlab.ox.ac.uk
Oxford OX1 3QD,	UK.						
Article: 5810
Subject: Re: VHDL & ABEL synthesis tools on 95/NT
From: Tom Bowns <bowns@data-io.com>
Date: Mon, 17 Mar 1997 15:52:11 GMT
Links: << >>  << T >>  << A >>
> Todd A. Kline wrote:
>...  I also have doubts about DataIO's commitment to EDA
> products.  

I told myself I wouldn't jump in, but I must.

Synario is entirely committed to the Windows EDA market; since we
started five years ago, since we launched Synario 1.0 in 1993, today,
and on into the future. 

If I say more, it would be considered a spam.

-TBB
Article: 5811
Subject: Re: pld 74hc195 equiv
From: peter@xilinx.com (Peter Alfke)
Date: Mon, 17 Mar 1997 09:24:22 -0700
Links: << >>  << T >>  << A >>
In article <858277750.13643@dejanews.com>, rcgipson@ix.netcom.com wrote:

> has anyone ever duplicated a 74hc195 with a pld?  i've a need
> to add a 195 and some other circuitry in a single chip.

The 74195 
( originally the Fairchild 9300 4-bit shift register with synchronous
parallel load, Jkbar shift input to the first stage, and asynchronous
clear) 
is a trivial design that would fit into 2 CLBs ( XC3000 or XC4000 ), i.e.
3% of the smallest FPGA devices available. 
In a CPLD, it would take 4 macrocells, which is  about 10% of the smallest
available CPLD. 
It takes 40% of a 22V10 PAL.
Any of these designs can run close to a 100 MHz clock rate.

So, the PAL may be the most practical choice, unless you want to add a
substantial amount of logic.

Peter Alfke, Xilinx Applications.
Article: 5812
Subject: Re: viewoffice compatibility - dumb question
From: "Rich K." <rich.katz@gsfc.nasa.gov>
Date: 17 Mar 1997 16:29:29 GMT
Links: << >>  << T >>  << A >>
hi bob,

please see embedded comments (w/ '****') below.

thanks for the tips.

rk

-----------------------------------------------

bob elkind <eteam@aracnet.com> wrote in article
<MPG.d9156451f7e4481989689@news.zippo.com>...
> rich.katz@gsfc.nasa.gov says...
> > hi,
> > 
> > i have upgraded a bunch of viewlogic 'seats' to the viewoffice stuff
and
> > got them all at the exact same revision.  seems like a good idea.  now,
> > some seats were upgraded from workview plus and others from pro series.

> <snip>
> > now that they are all the same,
> > i am having trouble (like can't do it) reading files on 'heritage' pro
> > series seats from former workview plus seats, although they are just
simple
> > schematics that i can easily create on either computer.  and going from
the
> > former pro series to the former workview plus seems to work just fine.
> > 
> > suggestions? comments?

----------------------------------------------------------------------

> 
> Sounds like possible artifacts from the ViewLogic licensing
> scheme for WV and PRO, where PRO licenses were deliberately
> crafted so that there was no compatibility permitted from
> WV to PRO seats.  ViewLogic tech support should be able to
> sort this out for you, but the fix should be interesting.

**** definitely an artifact of this and was part of the reason to upgrade
all seats
**** to the same s/w.  i am working with tech support now and have sent
them
**** license file and all from the previously pro series machine and now
they
**** want a license file from a machine which generated the incompatible
**** files.  i figured i would get a quick answer as to whether there is a
problem
**** or not but not so.

> 
> Here's a possible suggestion, if you're desperate:

**** not desperate (yet) but already at the highly annoyed stage.

> 
> How about installing the old WorkView on the former
> PRO seats?  Have you tried that?  If that works, then
> you can try "upgrading" the WV to WV Office.  This may
> be worth a go.

**** one of the pro series seats originated as proseries.  and
**** apparently the license files are completely new - getting the
**** right license file was a major headache.  so, can't try it and
**** don't think it will work.  i assume you thought that some 
**** previous permissions might be promoted.  if not, then i 
**** missed it so please let me know if there is something else.
**** depending on how this works, i have to dormant 'crippled'
**** seats which i may upgrade, as they are coming in demand.
**** might be easier to start over with .....   :-)

> 
> And here's a gratuitous comment:  ViewLogic's licensing,
> dongle, and security key schemes were devised to maximise
> revenue to the last penny.  For users, it was a real pain
> to be blocked at every new turn while trying to do something
> that should have been simple enough, and every time the
> answer from ViewLogic was 'sure, we can help you, here's
> what you need to buy, and this is how much it costs.'

**** no comment (hey, i work for the gov't, i can say that!)
**** actually, when i was switching things over to an edif
**** interface they quoted me the price to 'upgrade' three
**** seats (workview plus, i believe).  not inexpensive.

> 
> I wouldn't be surprised if you've been bitten by a residual
> artifact of their arcane licensing policy and implementation.
> You would not have been the first, if this is the case.

**** this would be bad if we're stuck as we have all of our
**** 'puters pretty well connected w/ win '95 and ftp and all
**** and like to effortless move modules and designs between
**** machines and designers.  thinking about only uni-directional
**** flows and dealing with them sort of hurts.

> 
> Good luck, and please post the final fix for this problem!

**** it shall be post the final answer - can't promise the final fix.

**** rk


> 
> -- Bob
> 
> ****************************************************************
> Bob Elkind                              mailto:eteam@aracnet.com 
> 7118 SW Lee Road               part-time fax number:503.357.9001
> Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
> ****** Video processing, R&D, ASIC, FPGA design consulting *****
> 
Article: 5813
Subject: Re: PEEL16V8 with PALASM
From: Werner Dreher <dreher@informatik.uni-tuebingen.de>
Date: Mon, 17 Mar 1997 17:59:51 +0100
Links: << >>  << T >>  << A >>
Gabby Shpirer wrote:
> 
> I'm maybe old fashion but I'm using PEEL16V8 and I'm trying to

Hi,

maybe you should try PALCE16V8 (from AMD)

Werner
Article: 5814
Subject: Re: Synopsys -> Altera (maxplus2) interface
From: peck@cs.ucla.edu (John C. Peck, Jr.)
Date: Mon, 17 Mar 1997 20:23:03 GMT
Links: << >>  << T >>  << A >>
Kari,

Here's one half of your solution.  Make sure to set the global
synthesis style in maxplus2 to WYSIWYG.  Your mapped LCELL
info will be retained because no resynthesis is performed.

You may want maxplus2 to make use of  carry and cascade logic though
within your LUT solution.  I've noticed lower delays when these
features are added to my mapped solutions.  Make sure that that the
"minimization" parameter is set to default and the carry chain and
cascade chain are set to auto. 

Good luck,

John Peck

Kari Laiholuoto <kari.laiholuoto@martis.fi> wrote:

>Hi
>I have a problem in synopsys-maxplus2-interface. I would appreciate
>if someone who has solved the problems would share the knowledge with
>me.
>
>If I am using LUT's in synopsys, is it possible to produce an edif
>netlist
>file so that the maxplus2 would accept the LUT's in it?
>
>I have not found a method to do so  - it seems to me that I have to run
>the replace_fpga command (and lose the mapping information) and
>'resynthesize' the design once again in maxplus2 which will give much
>worse area estimate. If the design is allready mapped into LUT's in
>synopsys phase it would be nice to use that information in maxplus2
>directly.
>
>Yours  Kari Laiholuoto
>--
>
>Kari Laiholuoto                          Tellabs Oy
>Tel. 358-9-4131 2795               Sinikalliontie 7
>Fax. 358-9-4131 2200               FIN-02630  ESPOO
>Email: Kari.Laiholuoto@tellabs.fi           FINLAND

Article: 5815
Subject: Re: PLC
From: Brad Taylor <blt@emf.net>
Date: Mon, 17 Mar 1997 15:14:38 -0800
Links: << >>  << T >>  << A >>
Apolonio B. Sanches wrote:
> 
> To all
> 
> I'm making a survey regarding the limitations in features of PLCs.
> I would like to have your comments on what improvements or  added > features should be added or improved in today PLC.
 

I evaluate FPGAs for their ability to do data processing tasks.

My list of really desireable features:
1) bigger/faster/cheaper parts
2) bigger/faster/cheaper parts
3) bigger/faster/cheaper parts

My list of worthwhile architectural tradeoffs:
1) More Internal SRAM
2) HW multiplier in 4LUT 
3) HW PCI interface
4) RAMbus support
5) Time muxxed pins
6) Internal clock generation
7) Word oriented architecture
8) Internal (picojava?) CPU to assist in configuration/SW 

My list of necessary industry standards:
1) Standards for FPGA coprocessor hardware
2) Standard compilers for above HW
3) Standard debuggers for above HW
4) Satndard operating systems for above HW
4) Standard applications for above HW

My list of desireable Tools:
1) Fully automated compile/place/route/test
2) A router that runs under NT 
3) A (restricted) ANSI C/C++ complier for FPGAs
4) Dataflow managment tools
5) Operator code generation
7) Accuracy driven translation of floating point code to fixed point.

and so on.

-
Brad
Article: 5816
Subject: Cisco's SIBU is looking for ASIC and Systems Engineers
From: lshevock@diablo.cisco.com (CISCO SYSTEMS)
Date: 18 Mar 1997 00:12:20 GMT
Links: << >>  << T >>  << A >>
I am with Human Resources for the Small Internetworks Business Unit
(formerly Grand Junction) at Cisco Systems.  We develop switches, routers,
and hubs that focus on small and medium-sized companies.  Revenue-wise we
are the fastest growing Business Unit at Cisco Systems with 30+% growth
over the last five quarters.  

We are currently looking for senior and intermediate ASIC Engineers
(digital) as well as senior and intermediate Systems Engineers (embedded
CPU, FPGA) to join our team.  We are located in San Jose, California.

If you, or anyone you know is interested, please contact me or send me
your resume.  I will be happy to talk with you further about the
positions.

Randall Birkwood (rabirkwo@cisco.com)
408-526-4244-direct
408-527-0180-fax

-- 
To send your resume:
fax:  527-0180 or
email:  lshevock@cisco.com
No agencies please
Article: 5817
Subject: Re: viewlogic ...
From: David Pashley <david@fpga.demon.co.uk>
Date: Tue, 18 Mar 1997 11:17:04 +0000
Links: << >>  << T >>  << A >>
7.3 is really worth having, but not easy to get hold of (even for VARs
like us). It's not buggy, but was withdrawn because of a minor
commercial technicality.

ViewDraw features Return Of The Command Line, LPM symbol generator, OLE
interface methods, autopan, symbol wizard, ViewDRC and more...

There are major improvements to many other modules, including SpeedWave,
ViewSynthesis (now Synopsys-compatible), VCS, ViewDataBook.

7.31 just started to ship, I hear.

David Pashley


In article <01bc28d5$2f53d6e0$6e0db780@Rich>, "Rich K."
<rich.katz@gsfc.nasa.gov> writes
>i've seen a number of posts on the viewlogic s/w with some having
>experience with 7.3 (currently i am at 7.2).  now, is 7.3 an improvement
>over 7.2?  we heard that it hasn't shipped to us because it is buggy and we
>should wait to 7.31.  anybody have any thoughts on this?  anybody know of a
>version that isn't buggy? :-)
>
>thanks for the help,
>
>rk


Article: 5818
Subject: Re: A viewlogic story
From: st803cwk@dunx1.ocs.drexel.edu (Charles Reed)
Date: 18 Mar 1997 13:00:56 GMT
Links: << >>  << T >>  << A >>
In article <33246ee5.19810726@news2.lightlink.com>,
Mike Williams <please@no.junk.mail.com> wrote:
>On Fri, 7 Mar 1997 15:07:00 GMT, ecla@world.std.com (alain arnaud)
>wrote:
>
>>A viewlogic story...
>>
>>I have been using Viewlogic since the late 80s. 
>
>-snip-
>
>>In summary:
>>	- Viewsynthesis is BAD!
>>	- Viewoffice is usable but less user friendly than the older
>>	  products.
>>	- Viewlogic tech support is non-existent.
>>	- I will not recommend ViewOffice to any of my clients anymore.
>>
>>IMHO, Viewlogic decided that they had to compete with Orcad and some
>>of the other low end tools at the same time they were trying to compete
>>with Mentor and Cadence, and they missed the boat. They changed the sales
>>channel, by focusing on distributors (Trilogic in Mass.) for small companies
>>and direct sales for large corp.
>>
>>So my question is:
>>	Does Mentor Graphics and or Cadence have CAD tools for Win/NT or
>>	a Sparc at a competitive price?	
>>
>>Tools I use today are:
>>	- Viewdraw and Viewsim (until I find a replacement)
>>	- Modeltech for VHDL simulation
>>	- FPGA Express for FPGA synthesis
>>	- DC for ASIC synthesis
>>
>>Alain Arnaud (arnaud@ecla.com)
>>ECLA Inc.
>
>How timely. Just yesterday I received a package from VIEWlogic
>singing the praises of Workview Office. I guess I should read their
>hype with a pound of salt.
>
>I'm looking to update my NT OS CAD tool set. I was looking at ORCAD
>but was told by some old school VIEWlogic users that VIEWlogic was
>superior. Now I'm not so sure.
>
>Any suggestions. I need schematic entry for PCB design. I don't need
>to actually do the PC layout, just produce the schematics, parts
>list and netlist.
>
>-Mike Williams
>mcw@lightlink.com
>
>
>

I just completed the Xilinx 3-day training class which used the
VIEWlogic tools.  I thought they were fine.  Since I won't be
using VIEWLogic (we're an ORCAD house for the time being) I
didn't pay *that* much attention to those lab exercises. It
definately worked well as far as flowing into and out of the XACT 
tools.

Chuck Reed
 

Article: 5819
Subject: Re: Development board with multiple FPGAs
From: olson@ee.duke.edu (Kevin M. Olson)
Date: 18 Mar 1997 16:16:59 GMT
Links: << >>  << T >>  << A >>
Hari Shankar <hshankar@wlv.hp.com> writes:


The University of California at  Santa Cruz developed what is called a Borg board,  which is a PC board with 4 FPGA's on it, as well as some software to go along with it.   I am not sure if they are available commercially,  but I know that they are used in several universities.   I don't know of any specific link to check it out-    maybe the ucsd web pages,  or do a net search.  Good luck-  I hope this helps.

Kevin


>Is it possible to purchase a development board with multiple XILINX 4000
>series FPGAs so that large designs can be accomodated?  If so, can I 
>have the address/phone# of the company?

>Thanks in advance,

>Hari Shankar
Article: 5820
Subject: Multiple clocks in Xilinx
From: djg@tas.com (David Gesswein)
Date: 18 Mar 1997 12:04:31 -0500
Links: << >>  << T >>  << A >>
Has anybody found any documentation on using multiple clocks in a xilinx
4000/5200 part?  The question I have is how to transfer signals between the two 
clock domains.  Can you use a low skew external clock generator and the internal
clock distribution including the two global clock buffers skew will be small
enough that the hold time when a register feeds a register will be met or
do I have to treat the clocks as asynchronous or use different edges or
other methods to ensure that the signal will be transfered reliably?

The reason for the two clocks is that most of the design should run at a slower
clock but a little bit needs to run faster so using the clock enable to
simulate the slower clock seems excessive.

I talked to the hotline but they didn't have any application information on the
use of multiple clocks.

Thanks
David Gesswein
djg@tas.com
Article: 5821
Subject: Re: Development board with multiple FPGAs
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 18 Mar 1997 17:09:56 GMT
Links: << >>  << T >>  << A >>
I believe that the proper person to contact regarding the BORG board would
be Professor Pak K. Chan at the University of California at Santa Cruz.

http://www.cse.ucsc.edu/~pak/

For more information on the BORG board itself, see

http://www.cse.ucsc.edu/~martine/borg/


-- 
Steven Knapp
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Kevin M. Olson <olson@ee.duke.edu> wrote in article
<5gmf5r$b3p@newsgate.duke.edu>...
| Hari Shankar <hshankar@wlv.hp.com> writes:
| 
| 
| The University of California at  Santa Cruz developed what is called a
Borg board,  which is a PC board with 4 FPGA's on it, as well as some
software to go along with it.   I am not sure if they are available
commercially,  but I know that they are used in several universities.   I
don't know of any specific link to check it out-    maybe the ucsd web
pages,  or do a net search.  Good luck-  I hope this helps.
| 
| Kevin
| 
| 
| >Is it possible to purchase a development board with multiple XILINX 4000
| >series FPGAs so that large designs can be accomodated?  If so, can I 
| >have the address/phone# of the company?
| 
| >Thanks in advance,
| 
| >Hari Shankar
| 
Article: 5822
Subject: FCCM'97 Preliminary Program
From: jmarnold@potomac.znet.com (Jeffrey M. Arnold)
Date: 18 Mar 1997 09:22:01 -0800
Links: << >>  << T >>  << A >>
                   The 5th Annual IEEE Symposium on
             Field-Programmable Custom Computing Machines
              Marriott at Napa Valley, Napa, California
                      April 16 - April 18, 1997

                         Preliminary Program

                         http://www.fccm.org


        Tuesday, April 15, 1997
7:00 - 9:00 PM                  Registration and Reception

        Wednesday, April 16, 1997
7:30 AM                         Registration Opens
8:30    - 10:00 AM              Session 1
10:00   - 11:00 AM              Break and Poster Session 1
11:00   - 12:00 PM              Session 2
12:00   - 1:30 PM               Lunch
1:30    - 3:00 PM               Session 3
3:00    - 4:00 PM               Break and Poster Session 2
4:00    - 5:00 PM               Session 4
5:00    - 6:00 PM               Open
6:00    - 9:00 PM               Demonstrations and Reception

        Thursday, April 17, 1997
8:00 AM                         Registration opens
8:15    - 8:30 AM               Administrative updates
8:30    - 10:00 AM              Session 5
10:00   - 11:00 AM              Break and Poster Session 3
11:00   - 12:00 PM              Session 6
12:00   - 1:30 PM               Lunch
1:30    - 3:00 PM               Session 7
3:00    - 4:00 PM               Break and Poster Session 4
4:00    - 5:00 PM               Session 8
5:00    - 7:00 PM               Open
7:00    - 10:00 PM              Banquet

        Friday, April 18, 1997
8:00 AM                         Registration opens
8:15    - 8:30 AM               Administrative updates
8:30    - 10:00 AM              Session 9
10:00   - 11:00 AM              Break and Poster Session 5
11:00   - 12:00 PM              Session 10
12:00   - 12:30 PM              Closing Remarks & Feedback for next year


Wednesday, April 18, 1997 (Day 1)

Session 1:  Device Architecture
        Title:          An FPGA Architecture for DRAM-based Systolic Computations
        Authors:        N. Margolus
        Organizations:  Boston University and Massachusetts Institute of Technology

        Title:          Garp: A MIPS Processor with a Reconfigurable Coprocessor
        Authors:        J. Hauser, J. Wawrzynek
        Organization:   University of California, Berkeley

        Title:          A Time-Multiplexed FPGA
        Authors:        S. Trimberger, D. Carberry, A. Johnson
        Organizations:  Xilinx, Inc.

Poster Session 1

Session 2:  Communication Applications 
        Title:          An FPGA-Based Coprocessor for ATM Firewalls
        Authors:        J. McHenry, P. Dowd, T. Carrozzi, F. Pellegrino, W. Cocks
        Organization:   National Security Agency and University of Maryland

        Title:          A Wireless LAN Demodulator in a Pamette: Design and Experience
        Authors:        T. McDermott, P. Ryan, M. Shand, D. Skellern,
                        T. Percival, N. Weste
        Organization:   Macquarie University, CSIRO, and Digital Equipment Corp.

LUNCH

Session 3:  Run Time Reconfiguration
        Title:          Incremental Reconfiguration for Pipelined Applications
        Authors:        H. Schmit
        Organization:   Carnegie Mellon University

        Title:          Compilation Tools for Run-Time Reconfigurable Designs
        Authors:        W. Luk, N. Shirazi, P. Cheung
        Organization:   Imperial College

        Title:          A Dynamic Reconfiguration Run-Time System
        Authors:        J. Burns, A. Donlin, J. Hogg, S. Singh, M. de Wit
        Organization:   University of Glasgow

Poster Session 2

Session 4:  Architectures for Run Time Reconfiguration
        Title:          The Swappable Logic Unit: A Paradigm for Virtual Hardware
        Authors:        G. Brebner
        Organization:   University of Edinburgh

        Title:          Computing Kernels Implemented with a Wormhole RTR CCM
        Authors:        R. Bittner and P. Athanas
        Organization:   Virginia Polytechnic Institute


Thursday, April 17, 1997 (Day 2)

Session 5:  Architecture
        Title:          The Chimaera Reconfigurable Functional Unit
        Authors:        S. Hauck, T. Fry, M. Hosler, J. Kao
        Organization:   Northwestern University

        Title:          Mapping Applications to the RaPiD Configurable Architecture
        Authors:        C. Ebeling, D. Cronquist, P. Franklin, J. Secosky, S. Berg
        Organization:   University of Washington

        Title:          Defect Tolerance on the Teramac Custom Computer
        Authors:        B. Culbertson, R. Amerson, R. Carter, P. Kuekes, G. Snider
        Organizations:  Hewlett-Packard Laboratories

Poster Session 3

Session 6:  Performance
        Title:          Systems Performance Measurement on PCI Pamette
        Authors:        L. Moll, M. Shand
        Organizations:  Pole Universitaire Leonard de Vinci and 
                        Digital Equipment Corp.

        Title:          The RAW Benchmark Suite: Computation Structures 
                        for General Purpose Computing
        Authors:        J. Babb, M. Frank, E. Waingold, R. Barua, M. Taylor,
                        J. Kim, S. Devabhaktuni, P. Finch, A. Agarwal
        Organization:   Massachusetts Institute of Technology

LUNCH

Session 7:  Software Tools
        Title:          Automated Field-Programmable Compute Accelerator Design Using
                        Partial Evaluation
        Authors:        Q. Wang, D. Lewis
        Organization:   University of Toronto

        Title:          FPGA Synthesis on the XC6200 using IRIS and Hades
        Authors:        R. Woods, S. Ludwig, J. Heron, D. Trainor, S. Gehring 
        Organization:   The Queen's University of Belfast and ETH Zurich

        Title:          High Level Compilation for Fine Grained FPGAs
        Authors:        M. Gokhale, E. Gomersall
        Organization:   David Sarnoff Research Center and National Semiconductor

Poster Session 4

Session 8:  CAD Applications
        Title:          Acceleration of an FPGA Router
        Authors:        P. Chan, M. Schlag
        Organization:   University of California, Santa Cruz

        Title:          Fault Simulation on Reconfigurable Hardware
        Authors:        M. Abramovici, P. Menon 
        Organization:   Lucent Technologies and University of Massachusetts


Friday, April 18, 1997 (Day 3)

Session 9:  Image Processing Applications
        Title:          Automated Target Recognition on Splash 2
        Authors:        M. Rencher, B. Hutchings
        Organization:   Brigham Young University

        Title:          Real-Time Stereo Vision on the PARTS Reconfigurable Computer
        Authors:        J. Woodfill, B. Von Herzen
        Organization:   Interval Research Corp. and Rapid Prototypes, Inc.

        Title:          Increased FPGA Capacity Enables Scalable, Flexible CCMs:
                        An Example from Image Processing
        Authors:        J. Greenbaum, M. Baxter
        Organization:   Ricoh California Research Center

Poster Session 5

Session 10:  Arithmetic Applications
        Title:          Comparison of Arithmetic Architectures for Reed-Solomon
                        Decoders in Reconfigurable Hardware
        Authors:        C. Paar, M. Rosner
        Organization:   Worcester Polytechnic Institute

        Title:          Implementation of Single Precision Floating Point 
                        Square Root on FPGAs
        Authors:        Y. Li, W. Chu
        Organization:   University of Aizu
-- 
Jeffrey M. Arnold		jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace		Tel: 619-547-9257
San Diego, CA 92131		Fax: 619-547-9010
USA
Article: 5823
Subject: Re: viewlogic ...
From: "Rich K." <rich.katz@gsfc.nasa.gov>
Date: 18 Mar 1997 18:52:10 GMT
Links: << >>  << T >>  << A >>


David Pashley <david@fpga.demon.co.uk> wrote in article
<HbUXWCAwmnLzMA9g@fpga.demon.co.uk>...
> 7.3 is really worth having, but not easy to get hold of (even for VARs
> like us). It's not buggy, but was withdrawn because of a minor
> commercial technicality.
> 
> ViewDraw features Return Of The Command Line, LPM symbol generator, OLE
> interface methods, autopan, symbol wizard, ViewDRC and more...
> 
> There are major improvements to many other modules, including SpeedWave,
> ViewSynthesis (now Synopsys-compatible), VCS, ViewDataBook.
> 
> 7.31 just started to ship, I hear.
> 
> David Pashley

7.31 is shipping; our copy came just a day or two ago.  now comes the fun
of installing it three times.

rk
Article: 5824
Subject: Re: Development board with multiple FPGAs
From: martine@cse.ucsc.edu (Martine Schlag)
Date: 18 Mar 1997 21:51:38 GMT
Links: << >>  << T >>  << A >>
In article <5gmf5r$b3p@newsgate.duke.edu>,
Kevin M. Olson <olson@ee.duke.edu> wrote:
>Hari Shankar <hshankar@wlv.hp.com> writes:
>
>
>The University of California at  Santa Cruz developed what is called a Borg board,  which is a PC board with 4 FPGA's on it, as well as some software to go along with it.   I am not sure if they are available commercially,  but I know that they are used in several universities.   I don't know of any specific link to check it out-    maybe the ucsd web pages,  or do a net search.  Good luck-  I hope this helps.
>

http://www.cse.ucsc.edu/~martine/borg/



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