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Messages from 5850

Article: 5850
Subject: Re: Is this really possible?
From: Ray Andraka <randraka@ids.net>
Date: Thu, 20 Mar 1997 10:41:31 -0500
Links: << >>  << T >>  << A >>
Kent wrote:

> I am curious to know if anyone else has been able to instantiate a basic 50
> Mips processor in less than 10% of a 3090, or a "vector processor" in a
> little more than 200 CLBs. Is there some big secret about the 3090 you
> guys have been keeping quite, or is there something I am missing here?

No big secret.  The design is just well tailored to the FPGA
architecture.  I suspect the 'nanoprocessor' is a simple RISC engine
(very few instructions) with hooks to permit specialized instructions to
be added.  Metalithic makes extensive use of reconfiguration to handle
these special instructions.   You might refer to Mike Wirthlin's paper
on his Dynamic Instruction Set Computer (DISC) which he presented at
FCCM, I think in 1995. A 'vector processor' as described in the snipet
you included is quite doable.  You do need to tailor the design to the
FPGA architecture to get the performance and density.  For audio stuff,
like digital wings, it usually makes sense to do the processing with bit
serial processors.  Even at 30 bits and 8x oversampling, the bit rate is
only a little over 10 MHz.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930   FAX 401/884-7950
mailto:randraka@ids.net
http://www.ids.net/~randraka/
 
The Andraka Consulting Group is a digital hardware design firm
specializing in high performance DSP designs in FPGAs. Expertise
includes reconfigurable computers, computer arithmetic, and maximum
performance/density FPGA design.
Article: 5851
Subject: Viewlogic Licensing delays?? Anyone?
From: stuart.summerville@practel.com.au (Stuart Summerville)
Date: Thu, 20 Mar 1997 16:51:08 GMT
Links: << >>  << T >>  << A >>
Hi all,

I've now been waiting for 1 week to receive my license.dat file from
Viewlogic for Workview Office. Am I being too impatient, or are
Viewlogic either slack in customer support or inefficient in supplying
presumably basic license details....?

Stu.
---------------------------------------------
Stuart Summerville      
Project Engineer         
Practel International
442 Torrens Road, Kilkenny, SA 5009
Tel: (61.8) 8268 2196  Fax: (61.8) 8268 2882
Email: stuart.summerville@practel.com.au  
---------------------------------------------
Article: 5852
Subject: Re: Multiple clocks in Xilinx
From: Brad Taylor <blt@emf.net>
Date: Thu, 20 Mar 1997 09:18:33 -0800
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Some of the math here is getting out of hand. A mathematical "proof"
> that one cannot even build a shift register with a common clock just
> shows that the assumptions are wrong, since such designs are working > > by the millions.
> Some of these subtleties are impossible to capture in a data sheet.
> Any absolute min delay can be quite short, but it cannot coexist with > a max delay....etc.
....


No one disputes that your FPGAs work in the presence of substantial
clock skew.  Xilinix can guarantee that they will work, but as a
designer I can't. Not unless I make assumptions about tracking, and
routing delays.  As you say, these relations are complex variables of
the design, the family and the process. As a user, how do I calculate
when the clock skew is legal? I really appreciate the information you
put out about the physics of the problem. It's just that sometimes I
don't know what to do with the information. 

I think a good solution is to add this type of calculation to XDELAY. It
would be fine for instance, to print the allowable skew and required
delays between two external clock edges. 

Another solution is to simply use one clock, never gate it and write 
off any performance gained with such tricks, but this may not always be
an option.

-
Brad
Article: 5853
Subject: Re: Xilinx 4002 RAM Question
From: L3ZHANG@ELECOM2.watstar.uwaterloo.ca (Louis Zhang)
Date: Thu, 20 Mar 1997 17:26:40 GMT
Links: << >>  << T >>  << A >>
In article <5gnq2p$k94@beirdo.uplink.on.ca> gjhurlbu@beirdo.uplink.on.ca (Gavin Hurlbut) writes:
>From: gjhurlbu@beirdo.uplink.on.ca (Gavin Hurlbut)
>Subject: Re: Xilinx 4002 RAM Question
>Date: Wed, 19 Mar 1997 04:29:13 GMT

>Peter Alfke (peter@xilinx.com) wrote:
>> In article <L3ZHANG.18.3324A6E7@ELECOM2.watstar.uwaterloo.ca>,
>> L3ZHANG@ELECOM2.watstar.uwaterloo.ca (Louis Zhang) wrote:
>> 
>> 
>> > Unfortunately, unlike the discrete RAM and RAM cell in ASIC, the RAM cell in 
>> > Xilinx 4000 has address and data setup/hold time requirements. 
>> 
>> Whenever I read "hold time" my blood pressure goes up 10 mm.
>> The XC4000E data sheet lists hold time as 0, i.e. ZERO.
>> So, don't worry about hold time. And EVERY clocked device has a set-up time.

>Unfortunately, the prototype board (BORG board) that Louis (and myself -- in
>the same class) is required to use in his project contains (interconnected
>to each other and interfaced to a PC via an ISA card connected to one of
>the 4002 chips):

>        2 x 4002APC-6
>        2 x 4003APC-6

>At least that is what we were told.  So the specs of the 4000E series
>unfortunately do not apply.  :)

Gavin was right about the Xilinx devices that we are using; they are NOT
4000E and that's why I was trying to make a Sync RAM from the Async RAM
in 4000A.

So I was really talking about the setup/hold time of the Asyncrhonous
RAM in XE4000.  This is the setup/hold time of the Address with respect
to WE (NOT clock, since there's no clock in an Async RAM).  On page 8-128 
to 8-129 of the Xilinx 1994 Data Book, it has a comparsion chart between 
Xilinx (Async) RAM and the discrete RAM.  It states that in Xilinx RAM, 
the address MUST have 2ns setup AND hold time with respect to WE.  While on
the same page, it states the setup/hold time for discrete RAM can be 
0ns (ie. ZERO) minimum.  I checked up a Cypress data book and its Async 
RAM also have minimum 0ns address setup/hold time with respect to WE.  
Therefore, it's possible that the address and WE can be clocked on the 
same cycle for a discrete RAM, while I must provide address setup AND hold 
time (with respect to WE) for Xilinx RAM, which potentially costs me a 
extra cycle (the clock here is the clock used for our design, NOT for 
the Xilinx Async RAM) for doing so.  That's why I ended up just using 
the Async RAM and got the project work.   

Please feel free to correct me if I am wrong.  Thanks again for all 
of your suggestions.


------------------------------------------------------------------------------
Louis Zhang
4B Electrical Engineering
University of Waterloo

Article: 5854
Subject: Re: Sole source
From: rick@camden.algor.co.uk (Rick Filipkiewicz)
Date: 20 Mar 1997 18:57:30 GMT
Links: << >>  << T >>  << A >>

Much worse than not having a second source for the physical parts is having 
the FPGA vendor as the only source for the Place&Route tools. Its like always 
having to buy a Pentium assembler from Intel, a PowerPC one from Motorola,
 etc. 

This would not be tolerated in the software world so why do we poor h/w folk
have to put up with it?

 _________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England

Article: 5855
Subject: Cisco's SIBU is looking for ASIC and Systems Engineers
From: lshevock@diablo.cisco.com (CISCO SYSTEMS)
Date: 20 Mar 1997 19:01:09 GMT
Links: << >>  << T >>  << A >>
I am with Human Resources for the Small Internetworks Business Unit
(formerly Grand Junction) at Cisco Systems.  We develop switches, routers,
and hubs that focus on small and medium-sized companies.  Revenue-wise we
are the fastest growing Business Unit at Cisco Systems with 30+% growth
over the last five quarters.  

We are currently looking for senior and intermediate ASIC Engineers
(digital) as well as senior and intermediate Systems Engineers (embedded
CPU, FPGA) to join our team.  We are located in San Jose, California.

If you, or anyone you know is interested, please contact me or send me
your resume.  I will be happy to talk with you further about the
positions.

To send your resume:
fax:  408-527-8048 or
email:  lshevock@cisco.com
No agencies please

-- 
To send your resume:
fax:  527-0180 or
email:  lshevock@cisco.com
No agencies please
Article: 5856
Subject: Re: Is this really possible?
From: Roger Kinkead <roger@rkhost.demon.co.uk>
Date: Thu, 20 Mar 1997 19:23:33 GMT
Links: << >>  << T >>  << A >>
In article: <33315AAB.3416@ids.net>  Ray Andraka <randraka@ids.net> writes:
> 
> Kent wrote:
> 
> > I am curious to know if anyone else has been able to instantiate a basic 
50
> > Mips processor in less than 10% of a 3090, or a "vector processor" in a
> > little more than 200 CLBs. Is there some big secret about the 3090 you
> > guys have been keeping quite, or is there something I am missing here?
> 
> No big secret.  The design is just well tailored to the FPGA
> architecture.  I suspect the 'nanoprocessor' is a simple RISC engine
> (very few instructions) with hooks to permit specialized instructions to
> be added.  
<SNIP>

If anyone is interested, it is possible to view/download/print patents at IBM
patent server (www.ibm.com/patent I think it is?).  Along with other
interesting things, you can pull down Metalithic's 5,361,373 patent which may
explain many things to you.

Hope at least some of this helps.


Roger
-- 

-----------------------------------------------------------------------------
   Roger Kinkead                           EMAIL: roger@rkhost.demon.co.uk   
   "Moorcroft", 27 Antrim Road, Lisburn,County Antrim, Northern Ireland
-----------------------------------------------------------------------------


Article: 5857
Subject: Re: Is this really possible?
From: peter@xilinx.com (Peter Alfke)
Date: Thu, 20 Mar 1997 13:22:07 -0700
Links: << >>  << T >>  << A >>
In article <5gqeo1$k50@agate.berkeley.edu>, nweaver@hum.cs.Berkeley.EDU
(Nicholas C. Weaver) wrote:
 So all the computing bandwidth in the world doesn't do any
> good!  Who CARES how much processing they can get out of those two
> 3090s, when you cant get the data into the card?
> 
Maybe there was some hype, but there is also astounding performance, and
it is achieved by dynamically reconfiguring the XC3090.
Don't brush this off as just hype, or just a niche product. It's a very
clever use of the parallel processing power of hundreds of logic blocks
working in parallel, rather than a single ALU having to do all the work.
 
There are other applications in DSP where one SRAM-based FPGA can beat any
dedicated high-end DSP chip from a certain company in Texas, and beat it
by a wide margin.

Never underestimate what hundreds and thousands of simple little engines (
CLBs ) can do, when they work concurrently, especially when you can modify
them on-the-fly. It's just new, and it takes some unconventional thinking.


Peter Alfke, Xilinx Applications
Article: 5858
Subject: Re: Is this really possible?
From: dbuckley@esl.tex.com (David Buckley)
Date: Thu, 20 Mar 97 20:22:17 GMT
Links: << >>  << T >>  << A >>
In article <01bc34c8$a1e53d30$0a2e36ce@infinity> "Kent" <address_withheld@my.discression> writes:
> I just read about this in a back issue of EDN magazine (online- December
> 19, 1996).
> 
> [ snip ]
> 
> Metalithic aims Digital Wings for Audio at "prosumers"--professional and
> private musicians who cannot afford a studio, according to Gilson. The
> system features 64-voice synthesis (with only two voices currently
> implemented); software; and an optional, $300 professional breakout box.
> The company based the system on the "Wingware" reconfigurable-computing
> system, which comprises an operating system; a tool set; an assembler; a
> function library that enables reconfigurable computing on FPGAs; and a
> "nanoprocessor," a Metalithic-patented configurable RISC processor. The
> nanoprocessor motors through simple operations and uses instruction-set
> extensions to perform complex processing operations that would otherwise
> slow a system. 
> 
> Two Xilinx 3090s, each having 320 configurable logic blocks (CLBs), form
> the processing engine. The basic nanoprocessor takes 28 CLBs, or less than
> 10%, to instantiate the basic core processor at 50 MIPS, leaving 160 CLBs
> for Musical Instrument Digital Interface (MIDI), UART, I/O, ISAbus,
> synthesizer, telephone, and crystal-codec interfaces, along with about 15
> instructions. The other 3090 uses a little more than 200 CLBs to provide
> the vector processor that performs the multiply accumulates, linear
> interpolation, and table look-up for the synthesizer engine. 
> 
> [ snip ]
> 
> I am curious to know if anyone else has been able to instantiate a basic 50
> Mips processor in less than 10% of a 3090, or a "vector processor" in a
> little more than 200 CLBs. Is there some big secret about the 3090 you
> guys have been keeping quite, or is there something I am missing here?

Sitting in the Old Mags pile I have Electronics and Wireless World, sep,
oct, nov 1985, in whioch is published a design for a digital polyphonic
keyboard called digipoly.  8 simultaneous voices.

This has a "discrete high speed TTL processor", which implements ten
instructions, and runs at about 20 mips.  Being discrete, it lives in
TTL ICs, and the count goes up to IC34. You have:

2       181
3       161
3       373
2       374
2       244
1       245
1       154
1       157

A dozen or so each of inverters, flip-flops, nands, a couple of xor and
thats it.  Oh and a 2K RAM, a small prom, and a D/A.  First time I've
looked at it really, it's harvard archetecture.

So thats the challange.


--
----------------------------------------+------------------------------------
David Buckley of Electric Solutions Ltd | Email: dbuckley@esl.tex.com
 Services to the Computing,Electronics  |
  and Entertainment industries.         |
Calling from South London, in the UK    |
-----------------------------------------------------------------------------

Article: 5859
Subject: Re: VHDL & ABEL synthesis tools on 95/NT
From: pngai@adobe.com (Phil Ngai)
Date: 20 Mar 1997 13:46:18 -0800
Links: << >>  << T >>  << A >>
> Todd A. Kline wrote:
>...  I also have doubts about DataIO's commitment to EDA
> products.  

We're not a very large site for them (4 seats) but they come down
from WA at least once a year to talk to us, so I think they're
pretty interested in the market.

I was at a focus group dedicated to the question of what should
the business be called when DataIO spun off the EDA division as
a separate company.

Since the spin off, technical support has gotten really good.

-- 
	Another Popular Mechanics kind of guy...
Article: 5860
Subject: Re: Development board with multiple FPGAs
From: Steve Nordhauser <nords@intersci.com>
Date: 20 Mar 1997 16:17:01 -0700
Links: << >>  << T >>  << A >>
Richard Schwarz wrote:
> 
> Stuart Clubb wrote:
> 
>   Try Aptix at:
>   http://www.aptix.com
> 
>   Probably not cheap, but looks_real_nice. :-)
> 
>  Take a look at
> http://www.erols.com/aaps .
> 
> The ST-FPGA module has 4 XILINX 208pin QFP chips and a ton of IO pins.
> The board was originally developed for ASIC design testing.You can put
> whatever type chips you want on the boards.

I'm using a board from Giga Operations that is very expandable.
Their support is excellent and the features are very useful.
http://www.gigaops.com

Steve Nordhauser
Article: 5861
Subject: Re: Multiple clocks in Xilinx
From: daveb@iinet.net.au_spam_trap (David R Brooks)
Date: Thu, 20 Mar 1997 23:46:56 GMT
Links: << >>  << T >>  << A >>
z80@dserve.com (Peter) wrote:

[snip]
:Quite. In fact a shift reg merely assumes that the clock skew is less
:than the clock-Q propagation delay. 
:
:This is easily achieved when using global clock nets, but very hard
:when the clock is routed through switches. It actually used to be easy
:to achieve with e.g. the old 3064 but not with the 3064A.
:
 When the clock distribution is subject to delays, one solution is to
route the clock against the signal flow. That is, from the clock
source, to the final FF in the signal chain, then to its predecessor,
and so on. This way, so long as the total signal delay (plus setup
time) does not approach a full clock period, its safe.
 Of course, this will likely mean getting your hands real dirty in
terms of low-level layout stuff, but that's life.


--  Dave Brooks    <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
    "From" line rigged to foil spambots: daveb <at> iinet.net.au
Article: 5862
Subject: FPGA and PLL
From: A.Cosic@eee.utas.edu.au (Alec Cosic)
Date: Fri, 21 Mar 1997 00:23:15 GMT
Links: << >>  << T >>  << A >>

I have found PHD disertation from Germany desribing  PLL implementation using 
FPGA. I have lost its WWW site. Only what I know is that it was from Germany 
in 1995.


Can somebody help me?

Thanks in advance


A. Cosic
Article: 5863
Subject: FIFOs
From: Greg Quintana <gregq@sr.hp.com>
Date: Thu, 20 Mar 1997 19:31:17 -0800
Links: << >>  << T >>  << A >>
Anyone have equations for FIFOs that could be used in a xilinx part?
-- 

						Greg Quintana
Article: 5864
Subject: FPGA CLB USAGE
From: Samir Marc Falaki <Samir_Marc_Falaki@uqtr.uquebec.ca>
Date: Fri, 21 Mar 1997 04:09:44 GMT
Links: << >>  << T >>  << A >>
Hi all,

I recently synthesized some VHDL on Synopsys targetting the
Xilinx 4010 FPGA.  I want to find out how many CLBs it uses
but I have to generate a report for each module (instance) seperately 
and then add them up.  Does this give a pretty accurate estimate
of the total cell usage.  The reason I'm asking this is that I seemed
to think that CLBs could be shared by different modules if they
are underutilised.  Is this correct?

Sam Falaki

University of Quebec in Trois-Rivieres
Dept. Electrical Eng.
Article: 5865
Subject: RENOIR DEMO CD
From: Samir Marc Falaki <Samir_Marc_Falaki@uqtr.uquebec.ca>
Date: Fri, 21 Mar 1997 04:25:16 GMT
Links: << >>  << T >>  << A >>
Hi,

I am by no means posting this article to put Mentor but I thought
this was too funny.  I use Mentor and find that I always come across
problems requiring patches or work-arounds for some reason.  If it's
not that, it's problems with paths and pointers pointing at pointers
pointing etc...  Anyhow, I made a request for the free evaluation of
"Renoir" which I thought I could run on my mom's PC.  I thought that
it would probably be straightforward to use.  Today I got a demo
CD.  They send you this CD first, and then you ask for the evaluation
kit.  Well, the demo CD installs fine but when I run it I get some
kind of "invalid date" error right from the start (something to do 
with a .ilm file).  I said to myself, "ahh yes, Mentor". If the demo 
CD doesn't work, how do they expect people to have confidence in their
software?  What the hell are they doing at Mentor?  They have all these
powerful tools but they always have these stupid little problems.

Sam
Article: 5866
Subject: BIT SERIAL MULTIPLY
From: Samir Marc Falaki <Samir_Marc_Falaki@uqtr.uquebec.ca>
Date: Fri, 21 Mar 1997 04:45:11 GMT
Links: << >>  << T >>  << A >>
Hi,

I read somewhere (one of Ray Andraka's articles I believe) about using
bit serial multiply to implement a tap filter on an FPGA.  What I don't
quite understand is how one can impose an architecture into an FPGA
when using high level tools.  I implemented a 16X16 bit multiply
today via behavioural VHDL on Synopsys and got about 120 CLB usage
for a 4010 Xilinx device.  Any tips would be appreciated and on 
implementing signal processing algorithms on FPGAs in general.  Thanks
in advance.

Sam Falaki
Article: 5867
Subject: Re: BIT SERIAL MULTIPLY
From: Andreas Kugel <kugel@mp-sun1.informatik.uni-mannheim.de>
Date: Fri, 21 Mar 1997 08:05:34 +0100
Links: << >>  << T >>  << A >>
Samir Marc Falaki wrote:
> 
> Hi,
> 
> I read somewhere (one of Ray Andraka's articles I believe) about using
> bit serial multiply to implement a tap filter on an FPGA.  What I don't
> quite understand is how one can impose an architecture into an FPGA
> when using high level tools.

Sam,
You have to leave your behavioural description and use a
structural (rtl) description instead. 
You have all Xilinx primitives like fliplops, iobufs, clbs, etc
at hand in the synopsys libraries - look into the XSI interface
manual.
If you could draw the schematic then you could also create
the same architectur by instantiating primitives in VHDL.

However I would recommend to use a synthesis tools with
libraries and strategies powerful enough to enable behavioural
description with sufficent performance.
Your current tool might not be the one.


I came accross some DSP like libraries on the XIlinx website.
Did you checked those out ?


Andreas

-- 
Andreas Kugel - University of Mannheim - Dept. of Computer Science V
B6,26 - 68131 Mannheim - Germany
Phone:+(49)621 292 1634 - Fax:+(49)621 292 5756
e-mail:kugel@mp-sun1.informatik.uni-mannheim.de
Article: 5868
Subject: What tools for $8000?
From: "Anthony Ellis" <aelogic@iafrica.com>
Date: 21 Mar 1997 08:02:12 GMT
Links: << >>  << T >>  << A >>
Given that I have $8000 to spend on tools and want to do the following:

	FPGA VHDL development - just the VHDL coding, debugging and simulating.
Independent of FPGA vendor. 
	Will use customer's back end tools as required. Typical VHDL design
bureau.
	
	Front end schematic capture tools to interface with Coopers&Cyan  as  well
as PCAD PCB tools.

I currently use Workview Office tools and Speedwave. Need tools for my own
business now and would like some alternatives. 
Any recommendations?

Anthony "LogicWorks" 
Article: 5869
Subject: Re: Is this really possible?
From: Roger Kinkead <roger@rkhost.demon.co.uk>
Date: Fri, 21 Mar 1997 09:23:11 GMT
Links: << >>  << T >>  << A >>
In article: <2262658wnr@rkhost.demon.co.uk>  Roger Kinkead 
<roger@rkhost.demon.co.uk> writes:
> 
> If anyone is interested, it is possible to view/download/print patents at 
IBM
> patent server (www.ibm.com/patent I think it is?).  Along with other
> interesting things, you can pull down Metalithic's 5,361,373 patent which 
may
> explain many things to you.

http://patent.womplex.ibm.com/


Roger
-- 

-----------------------------------------------------------------------------
   Roger Kinkead                           EMAIL: roger@rkhost.demon.co.uk   
   "Moorcroft", 27 Antrim Road, Lisburn,County Antrim, Northern Ireland
-----------------------------------------------------------------------------


Article: 5870
Subject: 8-bit divider in FPGA
From: Johannes Soelhusvik <jso@nocrc.abb.no>
Date: Fri, 21 Mar 1997 11:10:10 +0100
Links: << >>  << T >>  << A >>
Does anyone have a simple solution to the design of an 8-bit simple
divider (A=B/C, A,B and C being 8-bit variables) for a xilinx FPGA
(xc4000 series). The circuit must take up as little space as possible
(bit serial solution?).


-- 
Johannes Sølhusvik
ABB Corporate Research
Electronic Systems Dept.
P.O. Box 90
N-1361 Billingstad
Norway
Tel: +47 66 84 34 28
Fax: +47 66 84 35 41
Email: jso@nocrc.abb.no
Article: 5871
Subject: Re: Multiple clocks in Xilinx
From: steve goodwin <steve@p2cl.demon.co.uk>
Date: Fri, 21 Mar 1997 10:18:55 GMT
Links: << >>  << T >>  << A >>
In article: <3332f069.55925897@news.alt.net>  z80@dserve.com (Peter) writes:
> Quite. In fact a shift reg merely assumes that the clock skew is less
> than the clock-Q propagation delay. 
> 
> This is easily achieved when using global clock nets, but very hard
> when the clock is routed through switches. It actually used to be easy
> to achieve with e.g. the old 3064 but not with the 3064A.
> 

could you elaborate a little please, i don't understand and i'd like to as it
means i don't understand the difference between the 2 architectures. i'm
currently using some A's with bit streams designed for non-A's and
you have worried me!

-- 
steve goodwin


Article: 5872
Subject: Problem loading XC4010E with XCHECKER!
From: FT/KD Patrik Eriksson <emwepa@kiemw.ericsson.se>
Date: Fri, 21 Mar 1997 13:54:32 +0100
Links: << >>  << T >>  << A >>
When i try to configure one XC4010E with XCHECKER something goes wrong.
It seems as at the end of the cofiguration the FPGA drives INIT low.
What can be wrong?

-- 
Ericsson Saab Avionics AB  Telephone: +46 8 757 30 00
Torshamnsgatan 32C            Direct: +46 8 757 30 00
Kista                        Telefax: +46 8 404 41 20  
S-164 84 STOCKHOLM            E-mail: Patrik.E.Eriksson@emw.ericsson.se
Article: 5873
Subject: Re: Sole source
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Fri, 21 Mar 1997 14:18:24 GMT
Links: << >>  << T >>  << A >>
In article <peter-1903971555490001@appsmac-1.xilinx.com>,
Peter Alfke <peter@xilinx.com> wrote:
>A single source must and will use multiple fab lines ( to protect against
>accidents ) and must be forthcoming in price reductions. I think we in the
>FPGA world have done that...

Tell that to Altera's FLASHlogic customers.  Incidentally, how many price
reductions have there been on Xilinx's development software lately?

The biggest reason why the customers do still like having second sources
is that it insulates them from the management whims of a sole supplier. 
Sure, Intel will deliver... but will it deliver the parts you want?  Or
will it decide, to pick a purely hypothetical example :-), that it won't
ship Pentiums at more than 200MHz because that would compete with the
Pentium II (which they annoyingly decided wouldn't be socket-compatible
with anything that came before)?
-- 
Committees do harm merely by existing.             |       Henry Spencer
                           -- Freeman Dyson        |   henry@zoo.toronto.edu
Article: 5874
Subject: Re: 8-bit divider in FPGA
From: Pasquale Corsonello <pascor@ccusc1.unical.it>
Date: Fri, 21 Mar 1997 17:14:39 +0100
Links: << >>  << T >>  << A >>
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Johannes Soelhusvik wrote:
> 
> Does anyone have a simple solution to the design of an 8-bit simple
> divider (A=B/C, A,B and C being 8-bit variables) for a xilinx FPGA
> (xc4000 series). The circuit must take up as little space as possible
> (bit serial solution?).
> 

I think SRT algorithm is suitable. We use an XC4003 for SRT divider with
8 bit operands and 22 bit quotient.
The main design parameter is the throughput rate required.
I can give you more suggestions.

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*********************************************************
*Pasquale Corsonello  Microelectronic Design Laboratory *
*Department of Electronic Computer Science and System   *
*University of Calabria                                 *
*Loc. Arcavacata di Rende - RENDE (CS) - 87036-ITALY    *
*Tel:+39 984 494708 Fax:+39 984 494713                  *
*email:pascor@ccusc1.unical.it-corsone@nwdeis1.unical.it*
*********************************************************


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