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Messages from 6150

Article: 6150
Subject: Re: PCI Reset Spec...
From: "Austin Franklin" <darkroom1@ix.netcom.com>
Date: 18 Apr 1997 14:39:33 GMT
Links: << >>  << T >>  << A >>
>  The 1ms trst spec doesn't apply to
> the Xilinx configuration, it doesn't use the PCI reset, or the PCI clock.

Unless you 'inadvertently' hook the /PROGRAM pin to the PCI reset...and
certainly don't hook the /INIT pin up to the PCI reset signal...

Austin Franklin
..darkroom@ix.netcom.com.

Article: 6151
Subject: Re: Pentium Pro Worth it for Altera Max Plus?
From: Daniel Alley <dana@xetron.com>
Date: Fri, 18 Apr 1997 16:08:00 GMT
Links: << >>  << T >>  << A >>

Grason Curtis wrote:
> 
> Keith Blei wrote:
> >
> > I'm wondering what will  reduce compilation time more. Available
> > memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium.
> > Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized.
> > Compilation currently takes around an hour.
> >
> > Considering, Pentium Pro 200 and 64 MB.
> > Anybody have any practical experience in this area?
> > TIA,
> > Keith
> 
> Both available memory and processor speed will enhance your performance,
> however, from data I have seen, increasing the available memory has the
> most dramatic effect on Mr. Gate's operating system.  I would suggest
> you first upgrade to 128MB of RAM.  You should see a significant
> improvement.  I forget the exact numbers so I can't quote them here, but
> a benchmark I saw was something like a P5-133 with 2X memory is
> equivalent to a P5-200 with 1X memory.  I believe this was for a WinNT
> platform.  Maybe someone else has seen data which is similar.  Bottom
> line, memory has the most immediate effect.
> 
> Regards...Grason


FWIW - I converted from an older 486-66 with 32 MB to a P200 with 128
MB.   80% loaded 10K50 compile times went from 80 minutes to under 10
minutes!!  I suspect the most improvement was for the memory, with older
system continuously file swapping during the latter stages of compile. 
Report files show up to 59 MB used by fitter, so 64MB may not be enough.
Article: 6152
Subject: Re: PCI Reset Spec...
From: wen-king@myri.com (Wen-King Su)
Date: 18 Apr 1997 11:45:36 -0700
Links: << >>  << T >>  << A >>
In a previous article "Austin Franklin" <darkroom1@ix.netcom.com> writes:
:
;>  The 1ms trst spec doesn't apply to
:> the Xilinx configuration, it doesn't use the PCI reset, or the PCI clock.
;
:Unless you 'inadvertently' hook the /PROGRAM pin to the PCI reset...and
;certainly don't hook the /INIT pin up to the PCI reset signal...

The point is you have to observe that 1ms spec to be fully compliant.
There is no specified minimum delay between power-on and first access of
the bus other than the 1ms spec.  I am quite puzzled by the "100ms typical"
marking on the graph in the spec book, for without a guaranteed minimum,
it has no meaning.  BIOS isn't required in all systems with PCI bus, and
it is perfectly OK for them to access the bus right after the 1ms reset delay. 
Article: 6153
Subject: FLEX 8000 FPGA Configuration
From: "Jacques Pelletier" <jpelletier@domosys.com>
Date: 18 Apr 1997 19:57:55 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm searching for an algorithm for programming the configuration of a FLEX
8000 device. I use a EPF8282ATC100-4 with the Passive Parallel Synchronous
scheme.

The application note AN33 from Altera is not clear about what we are
supposed to do after programming the data bytes. I send 5120 bytes and 8
clock pulses on DCLK for each byte: after that, the application note talks
about an additional 10 pulses.

I tried sending the 10 pulses but I have one configuration that is loading
properly, and another one that does not seem to load properly (after all
the DCLK pulses, the CONFIG_DONE line is still low.

Jacques Pelletier
jpellet@domosys.com

Article: 6154
Subject: Re: Pentium Pro Worth it for Altera Max Plus?
From: terry.harris@dial.pipex.com (Terry Harris)
Date: Fri, 18 Apr 1997 20:41:07 GMT
Links: << >>  << T >>  << A >>
Grason Curtis <gcurtis@postoffice.worldnet.att.net> wrote:

>Keith Blei wrote:
>> 
>> I'm wondering what will  reduce compilation time more. Available
>> memory or Processor. Currently have 48 MB, NT 4, 100 Mhz Pentium.
>> Altera 10K50 and 10K70 design ( soon ). Both about 75% utilized.
>> Compilation currently takes around an hour.
>> 
>> Considering, Pentium Pro 200 and 64 MB.
>
>Both available memory and processor speed will enhance your performance,
>however, from data I have seen, increasing the available memory has the
>most dramatic effect on Mr. Gate's operating system

NT has a system monitor so look at it. During a build you can watch
the amount of swap file/disk/paging activity - if it thrashes more
memory will help a lot - if it isn't thrashing more memory will do sod
all.

My experience with processor bound 32 bit applications under Win 95 is
a PPro 200 is a little over twice the speed of a P133, under NT4 I
would expect the improvement to be a little better again. 


Cheers Terry...
Article: 6155
Subject: FPGA gate counting: No truth in advertising
From: kevintsmith@compuserve.com
Date: Fri, 18 Apr 1997 17:41:20 -0600
Links: << >>  << T >>  << A >>
Dear comp.arch.fpga,

Forgive me for beating a dead horse, but since no one
responded to david@lowrance's challenge to explain gate counting
methodology I'll start a new thread to put in my $.02.

He was citing Xilinx and Actel for having unrealistic estimates,
and seemed to have a good understanding of where the marketing
department got their numbers and why they didn't always jibe with
reality.

Since he invited FAEs to present their side of the story, I'll
launch into this electronic seminar guilt-free!

QuickLogic's pASIC1 family counts gates as the minimum usable
content of a logic cell.  A pASIC1 logic cell has a wide fan-in
PAL-like stage, followed by muxes into a D flip-flop.  The total
number of 2-input NAND gates in a logic cell is 31.  The usable
portion is estimated at 11, roughly a third.

We count gates from *every* logic cell because our abundant,
low-impedance routing allows to use *every* logic cell (honest!).
Therefore, our pASIC1 lineup looks like this:

pASIC1 device    # logic cells    2-input NANDs    usable gates
QL8x12B              96              2,976             1,056 (1k)
QL12x16B            192              5,952             2,112 (2k)
QL16x24B            384             11,904             4,224 (4k)
QL24x32B            768             23,808             8,448 (8k)

The pASIC2 family actually squeezes more logic into fewer logic
cells by pulling a stunt with fragmentability.  This means that
each logic cell can either be used as a unit for complex SOP or
decoding operations, or the software can pick off a small part of
the logic cell, leaving the rest for another portion of logic to
utilize.  Each cell has 5 independent outputs for this kind of usage.
Since our routing resources are plentiful and fast, we don't suffer
a speed penalty for doing this.  There are now about 40 NANDs per
logic cell, with an estimated 16 minimum usable.

As an added bonus, our pASIC2 logic cell's fragmentability makes
the parts more suitable to Synthesis with tools like Synopsys,
Synplicity, Exemplar, and DesignWare.  We get results that keep
engineers from having to use any hand-designed macros.  But when
they need to, the process is straightforward, utilizing optimized
macros in schematic that can be netlisted to HDL to get speeds like
180MHz+ for a 24-bit loadable counter.

pASIC2 device # logic cells  2-input NANDs  usable gates
QL2003           192            7,680         3,072 (3k)
QL2005           320           12,800         5,120 (5k)
QL2007           480           19,200         7,680 (7k)
QL2009           672           26,880        10,752 (10k) misnamed?

As we go higher densities, we have no architectural limit to the
amount of routing resources we can add because our routing is all
between metal layers.  Therefore, as gate counts go up speed, routability,
and ease of use remain constant as QuickLogic's claims to fame.

Our new fab agreement with TSMC at .35u will enable parts with 20k
usable gates and more.
---
Keb'm

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6156
Subject: Re: PCI Reset Spec...
From: "Austin Franklin" <darkroom1@ix.netcom.com>
Date: 19 Apr 1997 00:01:52 GMT
Links: << >>  << T >>  << A >>
>  BIOS isn't required in all systems with PCI bus, 

I don't understand why you would say that.  How would the configuration
cycles get done?

Austin

Article: 6157
Subject: Re: Pentium Pro Worth it for Altera Max Plus?
From: gzs@explorer2.clark.net (George)
Date: 18 Apr 1997 20:48:58 -0400
Links: << >>  << T >>  << A >>

>Both available memory and processor speed will enhance your performance,

how about these dual or quad pentium or pentium-pro boards

is it realistic to expect a speedup for the Altera or Xilinx
  software compared with the uni-processor machines if running
  NT - (im a unix person I do not know what kind of multi-tasking
  NT really has for running other jobs simultaneously)

or are the bottlenecks primarily memory bandwidth?

and how do the P200 or PP200 compare against the sparc machines

thanks

-george
 gzs@clark.net

Article: 6158
Subject: Re: PCI Reset Spec...
From: "Steven K. Knapp" <optmagic@ix.netcom.com>
Date: 19 Apr 1997 00:58:44 GMT
Links: << >>  << T >>  << A >>
Again, I think we need to clarify the difference between Power-On Reset and
a System Reset with the system active.

What is the fastest time between power-on before the system processor
starts doing configuration cycles over the bus?  The spec. seems to be
vague about any real requirements in this area.

Can the processor even boot itself in less than 1 ms (Power-On Reset)?

After configuration, a SRAM-based FPGA can handle a system reset and
respond in far less that 1 ms.

-- 
Steven Knapp
OptiMagic(tm) Logic Design Solutions
E-mail:  optmagic@ix.netcom.com
Programmable Logic Jump Station:  http://www.netcom.com/~optmagic

Wen-King Su <wen-king@myri.com> wrote in article
<5j8fgg$jeu@neptune.myri.com>...
| In a previous article "Austin Franklin" <darkroom1@ix.netcom.com> writes:
| :
| ;>  The 1ms trst spec doesn't apply to
| :> the Xilinx configuration, it doesn't use the PCI reset, or the PCI
clock.
| ;
| :Unless you 'inadvertently' hook the /PROGRAM pin to the PCI reset...and
| ;certainly don't hook the /INIT pin up to the PCI reset signal...
| 
| The point is you have to observe that 1ms spec to be fully compliant.
| There is no specified minimum delay between power-on and first access of
| the bus other than the 1ms spec.  I am quite puzzled by the "100ms
typical"
| marking on the graph in the spec book, for without a guaranteed minimum,
| it has no meaning.  BIOS isn't required in all systems with PCI bus, and
| it is perfectly OK for them to access the bus right after the 1ms reset
delay. 
| 
Article: 6159
Subject: Re: PCI Reset Spec...
From: "Austin Franklin" <darkroom1@ix.netcom.com>
Date: 19 Apr 1997 01:13:36 GMT
Links: << >>  << T >>  << A >>
>  BIOS isn't required in all systems with PCI bus, and
> it is perfectly OK for them to access the bus right after the 1ms reset
delay. 

I know that every PCI board I have designed (6 total) is going in a system
with a BIOS that will run at least 200+ms of code before going out and
doing configuration cycles.  It is therefore guaranteed that a Xilinx will
work fine for every application I have done so far.  No one has ever given
me a requirement to develop a board that needs to run in anything other
than this condition.

If you have an application that has a different requirement, then you
cannot use a Xilinx FPGA if you are going to meet the 1ms reset spec.  Your
only solution is a programmed part of an ASIC.

Austin Franklin
..darkroom@ix.netcom.com.

Article: 6160
Subject: Low budget effort for JTAG EXTEST assembly test.
From: "Alvin E. Toda" <aet@lava.net>
Date: Fri, 18 Apr 1997 22:05:34 -1000
Links: << >>  << T >>  << A >>
I thought to re-post the following to get more 
comment and replies on the subject of a low cost 
system for a low budget effort to do assembly 
testing on high density boards with the JTAG 
EXTEST instruction. 

For a stuck-at fault model of the nets on the 
board a small number of patterns can be used, 
because the nets can be tested concurrently for 
two logic states-- say two scan patterns.  

However, a more realistic model of faults is to 
check for shorts because the leads of the board 
devices are in close proximity-- and solder 
could short leads together. Also, another 
realistic model is to check for open, or 
continuity of the wire because the solder could 
be bad. In these two cases the number of scan 
patterns could be large because only one driver 
at a time could be tested-- all others set to 
the other logic state. 

For example, for a board with an estimated 700 
nets, about 1400 scan patterns might be 
required. But this number may still be low 
enough to show some value with the technology.

Surely, this has been done. Perhaps this is the 
first thing a small company does to test the 
technology?? An added question: with good 
control over the board design and test system, 
can't the power supply current be monitored to 
check for shorts during the test?


########################################################################
Alvin E. Toda				aet@lava.net
sr. engineer				Phone: 1-808-455-1331

2-Sigma			  	WEB: http://www.lava.net/~aet/2-sigma.html
1363-A Hoowali St.
Pearl City, Hawaii, USA

Article: 6161
Subject: Re: PCI Reset Spec...
From: wen-king@myri.com (Wen-King Su)
Date: 19 Apr 1997 09:02:30 -0700
Links: << >>  << T >>  << A >>
In a previous article "Steven K. Knapp" <optmagic@ix.netcom.com> writes:
:
;Again, I think we need to clarify the difference between Power-On Reset and
:a System Reset with the system active.
;
:What is the fastest time between power-on before the system processor
;starts doing configuration cycles over the bus?  The spec. seems to be
:vague about any real requirements in this area.
;
:Can the processor even boot itself in less than 1 ms (Power-On Reset)?
;
:After configuration, a SRAM-based FPGA can handle a system reset and
;respond in far less that 1 ms.

The root of the confusion is a diagram in the spec that together with
a table of delay values says this:


system power     :  ___/===============================

                       | <--- 100 ms typical --->|
power good signal:  xxxxx________________________/======

                                       |<------->| 1ms minimum
reset            :  xxxxxxxxxxxxxxxxxxxx_________/======

Between the time the power reaches the operational level and the time
when the mystical "power good" signal is asserted, a figure of 100ms
typical is given.  I call it mystical because it is not a signal on the
PCI bus, and have no idea why it was in the spec at all.  I have also no
idea why a typical value is given, but not a minimum.  Failing to state
the minimum makes it meanless.  So all I am left with is that the bus is
guaranteed not to be accessed while it is in reset, which is guaranteed
to last for only 1ms. 

The spec doesn't say PCI bus systems need a processor at all, so the
question of whether a processor can boot itself in less than 1ms is moot.
Certainly a processor can easly complete its own internal reset in less
than 1ms, and the first thing it might do after that might be to probe
the bus for boot devices.  This might not be the case for pc's with the
more popular BIOS implementations, but devices that doesn't reach
operational state in 1ms is still non-conforming.

I would fully support that we ammend the spec by adding a guaranteed
minimum, or by providing a shared signal that devices can hold low
while they are in the process of initializing themselves.
Article: 6162
Subject: Re: PCI Bus Problems
From: richard@ucmsj.vatech.com (RT)
Date: Sat, 19 Apr 1997 09:28:06 -0700
Links: << >>  << T >>  << A >>
I jumped in at the end of this - but there are IP developers who have
successfully put PCI Target interfaces into the EPM7256S (PLD Applications
in France being one) which would fit your requirement for non-volatility.

Richard Terrill
Altera Corporation

In article <5iq681$aht@wallaby.digideas.com.au>,
graeme@wallaby.digideas.com.au (Graeme Gill) wrote:

> Austin Franklin (#darkroom@ix.netcom.com#) wrote:
> : Isn't that two chips?  If you did the PCI interface in the FPGA, then that
> : would be one chip?
> 
> Except that you can't use an 8k or 10K for this. The PCI interface has
> to be non-volatile, or it won't meet the PCI specs.  (There has
> to be enough of a PCI inteface there immediatly after powe-on/reset, to
> respond to config space cycles with a retry.)
> 
>         Graeme Gill.
Article: 6163
Subject: Re: Exponential function architecture
From: Ray Andraka <randraka@ids.net>
Date: Sun, 20 Apr 1997 21:48:09 -0400
Links: << >>  << T >>  << A >>
Mourad Aberbour wrote:
> 
> Hi there,
> Did anybody had any experience with designing an architecture for
> the computation of the exponential function?
> I would appreciate any kind of help.
> 
> regards,
> --

You can compute the exponential using the CORDIC algorithm, or more
efficiently with a CORDIC-like algorithm that works on an incremental
expression of the exponential.  The CORDIC algorithms are iterative
shift-add algorithms useful for computation of trig, inverse trig,
hyperbolic and inverse hyperbolic, square roots and other functions. 
Generally speaking, the results improve by one bit for each iteration
(the exponent is an exception).

I have extensive experience using the CORDIC algorithm, including design
of a log/exponential.  I've got one paper on my website that discusses a
bit serial construction of a CORDIC vector magnitude.  The structure for
the exponential is similar.  The first method, described by Walther in
his paper on elementary functions (ca 1971) derives the exponential from
hyperbolic CORDIC functions.  The more efficient method uses a small
look-up (one entry per iteration) to compute the Log:

The incremental expression for an exponential, bx+dx = bx * bdx, can be
restated as bx+dx  =bx + bx * 2-i if bdx = 1 + 2-i.  For this to be
useful, the control element must be incremented by logb(1 + 2-i) for
each iteration that the decision function is true.  Since the value of
the log element is not used by the exponent element, the same results
are obtained if the control element is initialized with x and
decremented to zero.  The resulting cordic equations 
are:	 
		   Fi+1 = Fi + di*Fi*2-i 
	   and  Xi+1 = Xi - di*Logb(1 + 2-i).  
	 where  di = 1 if Xi+1 >= 0,  0 otherwise,
		   Logb(1 + 2-i) are read from a constants table,
		   X0 is the input value (x), and F0=1.
		   F will contain bx after the iterations.

Initializing F with some other value than 1 has the effect of scaling
the results by that value.  For natural base, a scale factor of 1/4 is
required to achieve valid outputs for any input 0 < x < 1. 

Of course, if you don't need much precision, a look-up table may be a
better choice.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka

The Andraka Consulting Group is a digital hardware design firm
specializing in high performance DSP designs in FPGAs. Expertise
includes reconfigurable computers, computer arithmetic, and maximum
performance/density FPGA design.
Article: 6164
Subject: palasm...
From: D Chiron <ZZA96DC@shef.ac.uk>
Date: Mon, 21 Apr 1997 16:11:29 +0100
Links: << >>  << T >>  << A >>
hello,

I am looking for some examples of *.PDS files used in PALASM
I need some files containing examples about STATE MACHINE (Moore)

If you have some files, could you e-mail me them? 

Thank you

David
Article: 6165
Subject: The FreeCore Library is here!
From: "Rune Bæverrud" <r@acte.no>
Date: Mon, 21 Apr 1997 17:52:00 +0200
Links: << >>  << T >>  << A >>
Hello all Altera CPLD designers,

The FreeCore Library is now up and running. This library contains free,
parameterizable functions for users of Altera programmable logic, plus a
few useful facts pages.

Please visit http://193.215.128.3/freecore/ for more information!

And please contribute to the library by submitting more functions!

Regards,
--
Rune Baeverrud <r@acte.no>
ACTE NC Norway AS
P.O. Box 190, N-2020 Skedsmokorset, Norway
Tel: +47 6389 8969   Fax: +47 6389 8979

Article: 6166
Subject: FCCM'97 Photo album
From: jmarnold@potomac.znet.com (Jeffrey M. Arnold)
Date: 21 Apr 1997 10:00:42 -0700
Links: << >>  << T >>  << A >>

So you missed FCCM'97?  Never fear!  Check out the official FCCM'97
Photo Album on the FCCM web page: http://www.fccm.org

More pictures will be added as time (and good taste!) permits.

-jeff
-- 
Jeffrey M. Arnold		jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace		Tel: 619-547-9257
San Diego, CA 92131		Fax: 619-547-9010
USA
Article: 6167
Subject: Postdoc: Brisbane Australia: FPGAs, Image Processing, GPS
From: n.bergman@qut.edu.au (Dr. Neil Bergman)
Date: Mon, 21 Apr 97 18:38:19 GMT
Links: << >>  << T >>  << A >>

Expressions of Interest Requested:  Postdoctoral Research Fellowships

GPS - Global Positioning System
Image Processing and Machine Vision
Reconfigurable Logic Circuits and Systems

Space Centre for Satellite Navigation
Queensland University of Technology, Brisbane, Australia

ABOUT THE CENTRE

The Space Centre for Satellite Navigation is a collaborative research centre 
within the Faculty of Built Environment and Engineering at the Queensland 
University of Technology in Brisbane, Australia. Research has expanded over 
recent years from an initial emphasis on satellite navigation to include 
groups working on image and vision processing, and computer architecture.

The Satellite Navigation Group is focused on applications for high precision 
GPS positioning. Current projects include developing an automated field 
tractor using kinematic GPS positioning as the sole means for navigation, and 
mine automation techniques.
The Image Processing and Machine Vision Group has pioneered techniques for 
analysis of satellite and aerial photographs for 3D terrain reconstruction, 
(as used in virtual reality pilot briefing for flight missions),  and 
measuring the exact geometry of the human eyeball for contact lens 
manufacturers. The focus of research is the analysis of stereo photography to 
yield high quality information about the 3D location of objects in the image, 
making use of the latest research in machine vision, artificial intelligence, 
image processing and photogrammetry.  New developments include the application 
of image processing techniques to textile manufacture.  

The Computer Architecture Group includes research into Reconfigurable Logic 
and Custom Computing, Asynchronous Logic, and VLSI Circuits and Systems.  The 
group has an applications emphasis on image and video processing systems to 
form a strong link to the work in the image processing and machine vision 
group.  Additionally, the group has interests in space-bourne computer and 
communications systems.

The Centre has excellent research infrastructure, and a strong record of 
collaborative research with industry and government. The Centre currently has 
four academic staff members, a professorial research fellow, four postdoctoral 
research fellows, about ten postgraduate students, and about ten research 
assistants, engineers and support staff. 

ABOUT THE POSITIONS

The Centre wishes to employ one or two postdoctoral research fellows who can 
take a senior role in strengthening and expanding one or more of the existing 
research areas of (i) satellite navigation (ii) image processing and machine 
vision, and (iii) reconfigurable logic circuits and systems.  The roles of the 
postdoctoral fellows will be:

(i) In collaboration with existing staff, to define and undertake 
industrially-relevant research of the highest international standards within 
the Centre's areas of interest.

(ii) To identify, initiate, coordinate and foster links with relevant 
industrial and government partners, so as to secure external industrial and 
government funding to undertake high quality, industrially relevant research 
to the benfit of the industrial partners and the centre.  Collaboration with 
other research centres of excellence is also encouraged.

(iii) To promulgate research results locally and internationally through 
research publications, conference presentations, patents and products.

(iv) To act as a mentor and supervisor to postgraduate students.

The Centre is currently seeking expressions of interest from potential 
candidates for these positions, pending the final approval of these positions 
by the University.  The positions will be for a period of up to three years.  
Annual salary is upwards from $A40,378 depending on qualifications and 
experience.  A PhD or equivalent research experience is expected.  Positions 
are to start as soon as possible.

An expression of interest, consisting of an extended CV outlining research and 
industrial experience should be sent to:

Dr Neil Bergmann, Deputy Director, SCSN,
School of Electrical and Electronic Systems Engineering,
Queensland University of Technology,
GPO Box 2434,
Brisbane Q 4001  AUSTRALIA
Phone: +61 -7- 3864-2785;  Fax: + 61 -7 -3864-1516
e-mail: n.bergmann@qut.edu.au

Potential candidates are encouraged to contact the Deputy Director to discuss 
the positions.

Suitable candidates will be forwarded final details of the positions as soon 
as they become available, so that a full application can be submitted.  It is 
expected that further positions will become available later in the year.  
While expressions of interest for this current round of applications should be 
received by 30 April, 1997, the Centre welcomes general expressions of 
interest in research positions at any time.
Article: 6168
Subject: PART 97 Conference: Special Session - Reconfigurable Computing
From: n.bergman@qut.edu.au (Dr. Neil Bergman)
Date: Mon, 21 Apr 97 18:51:02 GMT
Links: << >>  << T >>  << A >>

                       The 4th Annual Australasian Conference on
                           Parallel And Real-Time Systems
                                      (PART'97)

                                    29 - 30 September 1997 
                           The University of Newcastle, Newcastle, Australia 

		Website: http://www.cs.newcastle.edu.au/~part97/index.html

************NOTE SPECIAL SESSION ON RECONFIGURABLE COMPUTING *************
***************************SEE BELOW ************************************

The primary aim of the PART'97 conference is to bring together Australasian 
and International researchers, who are actively
involved in research on parallel and real-time systems, and to provide the 
opportunity for creative discussions. 

Authors are invited to submit manuscripts that demonstrate original 
unpublished research in all areas of parallel and real time
systems. Topics of interest include, but will not be limited to: 

  
   Parallel architectures and algorithms             Parallel programming
   Performance analysis and modelling                Mobile computing
   Network-based concurrent computing                Parallel databases
   Parallel I/O systems                              VLSI systems
   Heterogeneous computing                           Multimedia systems
   Distributed operating systems                     Message Passing Systems 
   Real-time languages and tools                     Fault-tolerant computing
   Real-time aspects of distributed systems          Real-time scheduling
   AI and neural networks in real-time control       Reconfigurable Computing

SPECIAL SESSIONS

A special session, of up to one full day in length, is being organised to 
examine all aspects of custom computers, i.e. computing
systems which incorporate FPGA-based reconfigurable computing subsystems. 
Papers are sought on custom computing
architectures, prototype systems, custom computing applications, 
hardware-software co-design, custom computing languages, and
any other aspects of custom computing. 

PAPERS PRESENTING A CRITICAL SUMMARY OF EXISTING, INDIVIDUAL PROJECTS
ARE WELCOME.

Plans for the special session include original unpublished results, a series 
of short presentations on work-in-progress, and a panel
discussion on the topic of "Developing a Strategy for Australia-wide 
Cooperative Research in Reconfigurable and Custom
Computing". 

Papers submissions for this special session, in the form of manuscripts of up 
to 10 pages in length, should be submitted to the
session organizer, Dr. Neil Bergmann. See Submission Details page for more 
details. Those wishing to present a 5-10 minute
description of work-in-progress should contact the session organizer, 
preferably by the submission deadline. 

Session Organizer
Dr. Neil Bergmann 
School of Electrical and Electronics Systems Engineering
Queensland University of Technology
GPO Box 2434 Brisbane 4001
Queensland, Australia
Ph.: +61 7 3864 2785 
FAX: +61 7 3864 1516 
n.bergmann@qut.edu.au 

IMPORTANT DATES

  
           Submission Deadline       8th May    1997
           Author Notification       30th June  1997
           Camera-ready copies       1st August 1997

LATER SUBMISSION MAY BE POSSIBLE - CONTACT SESSION ORGANISER
Article: 6169
Subject: Xilinx XC6216 availability?
From: Leon Heller <leon@lfheller.demon.co.uk>
Date: Mon, 21 Apr 1997 20:47:12 +0100
Links: << >>  << T >>  << A >>
Hello all,

Is there a problem with availability of the XC6216? My distributor only
has the XC6216-3PG299C in stock. I only want a couple to play with,
using the ETH Zurich software, so it doesn't matter too much. I was
hoping to use the (presumably) much cheaper 84-pin PLCC device, but they
appear to have been dropped.

Leon
-- 
Leon Heller
Amateur radio callsign: G1HSM
Email: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk
Tel: +44 (0) 118 947 1424 (home) +44 (0) 1344 385556 (work)
Article: 6170
Subject: FPGA gate counts - no truth in advertising?
From: kevintsmith@compuserve.com
Date: Mon, 21 Apr 1997 14:33:14 -0600
Links: << >>  << T >>  << A >>
Foreword:  I thought I posted this but didn't see it show up.  So if
this comes into your newsreader duplicated, don't adjust your set;
I may have sent it twice.
---
Dear comp.arch.fpga,

Forgive me for beating a dead horse, but since noone
responded to david@lowrance's challenge to explain gate counting
methodology I'll start a new thread to put in my $.02.

He was citing Xilinx and Actel for having unrealistic estimates,
and seemed to have a good understanding of where the marketing
department got their numbers and why he couldn't fully utilize the
claimed gate counts.

Since he invited FAEs to present their side of the story, I'll
launch into this electronic seminar guilt-free!

QuickLogic's pASIC1 family counts gates as the minimum usable
content of a logic cell.  A pASIC1 logic cell has a wide fan-in
PAL-like stage, followed by muxes into a D flip-flop.  The total
number of 2-input NAND gates in a logic cell is 31.  The usable
portion is estimated at 11, roughly a third.

We count gates from *every* logic cell because our abundant,
low-impedance routing allows to use *every* logic cell (honest!).
Therefore, our pASIC1 lineup looks like this:

pASIC1 device    # logic cells    2-input NANDs    usable gates
QL8x12B              96              2,976             1,056 (1k)
QL12x16B            192              5,952             2,112 (2k)
QL16x24B            384             11,904             4,224 (4k)
QL24x32B            768             23,808             8,448 (8k)

The pASIC2 family actually squeezes more logic into fewer logic
cells by pulling a stunt with fragmentability.  This means that
each logic cell can either be used as a unit for complex SOP or
decoding operations, or the software can pick off a small part of
the logic cell, leaving the rest for another portion of logic to
utilize.  Each cell has 5 independent outputs for this kind of usage.
Since our routing resources are plentiful and fast, we don't suffer
a speed penalty for doing this.  There are now about 40 NANDs per
logic cell, with an estimated 16 minimum usable.

As an added bonus, our pASIC2 logic cell's fragmentability makes
the parts more suitable to Synthesis with tools like Synopsys,
Synplicity, Exemplar, and DesignWare.  We get results that keep
engineers from having to use any hand-designed macros.  But when
they need to, the process is straightforward, utilizing optimized
macros in schematic that can be netlisted to HDL to get speeds like
180MHz+ for a 24-bit loadable counter.

pASIC2 device # logic cells  2-input NANDs  usable gates
QL2003           192            7,680         3,072 (3k)
QL2005           320           12,800         5,120 (5k)
QL2007           480           19,200         7,680 (7k)
QL2009           672           26,880        10,752 (10k) misnamed?

As we go higher densities, we have no architectural limit to the
amount of routing resources we can add because our routing is all
between metal layers.  Therefore, as gate counts go up speed, routability,
and ease of use remain constant as QuickLogic's claims to fame.

Our new fab agreement with TSMC at .35u will enable parts with 20k
usable gates and more.
---
Keb'm
*********************************************************
I am an employee of QuickLogic but anything I post here should be
construed to be my own opinion, not my employer’s.
*********************************************************

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6171
Subject: Re: palasm...
From: Gareth Baron <gareth@trsys.demon.co.uk>
Date: Tue, 22 Apr 1997 16:42:44 +0100
Links: << >>  << T >>  << A >>
In article <335B83A1.776A@shef.ac.uk>, D Chiron <ZZA96DC@shef.ac.uk>
writes
>hello,
>
>I am looking for some examples of *.PDS files used in PALASM
>I need some files containing examples about STATE MACHINE (Moore)
>
>If you have some files, could you e-mail me them? 
>
>Thank you
>
>David

If you get hold of the PALASM 4.0 s/w off AMD's website you will get a
load of example files that contain all types of state machine and logic
models.  I would advise you to start off there.

Regards,

Gareth Baron

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%                                               %
%       Morphesys Ltd.  Tel: +44 (0)802 754 512 %
%                                               %
%       EMail:    Gareth@trsys.demon.co.uk      %
%                                               %
%       http://www.trsys.demon.co/              %
%                                               %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

Article: 6172
Subject: CFP ASIC 97 (April 24th Deadline)
From: rauletta@erebor.cudenver.edu (Richard J. Auletta)
Date: 22 Apr 1997 18:36:45 GMT
Links: << >>  << T >>  << A >>
-------------------------------------------------------------------------------

                         **LAST CALL FOR PAPERS**
           10th Annual IEEE International ASIC Conference & Exhibit
                           PORTABLE SYSTEM SOLUTIONS
                               Portland, Oregon
                             September 7-10, 1997

             *** Latest information at http://asic.union.edu ***
 ******************************************************************************
                       Extended Deadline - April 24
                     Papers must be RECEIVED by April 24 

                             Submit paper to:
                            Ms. Lynne Engelbrecht
                         ASIC Conference Coordinator
                              1806 Lyell Avenue
                          Rochester, NY 14606, USA.
                          Telephone: (716) 254-2350
                             FAX: (716) 254-2237

 ******************************************************************************
 
                                CALL FOR PAPERS
 
           10th Annual IEEE International ASIC Conference & Exhibit
                           PORTABLE SYSTEM SOLUTIONS
                               Portland, Oregon
                             September 7-10, 1997
 
                Sponsored by the Rochester section of the IEEE
                              in cooperation with
                   IEEE Solid State Circuits Council & OCATE
 
             *** Latest information at http://asic.union.edu ***
 The ASIC'97 Conference provides a forum to disseminate recent advances about
 the application of VLSI design and technologies to the design requirements
 of electronic systems.
 
 A SPECIAL EDITION OF THE IEEE TRANSACTIONS ON VLSI SYSTEMS WILL BE PUBLISHED
 WITH SELECT PAPERS FROM THE CONFERENCE. The conference also presents a "BEST
 PAPER AWARD". The 1997 conference theme is "Portable System Solutions".
 Papers addressing this area are encouraged.
 
                               AREAS OF INTEREST
 
  ASIC Applications:        Multimedia, Image Processing, Imaging, Storage
                            Techniques & Graphics
 
  Devices & Technologies:   BiCMOS Mixed Technologies, Low Power Devices,
                            SOI, Memory Technologies & New Structures
                            Field Programmable Gate Arrays, PLDs, Gate
  Architectures:            Arrays, Memory Architectures, Full Custom ICs,
                            Specialty Cores & Hardware/Software co-Design
                            Mixed Signal Circuits, High Performance and Low
  Mixed-Signal/Analog:      Power Analog Techniques, Power Modules, D/A and
                            A/D Converters, testing, RF Circuits & Filters
  Communications:           Wireless, Modems, ATM, SONET & CAP
  Test:                     Boundary Scan, BIST, IDDQ & Stuck-At-Faults
  DSP:                      Filters, Compression, MPEG, HDTV & Equalizers
 
  CAD:                      Design Capture, Synthesis, Optimization, HDLs,
                            Automatic Routing, Layout & Verification
 
  Simulation & Modeling:    Device, Circuits, Interconnects & System
                            simulation
  High Performance          I/O, Multi-Chip Modules, GaAS, CMOS, BiCMOS &
  Circuits:                 Optical Interfaces
  Low Power Design:         Low Voltage and Low Power Designs.
 
 Submissions for tutorial workshops are also encouraged. Hands-on workshops
 aimed at design engineers are encouraged. Please contact the workshop chair
 for details.
 
                             SUBMISSION OF PAPERS
 
 Please submit a preliminary copy of the paper reporting your original and
 previously unpublished work. The paper must clearly state the advances
 proposed; sufficient results (measured or simulated) and diagrams must be
 presented to demonstrate the quality and originality of the contributed
 work. The paper (limit to four pages double column format) must include a
 three to four sentence abstract along with the composite paper (text,
 figures, tables, references, etc.). THE INITIAL PAPER SUBMISSION SHOULD
 CLOSELY APPROXIMATE THE FINAL ACCEPTED PAPER SUBMISSION.
 
 Each submitted paper must include a cover page with the following
 information on the presenting and correspondence (if different) author:
 name, affiliation, address, email address, phone and fax number. Please
 indicate the category of your submission using preferred topic areas (give
 first and second choices from the above topics). In addition, for each paper
 submitted, please email the title, author names, affiliation, address
 (including email, phone and FAX numbers) of the corresponding author and
 abstract to asic97@ieee.rochester.ny.us or, if unable to use e-mail, fax
 this information to the conference co-ordinator.
 
                    Please send 10 copies of the paper to
 
                             Ms. Lynne Engelbrecht
                          ASIC Conference Coordinator
                               1806 Lyell Avenue
                           Rochester, NY 14606, USA.
                           Telephone: (716) 254-2350
                              FAX: (716) 254-2237
                     e-mail: asic97@ieee.rochester.ny.us
 
 
  Steering Committee Chair:    James Meindl
                               Georgia Institute of Technology
                               Phone: (404) 853-9416
                               e-mail:james.meindl@ee.gatech.edu
 
  Conference Chair:            P.R. Mukund
                               Rochester Institute of Technology
                               Phone: (716) 475-2174
                               e-mail: mukund@cs.rit.edu
 
  Technical Co-chairs:         Ramalingam Sridhar
                               The State University of New York at Buffalo
                               Phone: (716) 645-2422x2139
                               e-mail: rsridhar@eng.buffalo.edu
 
                               Thaddeus Gabara
                               Lucent Technologies
                               Phone: (908) 582-2554
                               e-mail: gabara@bell-labs.com
 
  Workshop Chair:              Robert Daasch
                               Portland State University
                               Phone: (503) 725-5409
                               e-mail: daasch@ee.pdx.edu
 
  Exhibits Chair:              Steven Ciccarelli
                               ANRO Engineering, Inc.
                               Phone: (716) 334-0278
                               e-mail: ciccares@vivanet.com

=============================================================================== 
Article: 6173
Subject: Re: The FreeCore Library is here!
From: "Paul Baxter" <paje@globalnet.co.uk>
Date: 22 Apr 1997 18:48:04 GMT
Links: << >>  << T >>  << A >>

I have just visited the freecore site and wish to thank Rune for all the
hard work that must have gone into this site.

Thank you very much for a professionally presented site which I'm sure will
develop into an excellent resource for Altera EPLD designers.

I hope that people are encouraged to enter into the spirit of it

Good luck.

Paul Baxter, Paje Consultants Ltd.



Rune Bæverrud <r@acte.no> wrote in article <335B8D20.AD1C85AB@acte.no>...
> Hello all Altera CPLD designers,
> 
> The FreeCore Library is now up and running. This library contains free,
> parameterizable functions for users of Altera programmable logic, plus a
> few useful facts pages.
> 
> Please visit http://193.215.128.3/freecore/ for more information!
> 
> And please contribute to the library by submitting more functions!
> 
> Regards,
> --
> Rune Baeverrud <r@acte.no>
> ACTE NC Norway AS
> P.O. Box 190, N-2020 Skedsmokorset, Norway
> Tel: +47 6389 8969   Fax: +47 6389 8979
> 
> 
Article: 6174
Subject: Memory workshop, San Jose, August 11-12
From: fmeyer@cs.tamu.edu (Jackie Meyer)
Date: 22 Apr 1997 21:31:37 GMT
Links: << >>  << T >>  << A >>
Advanced registration deadline:  July 31, 1997

************************************************************************

              1997 IEEE INTERNATIONAL WORKSHOP ON MEMORY
 		TECHNOLOGY, DESIGN AND TESTING (MTDT)

************************************************************************

                  Program and Registration Details at

    <ftp://ftp.cs.tamu.edu/pub/fmeyer/service/mtdt97/abstracts.html>

************************************************************************

                    August 11-12, 1997
                    Hilton Hotel And Towers
                    300 Almaden Blvd,
                    San Jose, California, USA
                    Tel: (408)-287--2100

************************************************************************


                    INTRODUCTION  TO  MTDT 97

You are invited to participate in the 1997 IEEE International Workshop
on Memory Technology, Design and Testing.  This electronic document
includes up-to-date information about the Workshop (Technical Program,
Travel Information, etc).  Also, please find attached the WORKSHOP
REGISTRATION FORM and HOTEL INFORMATION.  After filling out the
registration form please mail or fax it to guarantee your
participation.
 
MTDT 97 is the latest meeting in a series that explores all aspects of
memory design, process technologies and testability related topics,
such as memory circuit designs, cell structures, fabrication
processes, design architectures.

The two-day technical program includes 16 paper presentations, one
panel session and a keynote address.  The paper sessions span many of
the key areas in design, test, and technology.

Also on the program are sessions on emerging areas that are gaining
prominence, such as low power, tools and sensing.  We hope that you
will find MTDT 97 interesting, thought-provoking, and rewarding.

     Fabrizio Lombardi
     General Chair
     E:  lombardi@cs.tamu.edu

     Thomas Wik
     Technical Program Chair
     E:  trw@lsil.com

Sponsored by:
  IEEE Computer Society
  Technical Committee on Test Technology
  Technical Committee on VLSI
In cooperation with:
  IEEE Solid-State Circuit Society

------------------------------------------------------------------------

	                1997 WORKSHOP ON MTDT

                         GENERAL INFORMATION

------------------------------------------------------------------------

All activities require a registration badge for admittance.  All
participants must pay the appropriate fees.  Reduced fees are available
to IEEE or Computer Society members on presentation of a valid member
number.

To register, use the Symposium Registration Form attached to this
file.  To receive early registration discount rates, your completed
Registration Form must be RECEIVED by mail or fax by July 31, 1997.
After July 31, register at the higher rates listed in the table below.

Technical program registration includes a copy of the Proceedings,
(published by IEEE CS Press), the banquet, luncheons and coffee
breaks.  Lunch and banquet tickets for companions of registered
attendees will be available at the registration desk.  Extra copies of
the Proceedings will be also available at $30 each.
        
     REGISTRATION FEES:

             Early Registration*     WORKSHOP
             IEEE/CS Member            $270
             Non-members               $345

             Registration at Hotel   WORKSHOP
             IEEE/CS Member            $325
             Non-members               $400

* discounts available until July 31, 1997

REFUNDS:  If you must cancel, advance registration fees will be
refunded only upon written request to the Finance Chair postmarked on
or before July 15, 1997.  A $100 processing fee is charged for each
refund.


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