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Messages from 6950

Article: 6950
Subject: Re: Best FPGA language for portability
From: Rune Baeverrud <r@acte.no>
Date: Mon, 14 Jul 1997 21:56:31 +0200
Links: << >>  << T >>  << A >>
Wade D. Peterson wrote:
> 
> I've got a couple of circuits that I think are salable
> to FPGA users.  I'd like to package them as 'core'
> logic and sell them.  However, I'm trying to decide on the
> best approach to FPGA tools.

You may find it difficult to sell your cores, unless you have a huge
marketing engine standing behind you. I would recommend that you try to
ally yourself with the vendor of the devices you have targeted. This is
in line with where the market is going today, all the big FPGA/CPLD
vendors provide IP cores as it becomes more and more important for them
to sell solutions rather than 'sillycon' alone.

Why not give away your cores, and instead base your income on design
services? Giving away your cores is an excellent opportunity for you to
market your name in the PLD community and gain respect for both you and
your work.

Rune Baeverrud
The FreeCore Library
http://193.215.128.3/freecore
Article: 6951
Subject: Re: Generating Sine/Cosine digitally
From: Ray Andraka <randraka@ids.net>
Date: Mon, 14 Jul 1997 20:55:05 -0400
Links: << >>  << T >>  << A >>
-Bodnar,B.L. wrote:
> 
> In article <33C3916F.7CEE@ix.netcom.com>,
> Stephen R. Synakowski <srs1@ix.netcom.com> wrote:
> >> Probably the most stable method (avoids accumulated offsets from
> >> rounding errors) is to accumulate phase in an device that that adds a
> >> user selected delta phase to a total at fixed intervals(clock) and
> >> applies the count to a sine/cos lookup prom. You can achieve arbitrary
> >> precision this way. I haven't seen the initial post, so I am not sure of
> >> desired frequencies.

...
> These articles are all very interesting.  However, I've yet to see the
> simplest approach mentioned:  using a lookup table with the sine/cosine values
> stored... 


That is exactly what the first post you copied in your post says.  The
phase accumulator is used to address the look up at an arbitrary
frequency determined by the delta phase value.  This means the frequency
can be changed without changing the look up table contents, assuming the
wave shape is not changed. That accumulator can be as many bits as
desired to obtain the desired frequency resolution.  The LUT is then
addressed by the n most significant bits of the accumulator to obtain an
output with n bit phase resolution. If the waveshape is symmetric, you
can play some logic tricks to reduce the size of the lookup (reverse the
count order and/or invert the look-up output).  Of course, the Lookup
table entries correspond to equally spaced phase angles such that the
full scale value on the phase accumulator corresponds to 2*pi radians.

Anyway, the look-up coupled with a phase accumulator is a sensible (and
the best) solution provided the required phase resolution is small
enough to have a reasonable table size (5 or 6 bit phase address to the
table for most FPGAs...assuming we're talking an FPGA implementation). 
The lookup also has the (potentially big) advantage of being capable of
generating an arbitrarily shaped waveform.  

  Of course, if you need quadrature sinusoidal outputs, then two
look-ups per sample point are required, and if the output is to be
scaled by some variable, then a multiplier for each phase is also
required.  In that context (as in a quadrature modulator), a pipelined
CORDIC approach can be considerably faster and smaller than a LUT based
solution since it simultaneously provides quadrature outputs and
inherently multiplies the outputs by the input magnitude.  For low data
rates, the hardware can be reduced by handling each phase on alternate
clocks using a LUT and multiplier approach.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka

***note the new website address***
Article: 6952
Subject: Re: Altera FLEX10K initialization
From: CoxJA@augustsl.demon.co.uk (Julian Cox)
Date: Tue, 15 Jul 1997 07:22:45 GMT
Links: << >>  << T >>  << A >>
Steve@s-dewey.removetostopspam.demon.co.uk (Steve Dewey) wrote:

>Pete
>
>This appears to be the kind of question that should be directed to Altera's
>tech. help desk. Send mail to sos@altera.com 
>
>I have always found them very helpful & prompt.
>
>However, if you have tried them, and not received a satisfactory response,
>then I think that a lot of people on this group would like to know,
>especially given the perpetual flame-war that appears to be waged between
>Altera & Xylinx ;-)
>
>Regards
>
>Steve
>
>P.S. Anyone in the UK got Maxplus 8 yet ?
>
Yep.

>
<snip>
>

-- 
---------------------------------------------------------------------
Julian Cox
CoxJA@augustsl.demon.co.uk              error: smartass.sig not found
Hardware development eng.                          August Systems Ltd
---------------------------------------------------------------------
                                          

Article: 6953
Subject: UTOPIA?
From: Utku Ozcan <ozcan@rnd.netas.com.tr>
Date: Tue, 15 Jul 1997 12:10:36 +0400
Links: << >>  << T >>  << A >>
Can I find UTOPIA theory and implementations for ASICs?

 topics:
 UTOPIA 2
 8 and 16 bits
 25, 33, 50, 66 MHz or more
 MULTI-ATM MULTI-PHY and even MULTI AAL, if available.
 VHDL and/or Verilog

 Thanks in advance.

-- 
Utku Ozcan, http://www.ehb.itu.edu.tr/~utku/
Article: 6954
Subject: Job; Senior Engineer; Altera; FPGA; High Speed Digital
From: richard_steinman@cmagroup.com
Date: 15 Jul 1997 16:36:53 GMT
Links: << >>  << T >>  << A >>

US, NY, Syracuse; Senior Engineer; FPGA; High Speed Digital. 

Must have: signal processing, algorithms, high speed digital design (40-
50 MegaHertz), FPGAs, and exposure to imaging &/or sensor systems applications. 
Client using Altera, ViewLogic and Spice CAE/CAD tools. 60-70% design/
detailed design; 30-40% systems level work. TO $48-75K

Please refer to JO# 582RJS in your response.



Richard Steinman
Team Leader
rjs@cmagroup.com
IT & Software Solutions Team
Career Marketing Associates
http://www.cmagroup.com/IT.html
Article: 6955
Subject: Bus termination - cool parts & app. notes
From: "Tom Burgess" <tburgess@drao.nrc.ca>
Date: 15 Jul 1997 19:04:04 GMT
Links: << >>  << T >>  << A >>
My cool site of the day is http://www.calmicro.com/prod/prod.htm. If you
are doing >50MHz bus FPGA designs you will
will find their Schottky and AC termination parts of interest, and their
application notes are very good. 

	regards, tom (tburgess@drao.nrc.ca)
Article: 6956
Subject: Selection Criteria for CPLD's/FPGA's
From: "Peter Welten" <welten@miles.nl>
Date: 15 Jul 1997 22:20:59 GMT
Links: << >>  << T >>  << A >>
Hello,

I'm asked to give a presentation that elaborates on the selection of the
right type of FPGA or CPLD for a certain job. Since I haven't given such a
presentation for some time now, I am now seeking for information to
updating my knowledge on the subject.

Does anyone know of an article or presentation or whatever documentation
that deals with this subject and that is free to use?
There are many Selection Criteria. They can be economical or technical.
They can be about associated tools, knowledge or investments already made
or to be made. Etc. etc.

I'm most interested in technical criteria like speed, size, voltage, power
dissipation, etc. But also the others like flexibility, programmability,
testability, programming speed, yes/no isp, etc.

Overview of recent new technologies are also welcome.
Recent benchmark results are welcome.

Who will point me in the(or some) right direction(s)??

Thanks in advance, Peter Welten
Article: 6957
Subject: GET FREE 2100 $ex-Web $Sites FREE! @?
From: 18734757@compuserve.com
Date: 16 Jul 1997 07:46:43 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

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--_-=391


Article: 6958
Subject: Re: Selection Criteria for CPLD's/FPGA's
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 16 Jul 1997 07:58:57 GMT
Links: << >>  << T >>  << A >>

There was an excellent article on the subject in a recent EDN magazine:

Shattering the Programmable-Logic  Speed Barrier, by Brian Dipert
EDN, May 22, page 36 thru 60.

Good luck on picking a winner.

But here's my thoughts on the subject of picking a winner.

Unless your design has some very specific requirements that only one
vendor's products support, all the vendors have products that can be
made to work within your design requirements.

If you need a PLD with 100 macro cells, to implement some big state
machine, then there are at least 4 or 5 vendors that PLDs that will
do the job.

If you need 10K gates (what ever a 'gate' is) of arithmetic datapath, then
there are 4 or 5 vendors that have products that will do the job. Most are
the same vendors as the PLD vendors. 

The deciding issue is more likely to be the tools.
Here is a short (and incomplete) checklist:

Tools issues/characteristics (in no particular order): 

1)  Price
2)  Existing expierence within your organization
3)  Learning curve
4)  Integration into other software you might have (PCB layout, Simulation
    test vector generation, system visualization, .... )
5)  Technology independence
6)  Support
7)  Host Operating System
8)  Available host machines
9)  Training
10) Availability to find a consultant to dig you out of any mess the
    vendor puts you into.
11) Import/export for design migration to other Silicon
12) add your own items here.


Good luck

Philip Freidin



In article <01bc916e$c5e3c500$e63e4fc1@default> "Peter Welten" <welten@miles.nl> writes:
>Hello,
>
>I'm asked to give a presentation that elaborates on the selection of the
>right type of FPGA or CPLD for a certain job. Since I haven't given such a
>presentation for some time now, I am now seeking for information to
>updating my knowledge on the subject.
>
>Does anyone know of an article or presentation or whatever documentation
>that deals with this subject and that is free to use?
>There are many Selection Criteria. They can be economical or technical.
>They can be about associated tools, knowledge or investments already made
>or to be made. Etc. etc.
>
>I'm most interested in technical criteria like speed, size, voltage, power
>dissipation, etc. But also the others like flexibility, programmability,
>testability, programming speed, yes/no isp, etc.
>
>Overview of recent new technologies are also welcome.
>Recent benchmark results are welcome.
>
>Who will point me in the(or some) right direction(s)??
>
>Thanks in advance, Peter Welten


Article: 6959
Subject: Re: Selection Criteria for CPLD's/FPGA's
From: edndipert@postoffice.worldnet.att.net (Brian Dipert)
Date: Wed, 16 Jul 1997 14:09:45 GMT
Links: << >>  << T >>  << A >>
Thanks for the flattering comments, Philip!

>
>There was an excellent article on the subject in a recent EDN magazine:
>
>Shattering the Programmable-Logic  Speed Barrier, by Brian Dipert
>EDN, May 22, page 36 thru 60.
>

Brian Dipert
Technical Editor
EDN Magazine: The Design Magazine Of The Electronics Industry
1864 52nd Street
Sacramento, CA   95819
(916) 454-5242
(916) 454-5101 (fax)
edndipert@worldnet.att.net
Visit me at <http://members.aol.com/bdipert>
Article: 6960
Subject: Re: UTOPIA?
From: "David Chhoeun" <chhoeun@aware.com>
Date: 16 Jul 1997 16:41:23 GMT
Links: << >>  << T >>  << A >>

There are UTOPIA Level I and Level II specs and as well as ITU I.xxx series
specs.  The UTOPIA specs you can get them from the ATM forum at:
www.atmforum.com and the ITU I.xxx series you can get them from the ITU
organization.

David Chhoeun
AWARE, Inc.
www.aware.com


Utku Ozcan <ozcan@rnd.netas.com.tr> wrote in article
<33CB307C.41C67EA6@rnd.netas.com.tr>...
> Can I find UTOPIA theory and implementations for ASICs?
> 
>  topics:
>  UTOPIA 2
>  8 and 16 bits
>  25, 33, 50, 66 MHz or more
>  MULTI-ATM MULTI-PHY and even MULTI AAL, if available.
>  VHDL and/or Verilog
> 
>  Thanks in advance.
> 
> -- 
> Utku Ozcan, http://www.ehb.itu.edu.tr/~utku/
> 
Article: 6961
Subject: Re: Selection Criteria for CPLD's/FPGA's
From: "L. Kumpa" <LKumpa@nonet.net>
Date: 16 Jul 1997 16:56:13 GMT
Links: << >>  << T >>  << A >>

Can you post or let people know where to read this EDN
article - on-line? --- Thanks.



Brian Dipert <edndipert@postoffice.worldnet.att.net> wrote in article
<33ccd5fc.1528452@netnews.worldnet.att.net>...
> Thanks for the flattering comments, Philip!
> 
> >
> >There was an excellent article on the subject in a recent EDN magazine:
> >
> >Shattering the Programmable-Logic  Speed Barrier, by Brian Dipert
> >EDN, May 22, page 36 thru 60.
> >
> 
> Brian Dipert
> Technical Editor
> EDN Magazine: The Design Magazine Of The Electronics Industry
> 1864 52nd Street
> Sacramento, CA   95819
> (916) 454-5242
> (916) 454-5101 (fax)
> edndipert@worldnet.att.net
> Visit me at <http://members.aol.com/bdipert>
> 
Article: 6962
Subject: Re: Xilinx Prom Generation Problem
From: z80@dserve.com (Peter)
Date: Wed, 16 Jul 1997 18:04:39 GMT
Links: << >>  << T >>  << A >>

Thank you for the explanation.

I wonder why someone has not written a little DOS utility utility for
doing this. The job is not complex; it is only slightly worse than the
standard EPROM programmer utility which loads multiple intel hex files
into a binary image.



Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 6963
Subject: FREE...Don't Pay For $ex $site Pa$$words,
From: 98776555554453@compuserve.com
Date: 16 Jul 1997 18:10:06 GMT
Links: << >>  << T >>  << A >>
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--_-=878


Article: 6964
Subject: Problem simulating 3-state output with M1 and Synopsys
From: Arrigo Benedetti <arrigo@vision.caltech.edu>
Date: 16 Jul 1997 18:34:14 -0700
Links: << >>  << T >>  << A >>
Dear fellows,

I'm doing a functional simulation of a 4028EX design that has several
three-state output lines with vss and the new M1 simprim library.
The vhdl entity that I'm simulating has been generated by ngd2vhdl
after design translation. This is the only kind of functional
simulation that I can do with this design, as it contains several
RPM macros from .xnf files.
My impression is that the three-state output buffer is not simulated
well, as the output lines are always defined as X"????" in vss.
I also checked that the GTS net was low giving the "assign '0' gts"
command before running the simulation but this didn't help.

Has anyone had this problem before ?

thanks in advance

-Arrigo
-- 
Arrigo Benedetti		    e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93				phone: (818) 395-3695
Pasadena, CA 91125				fax:   (818) 795-8649
Article: 6965
Subject: FREE SEX SITE..password is.
From: gary099g@erols.com
Date: 17 Jul 1997 05:25:51 GMT
Links: << >>  << T >>  << A >>
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--_-=599


Article: 6966
Subject: Get FREE PASSWORD TO 2000 SEX SITEs
From: 188d77@compuserve.com
Date: 17 Jul 1997 05:28:58 GMT
Links: << >>  << T >>  << A >>

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Article: 6967
Subject: CALL FOR PAPERS (CSD'98)
From: Alexander Taubin <taubin@u-aizu.ac.jp>
Date: 17 Jul 1997 01:20:37 -0700
Links: << >>  << T >>  << A >>

International Conference 
 on Application of Concurrency  to System Design  (CSD'98)

CALL FOR PAPERS

March 23-26, 1998, Aizu-Wakamatsu, Japan

Sponsored by:

The IEEE Computer Society - VLSI-TC, 
The IEICE TG on Concurrent System Technology, 
The SICE TG on Discrete Event Systems, 
The IMACS scientific association

In Cooperation With:

IFIP WG 10.3, 10.5, The University of Aizu
The UN University/IIST, Formal Methods Europe

GENERAL CHAIR:

Shoichi Noguchi - noguchi@u-aizu.ac.jp
The University of Aizu, Japan

PROGRAM CHAIRS:

Wolfgang Reisig (theory)
Humboldt Universität zu Berlin, Germany
reisig@informatik.hu-berlin.de
tel.+49-30-20181219, fax:+49-30-20181221

Luciano Lavagno (application)
Politecnico di Torino, Italy
Cadence Berkeley Labs, USA
lavagno@polito.it, luciano@cadence.com
tel.+39-11-5644150, fax:+39-11-5644099

CONFERENCE CO-CHAIRS:

Sadatoshi Kumagai - Osaka Univ., Japan
kumagai@pwr.eng.osaka-u.ac.jp
tel.+81-06-879-7693, fax:+81-06-875-2672

Alex Kondratyev - kondraty@u-aizu.ac.jp
The University of Aizu, Japan
tel.+81-242-372557, fax:+81-242-372744

PUBLICATION CHAIR:

Masaru Naniwada - NEC Corp., Japan,
naniwada@pepo.tmg.nec.co.jp

PUBLICITY CHAIR:

Tomohiro Yoneda - yoneda@cs.titech.ac.jp,
Tokyo Institute of Technology, Japan

FINANCE CHAIR:

Kazuaki Yamauchi - yamauchi@u-aizu.ac.jp
The University of Aizu, Japan

LOCAL ARRANGEMENT CHAIR:

Yuko Kesen - kesen@u-aizu.ac.jp
The University of Aizu, Japan

TUTORIAL/CAD BOOTH CHAIR:

Alexander Taubin - taubin@u-aizu.ac.jp
The University of Aizu,Japan

INDUSTRY RELATIONS:

Shinichi Honiden - Toshiba Corp., Japan,
honiden@ssel.toshiba.co.jp
Yoshihiro Ueda - OkI Electric,
Japan ueda@wbg.telcom.oki.co.jp
Naoshi Uchihira - Toshiba Corp., Japan,
uchi@ssel.toshiba.co.jp

The International Conference on Application of Concurrency to System Design
is being organized as a forum for disseminating advanced research results on
theory and practice of design of concurrent systems. While there are a few
``success stories'' in this field, there is a real need to provide
practitioners with adequately sound and expressive tools, and researchers
with real motivations and examples. The aim of this conference is to
contribute towards this goal by bringing together experts in a wide variety
of fields related to complex concurrent system design and analysis.

TOPICS OF INTEREST:

Formal and semi-formal models: Petri nets, Temporal Logics, Data Flow nets,
Statecharts, Synchronous Languages, HDLs, etc.

Formal methods for CAD and verification of concurrent systems: model
checking, asynchronous design, high-level synthesis, hardware/software
co-design, etc.

Real-time and hybrid systems

Case studies of concurrent systems design and verification

Presentation of software tools supporting the above topics

PAPERS: Submitted papers should be no more than 15 pages in 11-point font
with a 60-word abstract, and should include a cover page with authors'
physical and e-mail addresses, phone and FAX numbers. Prospective authors
should submit six single-sided copies of the manuscript with a cover-page by
October 10, 1997 to:

(1) Theoretical papers: Wolfgang Reisig (CSD98), Humboldt-Universität zu
Berlin, Institut für Informatik, Unter der Linden 6, 10099, Berlin, Germany

(2) Application papers: Luciano Lavagno (CSD98), Cadence Berkeley
Labs, 1919 Addison St. #303-304, Berkeley - CA 94704-1144, USA

Accepted papers are intended to appear in series by the IEEE Computer
Society Press. A limited number of travel grants will be available for
conference contributors.

INFORMATION: The University of Aizu: csd@u-aizu.ac.jp, 
Phone : (+81) 242 37 2557, Fax : (+81) 242 37 2744

On the World Wide Web at URL: http://www.u-aizu.ac.jp/csd98/

IMPORTANT DATES:

Papers due: October 10, 1997

Notification of acceptance by: December 1, 1997

Final Version by: January 5, 1998

PROGRAM COMMITTEE: Gerard Berry (France) Manfred Broy (Germany) 
Roy Campbell (USA) Edmund Clarke (USA) Jordi Cortadella (Spain) 
Jorg Desel (Germany) Javier Esparza (Germany) Jean-Luc Gaudiot (USA) 
Kunihiko Hiraishi (Japan)
Rene Jacquart (France) Tomasz Janowski (Macau) Timothy Kam (USA) Shmuel Katz
(Israel) Michael Kishinevsky (Japan) Bob Kurshan (USA) Edward Lee (USA)
Dong-Ik Lee (Korea) Shin-ichi Minato (Japan) Takashi Nanya (Japan) Mogens
Nielsen (Denmark) Kenji Onaga (Japan) Carl Pixley (USA) Patrick Scaglia
(USA) Fabio Somenzi (USA) Pasupathy Subrahmanyam (USA) 
Achim Sydow (Germany) P.S. Thiagarajan (India) Antti Valmari (Finland)
Jim Woodcock (UK) Zhou Chaochen (Macau)

-- 
Kind regards
Alexander Taubin
THE UNIVERSITY OF AIZU  phone   +81-242-37-2572 (office)        
Tsuruga, Ikki-machi, Aizu-Wakamatsu City fax     +81-242-37-2744         
Fukushima, 965-80 Japan    e-mail  taubin@u-aizu.ac.jp     
---- <A HREF="http://www.u-aizu.ac.jp/~taubin/">------------------------
Article: 6968
Subject: free FPGA software from actel
From: Herbert Kleebauer <klee@mistress.informatik.unibw-muenchen.de>
Date: Thu, 17 Jul 1997 02:35:55 -0600
Links: << >>  << T >>  << A >>
Has somebody tested the free actel software? Is it worth to download?
Is programmer support included? Is the ACTIVATOR needed or is there
a free design for a simple programming hardware.

If Vielogic would release the old DOS Workview as freeware this maybe
could be a good system for homberew chips.

-------------------------------------------------------------------------

Designer Lite 3.1.1

If you are a PC user (Win 95 or WinNT 4.0), you can now download Actel
software directly from the web: no sales call, no authorization code,
and
it’s free! There is no better way to find out how easy Actel software is
to
use.

With this software, you get all the following programs and libraries:

   * Designer Series up to 8000 gates
   * ACTgen Macro Builder
   * DirectTime - Timing-Driven Layout & Analyzer
   * VITAL Libraries
   * Verilog Libraries
   * Viewlogic Libraries

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 6969
Subject: free FPGA software from actel
From: Herbert Kleebauer <klee@mistress.informatik.unibw-muenchen.de>
Date: 17 Jul 1997 10:40:44 +0200
Links: << >>  << T >>  << A >>
Has somebody tested the free actel software? Is it worth to download?
Is programmer support included? Is the ACTIVATOR needed or is there
a free design for a simple programming hardware.

If Vielogic would release the old DOS Workview as freeware this maybe
could be a good system for homberew chips.

-------------------------------------------------------------------------

Designer Lite 3.1.1

If you are a PC user (Win 95 or WinNT 4.0), you can now download Actel
software directly from the web: no sales call, no authorization code,
and
it’s free! There is no better way to find out how easy Actel software is
to
use.

With this software, you get all the following programs and libraries:

   * Designer Series up to 8000 gates
   * ACTgen Macro Builder
   * DirectTime - Timing-Driven Layout & Analyzer
   * VITAL Libraries
   * Verilog Libraries
   * Viewlogic Libraries

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet

Article: 6970
Subject: Problem with unexpanded logic in xnf synhesized by Leonardo
From: Mark Sandstrom <Mark.Sandstrom@martis.fi>
Date: Thu, 17 Jul 1997 15:08:13 +0300
Links: << >>  << T >>  << A >>
Hi,

I get an error of unexpanded logical blocks when trying to 
map a xnf synthesized by Leonardo to an xc4000 fpga.

How can get over that?

Any advice is appreciated!

Best regards,

	Mark H. Sandstrom


Belowe are excerpts of the Leonardo and M1 runs:
 
Leonardo - V4.0.3
...
LEONARDO{1}: load_library xi4ex
Reading library file `/tools/exemplar/leonardo_403/lib/xi4ex.syn`...
Library version = 0.3
Delays assume: Process=3 
LEONARDO{2}: read -work work -format VHDL
/asic2/gma/leonardo/gma/gma.vhd
-- Reading file /tools/exemplar/leonardo_403/data/standard.vhd
-- Loading package standard into library std
-- Reading vhdl file /asic2/gma/leonardo/gma/gma.vhd into library work
-- Reading file /tools/exemplar/leonardo_403/data/std_1164.vhd
-- Loading package std_logic_1164 into library ieee
-- Searching for SYNOPSYS package std_logic_arith..
-- Reading file /tools/exemplar/leonardo_403/data/syn_arit.vhd
-- Loading package std_logic_arith into library ieee
-- Loading package gma_tdp into library work
-- Loading package gma_mca into library work
-- Loading entity ram_memgen into library work
-- Loading architecture spec of ram_memgen into library work
-- Loading entity fifo_sc1_rd_ctr into library work
-- Loading architecture spec of fifo_sc1_rd_ctr into library work
...
-- Loading entity xbus_ts_ctr into library work
-- Loading architecture spec of xbus_ts_ctr into library work
-- Compiling root entity xbus_ts_ctr(spec)
"gma.vhd",line 3570: Warning, expression value 1 TO 2112 can be out of
constraint range 0 TO 2111.
LEONARDO{3}: elaborate gma -work work
-- Compiling root entity gma(data_flow)
-- Compiling entity mc_sbus_if(data_flow)
...
-- Compiling entity ram_memgen(spec)
"gma.vhd",line 1746: Warning, component ramdata has no visible entity
binding.
-- Compiling entity sc1_ts_ctr(spec)
"gma.vhd",line 2851: Warning, expression value 1 TO 2430 can be out of
constraint range 0 TO 2429.
-- Compiling entity xbus_ts_ctr(spec)
"gma.vhd",line 3570: Warning, expression value 1 TO 2112 can be out of
constraint range 0 TO 2111.
-- Info, replacing xbus_ts_ctr(spec)
LEONARDO{4}: ungroup -all -hierarchy
20
LEONARDO{5}: pre_optimize .work.gma.data_flow -common_logic
-unused_logic -extract
-- Start pre-optimization for design .work.gma.data_flow
INFO: Using Counter counter_up_sclear_aclear_clock_clk_en_8.
INFO: Using Counter counter_up_sclear_aclear_clock_clk_en_8.
INFO: Using Counter counter_up_sload_sclear_aclear_clock_clk_en_3.
INFO: Using Counter counter_up_sload_sclear_aclear_clock_clk_en_2.
INFO: Using Counter counter_up_sload_sclear_aclear_clock_12.
LEONARDO{6}: load_modgen xi4
-- Reading module generator description from file
/tools/exemplar/leonardo_403/data/modgen/xi4.vhd
-- Reading vhdl file /tools/exemplar/leonardo_403/data/modgen/xi4.vhd
into library OPERATORS
-- Modgen File xi4.vhd Version 4.13
LEONARDO{7}: load_modgen xblox4
-- Reading module generator description from file
/tools/exemplar/leonardo_403/data/modgen/xblox4.vhd
-- Reading vhdl file /tools/exemplar/leonardo_403/data/modgen/xblox4.vhd
into library OPERATORS
-- Modgen File xblox4.vhd Version 4.4
LEONARDO{8}: resolve_modgen .work.gma.data_flow
-- Start module generator resolving for design .work.gma.data_flow
-- Resolving function mux with module generator
modgen_mux_64_small_false  from file xblox4.vhd
"gma.vhd",line 2353: Info, instance
instance_mc_sbus_if_instance_mc_if_modgen_5 infers mux
(size=64,signed=false,modgen_sel=small)
...
-- Resolving function inc with module generator
modgen_inc_2_small_false  from file xblox4.vhd
Info, instance xmplr_inst_1401_xmplr_inst_13 infers inc
(size=2,signed=false,modgen_sel=small)
Info, instance xmplr_inst_1436_xmplr_inst_52 infers inc
(size=12,signed=false,modgen_sel=small)
LEONARDO{9}: set infer_gsr TRUE
Info: setting infer_gsr to TRUE
set transformations TRUE
Info: setting transformations to TRUE
LEONARDO{9}: optimize .work.gma.data_flow -target xi4ex -effort Quick
-chip -area
-- Start optimization for design .work.gma.data_flow
Warning : The design contains some user hierarchy/blackboxes which WON'T
be processed for Global Set/Reset Signal.
Please flatten out the design if these lower level modules contains any
flip-flops or Latches.
                                                              
      Pass     Area    Delay     DFFs  PIs   POs --CPU--
               (FGs)    (ns)                      min:sec
      1        238       19       199    53    46   00:14 

                       Resource Use Estimate

        Technology:    xi4ex 
        Area:          238 Function Generators
        Critical Path: 19 ns
        DFFs:          199 (in CLBs or IOBs)
        IOFFs:         41 (in IOBs)
        HM CLBs:       0
        Input Pins:    53
        Output Pins:   46

Info, Added global buffer BUFG for port c20 
Info, Added global buffer BUFG for port c16 
LEONARDO{10}: write -format XNF gma.xnf
-- Writing file gma.xnf
LEONARDO{11}: 




{rausku:mark} [7] % ngdbuild -p xc4028xlhq208 gma gma.ngd
ngdbuild:  version M1.2.11
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.

Launcher: Using rule XNF_RULE
Launcher: gma.ngo being compiled because it does not exist
Launcher: Running xnf2ngd from /asic2/gma/xilinx/
Launcher: Executing xnf2ngd -p xc4000xl -u "gma.xnf" "gma.ngo"
xnf2ngd:  version M1.2.11
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.
   using XNF gate model
   reading XNF file 'gma.xnf' ...
   writing NGO file 'gma.ngo' ...
Launcher: xnf2ngd exited with an exit code of 0

Reading NGO file '/asic2/gma/xilinx/gma.ngo' ...
Reading component libraries for design expansion...

Running Timing Specification DRC...
Timing Specification DRC complete with no errors or warnings

Running Logical Design DRC...
WARNING:basnu - logical block
   'instance_xbus_sc1_converter_instance_rx1cas_dpram_u1' with type
'ramdata' is
   unexpanded
WARNING:basnu - logical block
   'instance_xbus_sc1_converter_instance_rx1data_dpram_u1' with type
'ramdata'
   is unexpanded
...
WARNING:basnu - logical block
'instance_mc_sbus_if_instance_mc_if_modgen_5_p1'
   with type 'MUXBUS' is unexpanded
WARNING:basnu - logical block
'instance_mc_sbus_if_instance_mc_if_modgen_5_bd1'
   with type 'BUS_DEF' is unexpanded
WARNING:basnu - logical block
'instance_mc_sbus_if_instance_mc_if_modgen_5_q0'
   with type 'ELEMENT' is unexpanded
WARNING:basnu - logical block
   'instance_mc_sbus_if_instance_mc_if_modgen_5_q0_duplicate_name_0'
with type
   'ELEMENT' is unexpanded
...
WARNING:basnu - logical net 'r<11>' has no driver
Logical Design DRC complete with 351 warnings

Ngdbuild Design Results Summary:
  There were 351 Logical Design DRC warnings
    851 total blocks expanded
Writing NGD file 'gma.ngd' ...

Writing ngdbuild log file 'gma.bld'...

Ngdbuild Done.
{rausku:mark} [17] % map -p xc4028xlhq208 gma.ngd  
map -p xc4028xlhq208 gma.ngd 
map:  version M1.2.11
Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.
Reading NGD file 'gma.ngd'...
Speed grade not specified.  Using default '-3'.
Using target part '4028xlhq208-3'.
map xc4000xl directives:
   Partname="xc4028xlhq208".
   No Guide File specified.
   No Guide Mode specified.
   Covermode="area".
   Coverlutsize=4.
   Coverfgsize=4.
   Perform logic replication.
   Pack CLBs to 100%.
Processing logical timing constraints...
Running general design DRC...
ERROR:basnu - logical block
   'instance_xbus_sc1_converter_instance_rx1cas_dpram_u1' with type
'ramdata' is
   unexpanded
ERROR:basnu - logical block
   'instance_xbus_sc1_converter_instance_rx1data_dpram_u1' with type
'ramdata'
   is unexpanded
...
ERROR:basnu - logical block
'instance_mc_sbus_if_instance_mc_if_modgen_5_p1'
   with type 'MUXBUS' is unexpanded
ERROR:basnu - logical block
'instance_mc_sbus_if_instance_mc_if_modgen_5_bd1'
   with type 'BUS_DEF' is unexpanded
ERROR:basnu - logical block
'instance_mc_sbus_if_instance_mc_if_modgen_5_q0'
   with type 'ELEMENT' is unexpanded
ERROR:basnu - logical block
   'instance_mc_sbus_if_instance_mc_if_modgen_5_q0_duplicate_name_0'
with type
   'ELEMENT' is unexpanded
...
WARNING:basnu - logical net 'r<11>' has no driver
{rausku:mark} [18] %
Article: 6971
Subject: Re: Selection Criteria for CPLD's/FPGA's
From: edndipert@postoffice.worldnet.att.net (Brian Dipert)
Date: Thu, 17 Jul 1997 13:15:53 GMT
Links: << >>  << T >>  << A >>
Pretty easy. Shoot over to <http://www.ednmag.com>. Since the article
is a few issues old, you'll probably have to register before you can
get access to it. It was the cover story in the May 22 issue. Look for
my next programmable logic article in the upcoming August 1 issue.

>
>Can you post or let people know where to read this EDN
>article - on-line? --- Thanks.

Brian Dipert
Technical Editor
EDN Magazine: The Design Magazine Of The Electronics Industry
1864 52nd Street
Sacramento, CA   95819
(916) 454-5242
(916) 454-5101 (fax)
edndipert@worldnet.att.net
Visit me at <http://members.aol.com/bdipert>
Article: 6972
Subject: Exists a special measurement newgroup?
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Thu, 17 Jul 1997 17:33:01 +0200
Links: << >>  << T >>  << A >>
Does somebody know if a specal measurement newgroup exists?

Especially for Logic Analyzers and DSO´s, JTAG etc?

Thanks
Best regards
Martin


martin.vorbach@scrap.de
Fon +49 721 97243 35
Fax +49 721 97243 28



Article: 6973
Subject: How is the ALTERA 10K100 IO-Pin state before (!) configuration (I
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Thu, 17 Jul 1997 18:29:19 +0200
Links: << >>  << T >>  << A >>
How is the ALTERA 10K100 IO-Pin state in the time gap between power on
and nSTATUS activation?


Best regards
Martin


martin.vorbach@scrap.de
Fon +49 721 97243 35
Fax +49 721 97243 28



Article: 6974
Subject: looking for a contract opening
From: dann@freenet.nether.net (Man`y)
Date: 18 Jul 1997 00:14:21 GMT
Links: << >>  << T >>  << A >>
Hi, 
  I would like to have information of any contracts that may
be available for the contract of any FPGA design synthesis
testing etc part time jobs. 
  
Thanks



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