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Messages from 7250

Article: 7250
Subject: Re: Should Xiling have more local clock nets?
From: Steve Lass <lass@xilinx.com>
Date: Mon, 18 Aug 1997 23:34:46 -0600
Links: << >>  << T >>  << A >>
Stuart Clubb wrote:

> On 13 Aug 1997 22:48:15 GMT, lass@xilinx.com (Steve Lass) wrote:
>
> >M1 does support the MAXSKEW constraint which can be used for clock nets.
>
> Please excuse my lack of knowledge, but does M1 support 3K series, the
> origin of this thread from Peter?

We are shipping 3K beta this week.  Official support for 3K in M1 willbe in
November.

> Isn't this "preference" from the original NeoCAD engine anyway?
>

Yes.

Steve


Article: 7251
Subject: FPGA Express...
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Tue, 19 Aug 1997 10:36:12 +0200
Links: << >>  << T >>  << A >>


	[M.Vorbach]  ;-))
	Nice try.

>  
> Will someone please send me
> the file License.dat for
> FPGA Express v1.2?
> Mine is corrupt!
> 
> 

Article: 7252
Subject: 10K100 socket?
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Tue, 19 Aug 1997 10:48:35 +0200
Links: << >>  << T >>  << A >>
> Roger,
> 
	[M.Vorbach]  MCKENZIE has normal (non zero insertion force)
sockets:
	810 Page Avenue
	Fremont, California 94538 USA
	Telephone (510) 651-2700
	Fax (510) 651-1020

	We use also single pin sockets and mount 503 pieces of them.
Supplier is:
	RS Components
	Part. No. 519-959
	The advantage is, that the heigth of the board is not much
higher than by mounting the FPGAs without sockets.

> In article <33F334B7.7F9E@net.polyu.edu.hk>,
>    "Yau Man Wai , Roger" <rogeryau@net.polyu.edu.hk> wrote:
> >Hello,
> >	I ordered a Altera 10K100GC503. I have search for AMP amd
> >3M but no such high pin counts PGA socket for this device, does 
> >anyone know where can I order a 503 pins PGA socket for this device?
> >Thank you!
> >
> >Roger Yau
> >R & D Engineer
> >Easson Precision Ltd.
> >http://www.net.polyu.edu.hk/~rogeryau

Article: 7253
Subject: MaxPlusII from Altera.
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Tue, 19 Aug 1997 10:51:52 +0200
Links: << >>  << T >>  << A >>
Sometimes I believe that XILINX-fitting is better. But only sometimes
and this is an architectural problem.
We had problems using 9K-technology, but within 2 weeks we got help from
ALTERA (a bug fix). 10K works (up to now) great.

I believe the tool is OK and the support too.


> can anybody compare this tool with other comparable tools?
> 
> how easy is it to learn?how is the support?
> __________________________________________________________________

Article: 7254
Subject: LogiBLOX components in VHDL?
From: Exjobbare Joachim Strombergson <qmwchim@emw.ericsson.se>
Date: Tue, 19 Aug 1997 12:40:30 +0200
Links: << >>  << T >>  << A >>
Hi!

I'm having problems using LogiBLOX components as component instances in
my VHDL-code. I'm using the LBGUI tool to customize the blocks to match
my need. I then try to include these block in my code by inserting the
generated VHI-file into my code and completing the port assignments. But
when I try to read in the design into Synopsys Design Analyzer the tool
does not recognize the component.

I either would like to inlude the LogiBLOX like any other library, and
then customize the component with attributes (but don't know how), or
somehow make Synopsys realize that the implementation of the component
is given by the generated netlist in the NGO-file.

I've read through the material in the dltext documentation, but it
doesen't help me out.

Any help greatly appreciated.
Joachim Strömbergson
Article: 7255
Subject: Re: ISP Stories
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Tue, 19 Aug 1997 11:50:40 +0100
Links: << >>  << T >>  << A >>
Graham Rhodes wrote:
> 
> Tim Conway wrote ...
>> We are considering the use of ISP CPLD's  Anyone have any amusing
>> or helpful anecdotes regarding their use?
> 
>..cut.. 
>I currently use cypress ISP parts, and have no real problems with
>programming them - it all works very nicely. The only minor snag is that >they need a 12V programming voltage. Cypress gets away with this by
>creating this in the PC cable. Other devices are nicer and only need
>a 5V programming voltage (AMD?)

An advantage of requiring external 12V supply for programming is that
the internal charge pump circuit is eliminated.  That makes the device
more robust in terms of effects of Vcc overvolts (in my experience an 8V
Vcc spike on a 5V-only programmable part destroys it completely, 10V Vcc
spike had no ill effects on a part using 12V programming - both spikes
were outside data book ratings of the standard 7V absolute maximum). 
Downsides are obvious (extra pin, extra net to be routed, have to
generate 12V somehow, etc).  It depends on the intended product type
whether the swings are nicer than the roundabouts.

ISP of any form has many plus points which are set out by all
manufacturers offering it.  Not sure any qualify as "amusing", but they
can be truly helpful.  I can repeat my anecdote of how to blow up
Lattice ispLSI if you like, but that was not amusing either.

Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK

The University is not responsible for my opinions
Article: 7256
Subject: Re: ISP Stories
From: sja@gte.net (Steven J. Ackerman)
Date: 19 Aug 1997 13:25:47 GMT
Links: << >>  << T >>  << A >>
On Fri, 15 Aug 1997 12:37:26 -0500, Tim Conway <timc@primafacie.com>
wrote:

>We are considering the use of ISP CPLD's.  Anyone have any amusing
>or helpful anecdotes regarding their use?
>Thanks much.
>-- 
>Tim Conway
>Prima Facie, Inc.
>(314) 989-0644 ext. 16
>(314) 989-0654 Fax

I don't know if its amusing or not but...

If you're using Lattice parts, you have to fully complete and debug
your design before you lay out a circuit board. And the signal pinout
will be completely arbitrary, not easily circuit board routable. If
you think that you can go in and re-assign pinouts or make logic
changes after the fact you may be in for a nasty suprise - the Lattice
router may no longer be able to fit your design into the part ! I have
found this to be the case if the part is over 50% utilized.

The Synario software is easy to use, much better than their own PDS.

Other than these discrepancies we find the Lattice parts to be useful
and have shipped several thousand units of various designs with no
manufacturing problems.

Steven J. Ackerman, Consultant
ACS, Sarasota, FL
sja@gte.net
http://www.acscontrol.com
Article: 7257
Subject: FPGA prototyping board
From: Bjorn Sihlbom <emwbs@emw.ericsson.se>
Date: Tue, 19 Aug 1997 16:38:59 +0200
Links: << >>  << T >>  << A >>
Hi!

I need to prototype a board incl. a complex ASIC.
Do anyone know about of-the-shelf boards with space for a lot of big
FPGAs and perhaps configurable routing?

Any other hints?

Regards,

Bjorn.
Article: 7258
Subject: Re: MaxPlusII from Altera.
From: aquantz@ibm.net (Aaron Quantz)
Date: Tue, 19 Aug 1997 14:42:40 GMT
Links: << >>  << T >>  << A >>
I'm not sure about other tools but I've been using this for about a
year and have NO compalaints. I'm doing a 10k20 desgn.
>
>can anybody compare this tool with other comparable tools?
>
>how easy is it to learn?how is the support?
>
>thnaks
>umesh
>
>__________________________________________________________________
>Undertake something that is difficult,it will do u good;
>Unless u try to do something beyond what u have already mastered
>you will never grow
>			-:Ronald E Osborn
>__________________________________________________________________
>


Regards,
Aaron Quantz                    \^ ^/
                                )@ @(
+---------------------------oOO--(_)------------------------------------+
+ Mgr Software Development, Turret Control Systems                      +
+ HR Textron                        | Phone: (805) 253-5471             +
+ 25200 W. Rye Canyon Rd.           | Fax:   (805) 253-5962             +
+ Valencia, CA USA 91355-1265       | Email: aquantz@ibm.net            +
+ Visit the Textron web site: http://www.textron.com                    +
+-----------------------------------Oooo--oOO---------------------------+
                              oooO (   )
                             (   )  ) /
                              \ (  (_/
                               \_)
Article: 7259
Subject: Re: ISP Stories
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Tue, 19 Aug 1997 08:25:56 -0700
Links: << >>  << T >>  << A >>
Graham Rhodes wrote:
<snip>
> I currently use cypress ISP parts, and have no real problems with
> programming
> them - it all works very nicely. The only minor snag is that they need a
> 12V programming voltage. Cypress gets away with this by creating this in the
> PC cable. Other devices are nicer and only need a 5V programming voltage
> (AMD?)
> 
 This is a two edged sword - Sure 5V is convienent, BUT I'd feel happier
shipping
product that was GUARANTEED to never kick into PGM mode by 'accident'.
 ( see an earlier posting about being careful about PowerUP / ISP
plugging order )

 The other advantage of 12V, is it allows the ISP pins to be SYSTEM
available,
the 5V only parts cannot do this.
 Also a SPI interface / connector for ISP, that is also RUNTIME
accessible, has to be
appealing.
 On FLASH PROM devices, which are runtime written, 5V makes sense, but
surely not on CPLD ?

Maybe the ideal solution is BOTH voltage options, with one die, but
factory selected to
5V for RunTime PGM customers, and 12V for factory/safe PGM.

- jim

-- 
======= Manufacturers of Serious Design Tools for uC and PLD  =========
= PLD Applications libraries available, for i2c, SPI, SPL
= for more info, Email : DesignTools@xtra.co.nz  Subject : c51Tools


Article: 7260
Subject: Re: 89c2051 Price & Capability (was Ourtageous Serial EEPROM $$)
From: Bill Ewing <bewing@imxtech.com>
Date: Tue, 19 Aug 1997 11:42:20 -0400
Links: << >>  << T >>  << A >>
Thanks for the info. But what the *@#$ are you saying? I had assumed
89c2051s are 8051 object compatible. Is "i2c" the serial protocol used
by "24Cxx" parts? Is "SPI" "Serial Programming Interface", for
programming Xilinxes? (a wheel I didn't need to re-invent?) In that
case, i2c -> SPI makes sense, but it's the verification that's rough.
What would I use an "SPI <-> SPI data pump" for? Have I slept through an
important but quiet revolution?

jim granville wrote:
> > > Have look at the 89C2051 ( 20 pins ) and the new SPI DataFLASH from
> > > ATMEL.
> > About how much does a low-end (slow, OTP) 89C2051 cost?
>  Here they are between $3-4US, in small quantities. For this you get
> DIP2O or SO20, and 2K FLASH with 128 Bytes RAM, 24MHz Clock, 2.7-6V Vcc.
> They will run your 80C52 SPI code unchanged.
> ( the 89C1051 is cheaper again, with 1K FLASH, 64 Bytes RAM, and an ISP
> version is comming ... )
> 
>  i2c LIB will cost appx 105 bytes, and SPI is appx 60, so you can do a
> 24Cxx <-> SPI or SPI <-> SPI data pump with a lot of room to spare.
Article: 7261
Subject: Re: Xilinx & Altera using same configuration lines?
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 19 Aug 1997 10:37:11 -0700
Links: << >>  << T >>  << A >>
There is a basic difference between the Xilinx and Altera daisy-chain
structure:
In the Xilinx case, all configuration data is passed through the daisy
chain, while ( I think ) in the Altera case it is an ENABLE signal that
is passed through the daisy chain.

Xilinx devices count every rising edge of CCLK in their internal length
counters ( "every " means each and every one ! ), and they all pass the
preamble through the daisychain. After the preamble, the head of the
daisy chain consumes data until it is full, then passes the incoming
data through to the next device, which consumesit until it is full, etc.

It might be quite a challenge to combine these bitstreams, and I ask:
Why do it? Why not run them in parallel ?

Peter Alfke Xilinx Applications

Article: 7262
Subject: Re: FPGA prototyping board
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 19 Aug 1997 18:02:08 GMT
Links: << >>  << T >>  << A >>

APTIX makes such a board.

In article <33F9B003.1381@emw.ericsson.se> Bjorn Sihlbom <emwbs@emw.ericsson.se> writes:
>Hi!
>
>I need to prototype a board incl. a complex ASIC.
>Do anyone know about of-the-shelf boards with space for a lot of big
>FPGAs and perhaps configurable routing?
>
>Any other hints?
>
>Regards,
>
>Bjorn.


Article: 7263
Subject: Re: Xilinx & Altera using same configuration lines?
From: Jose Paredes <josep@austin.ibm.com>
Date: Tue, 19 Aug 1997 13:08:34 -0500
Links: << >>  << T >>  << A >>
Dirk,

What exactly do you mean by the "same" configuration lines? You should
be able to connect the "DONE" pins together in both the Altera and
Xilinx parts so that the two set of devices wake up together. 

Jose
-- 
Jose A. Paredes

IBM RS/6000 Division
Office: 512-838-3855
Fax:    512-838-1852 
josep@austin.ibm.com
Article: 7264
Subject: Re: Help!!!!
From: "Austin Franklin" <dark9room@ix.netcom.com>
Date: 19 Aug 1997 18:25:39 GMT
Links: << >>  << T >>  << A >>
> Can anyone come up with a plausible explanation of how this could be
legit?
> Better yet, given that license.dat files are usually associated with a
> physical key (and the serial number it contains), or as in M1, the serial
> number of the C drive, can anyone come up with a way that sending your 
> license.dat file to this person could be anything other than pointless.

Better yet, that the license.dat file is a text files!  A text file could
still be corrupted....but it shouldn't be that hard to repair...and they
usually send it to you in e-mail, or on a disk...so....where's the
original?

Austin

Article: 7265
Subject: Xilinx PCI simulation problem...
From: "Austin Franklin" <dark9room@ix.netcom.com>
Date: 19 Aug 1997 19:02:10 GMT
Links: << >>  << T >>  << A >>
The PCI bus spec guarantees 7ns setup and 0ns hold.  In order to meet the
PCI spec, the 4k IOB flip flops have to be set to delay...which claims to
require a 7ns setup, and 0ns hold.

Ok, all that seems fine...but when I generate a .vsm file and simulate this
using ViewSim and a command file that gives 7ns setup and 0ns hold, I get
setup violations..claiming setup is 6.2, 10.2 is required.  Interestingly
enough, it's not the 7ns setup that is causing the problem, it's the 0ns
hold.  When I change the 0ns hold to 11, it works fine.

Now...my first guess is something is wrong with the timing model that
Xilinx provides.  I have not gone into the .vsm file to see what it is that
is wrong, but I am about to.

What my question is, has anyone simulated a Xilinx PCI design using ViewSim
and using 7ns setup and 0ns hold....successfully?

Thanks,

Austin Franklin
darkroom@ix.netcom.com

To reply to this post, remove the number from the reply address.

Article: 7266
Subject: Re: MaxPlusII from Altera.
From: Gerhard Vogt <Gerhard.Vogt@newbridge.com>
Date: Tue, 19 Aug 1997 13:22:29 -0700
Links: << >>  << T >>  << A >>
Umesh Nair wrote:
> 
> can anybody compare this tool with other comparable tools?
> 
> how easy is it to learn?how is the support?
> 
> thnaks
> umesh
> 
> __________________________________________________________________
> Undertake something that is difficult,it will do u good;
> Unless u try to do something beyond what u have already mastered
> you will never grow
>                         -:Ronald E Osborn
> __________________________________________________________________
Hi Umesh,

I have used the software over a few years now, and it's really
easy to work with it.
I prefer the Altera sw instead of some sw from Xilinx for
example.

Regards

	Gerhard Vogt
-- 
------------------------------------------------------------------------------------------------------------------
Gerhard Vogt                                                      |   
Newbridge Networks Corporation
E-mail: Gerhard.Vogt@newbridge.com    |    Suite 301, 8555 Baxter Place
Phone: (604) 421-2643 Ext. 5718                   |    Burnaby, BC
Direct: (604) 415-1400-5718                            |    Burnaby, BC
Fax:   (604) 421-2644                                         |   
Canada, V5A 1V7
PGP Key available                                           
---------------------------------------------------------------------------------------------------------------------
Article: 7267
Subject: Re: Price of Serial EEPROM is Outrageous
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Tue, 19 Aug 1997 20:53:13 -0700
Links: << >>  << T >>  << A >>
Bill Ewing wrote:
> 
> jim granville wrote:
<snip>
> > Have look at the 89C2051 ( 20 pins ) and the new SPI DataFLASH from
> > ATMEL.
> > This has 4MBit Serial FLASH, at under ByteWIDE prices.
> 
>   Yes, I've seen the recent discussion. I often need a few I/O pins, but
> I guess you can get that through the Xilinx, once it's operational.
> About how much does a low-end (slow, OTP) 89C2051 cost? I have a pending
> (i.e., overdue) project I think it might fit into.

 Here they are between $3-4US, in small quantities. For this you get 
DIP2O or SO20, and 2K FLASH with 128 Bytes RAM, 24MHz Clock, 2.7-6V Vcc.
They will run your 80C52 SPI code unchanged.
( the 89C1051 is cheaper again, with 1K FLASH, 64 Bytes RAM, and an ISP
version is comming ... )

 i2c LIB will cost appx 105 bytes, and SPI is appx 60, so you can do a 
24Cxx <-> SPI or SPI <-> SPI data pump with a lot of room to spare.

- jim

-- 
======= Manufacturers of Serious Design Tools for uC and PLD  =========
= Optimising Modula-2 Structured Text compilers for ALL 80X51 variants
= Reusable object modules, for i2c, SPI and SPL bus interfaces
= Safe, Readable & Fast code - Step up from Assembler and C
= Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55
= *NEW* Bondout ICE for 89C51/89C52/89C55 
= for more info, Email : DesignTools@xtra.co.nz  Subject : c51Tools


Article: 7268
Subject: Re: LogiBLOX components in VHDL?
From: Tim Warland <twarland@NOSPAMnortel.ca>
Date: Wed, 20 Aug 1997 08:46:35 -0400
Links: << >>  << T >>  << A >>
Exjobbare Joachim Strombergson wrote:
>
> I'm having problems using LogiBLOX components as component instances in
> my VHDL-code. I'm using the LBGUI tool to customize the blocks to match
> my need. I then try to include these block in my code by inserting the
> generated VHI-file into my code and completing the port assignments. But

This is the problem.  DO NOT insert the code into your code.  The VHDL
output is really just a simulatable model, NOT a synthesizable model.
You should treat the logiblox as a hierarchical piece of the code and
instantiate the module as a lower hierarchy.  

> when I try to read in the design into Synopsys Design Analyzer the tool
> does not recognize the component.

Correct, because it is not synthesizeable.  You just used LBGUI to
optimize
the block, don't get Synopsys to have its way with it.  The NGO output
of the logiblox IS the synthesized code.  In your hierarchical design,
you need a synthesis black_box or similar don't touch attribute to get
synopsys to compile the design correctly but not synthesis the LogiBlox
component. 
> 
> I either would like to inlude the LogiBLOX like any other library, and
> then customize the component with attributes (but don't know how), or
> somehow make Synopsys realize that the implementation of the component
> is given by the generated netlist in the NGO-file.
> 
LogiBlox does customize the component and you do include the component
like any other library.  I suggest you look in the documentation for
examples of including logiblox components. (I'd give it a shot but
I'm a verilog guy).

Tim.
-- 
You better be doing something so that in the future
you can look back on "the good old days"

My opinions != Nortel's opinion;
Article: 7269
Subject: Re: ISP Stories
From: Tim Conway <timc@primafacie.com>
Date: Wed, 20 Aug 1997 12:42:41 -0500
Links: << >>  << T >>  << A >>
jim granville wrote:
> 
> Steven J. Ackerman wrote:
> >
> <snip>
> > If you're using Lattice parts, you have to fully complete and debug
> > your design before you lay out a circuit board. And the signal pinout
> > will be completely arbitrary, not easily circuit board routable. If
> > you think that you can go in and re-assign pinouts or make logic
> > changes after the fact you may be in for a nasty suprise - the Lattice
> > router may no longer be able to fit your design into the part ! I have
> > found this to be the case if the part is over 50% utilized.
> 
> Yikes!
> We have just completed a design where we routed the PCB FIRST !
> ( using ATMEL ATF1500 PLDs, 100% & 87% packed )
Yes, but doesn't that series have a fully populated switch matrix.
It's a very nice feature to be able to lay out your PCB before you do 
the logic.  However, correct me if I'm wrong, aren't you
limited to 32 macrocells and a 15ns Tpd with the Atmel parts?

> This 'my fitter knows best' philosophy is too common, but with pressure,
> things will
> get better :-)
True, very true.  Both with the fitters and with the parts themselves.  
A Vantis marketing guy told me that they have a new generation of CPLD's
coming
that are designed based on the fitter, as opposed to designing the
fitter
to work with the PLD.  An interesting concept.  

-- 
Tim Conway
Prima Facie, Inc.
(314) 989-0644 ext. 16
(314) 989-0654 Fax
Article: 7270
Subject: Re: 89c2051 Price & Capability (was Ourtageous Serial EEPROM $$)
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Wed, 20 Aug 1997 10:46:19 -0700
Links: << >>  << T >>  << A >>
Bill Ewing wrote:
> 
> Thanks for the info. But what the *@#$ are you saying? I had assumed
> 89c2051s are 8051 object compatible.  
 Correct. I mentioned this because not all tiny C51's were 100%
compatible.
Fortunately the 2051 is just a C51 in 20 Pin Box.

> Is "i2c" the serial protocol used by "24Cxx" parts? 

 Yes. i2c is the Philips Inter IC bus, also called 'two wire' bus by
those
paranoid about acknowledging Philips :-)
 Many suppliers make 24C16/32/64/128/256 K Bit Serial EEPROMS/FLASH.
They are probably cheaper than the more niche 17xxx FPGA series.

> Is "SPI" "Serial Programming Interface", for programming Xilinxes? (a wheel I didn't need to re-invent?)
 Serial Peripheral Interface, is a simpler BUS than i2c, and is very
similar to JTAG - HW level.
Typically you have a long shift register ::
 CLK
 MISO  - Master In, Slave Out
 MOSI  - Master Out, Slave IN
 CS    - Some form of ChipSelect.

> In that case, i2c -> SPI makes sense, but it's the verification that's rough.

> What would I use an "SPI <-> SPI data pump" for? Have I slept through an
> important but quiet revolution?

Here I used SPI to mean CLK.DATI.DATAO Shifter BUS
The DataFLASH devices I mentioned are serial ( SPI R/W interface, SO28
package ), and the XILINX
and other FPGAs are also Serial, but with different Start.Block.Stop
requirements,
so you would use a SPI-SPI pump to handle these differences, tho mostly
the data
stream would be simply duplicated. 
 
- jim


Article: 7271
Subject: Re: ISP Stories
From: terry.harris@dial.pipex.com (Terry Harris)
Date: Wed, 20 Aug 1997 18:11:38 GMT
Links: << >>  << T >>  << A >>
jim granville <Jim.Granville@xtra.co.nz> wrote:

>> If you're using Lattice parts, you have to fully complete and debug
>> your design before you lay out a circuit board. And the signal pinout
>> will be completely arbitrary, 

>I shudder to think how a 'PLD determined' design would have performed
>:-(

>This 'my fitter knows best' philosophy is too common, but with pressure,
>things will get better :-)

It isn't a case of fitter knows best it is a case of CPLD
architectural restrictions  and all CPLDs have them to a greater or
lesser degree. 

If you lock down pins to guide a fitter towards a possible solution
then you are making life easy for it. If you lock down pins towards an
impossible solution then you make it work hard and end up with
something that will probably break with a small design change. 

Lattice parts are a little quirky, having a more complex set of small
restirctions than Xilinx 9500 or Altera 7000 for example. When you
begin to understand the architectural restrictions you begin to
understand if and how you can guide the fitter. 

Lattice parts have a GRP (global routing pool) which can route any
signal anywhere but unfortunately with some undocumented limitations,
when you lock down pins and the fitter can't fit (which sounds like
the problem the previous poster was getting) it is because of these
GLB restrictions. Being undocumented it is pretty hard to know what to
do about it. 


Cheers Terry...
Article: 7272
Subject: Re: ISP Stories
From: "Joel W. Kolstad" <Joel.Kolstad@Techne-Sys.com>
Date: 20 Aug 1997 20:52:03 GMT
Links: << >>  << T >>  << A >>
Steven J. Ackerman <sja@gte.net> wrote in article
<5tc6sr$6l9$1@gte2.gte.net>...
> If you're using Lattice parts, you have to fully complete and debug
> your design before you lay out a circuit board. And the signal pinout
> will be completely arbitrary, not easily circuit board routable. If
> you think that you can go in and re-assign pinouts or make logic
> changes after the fact you may be in for a nasty suprise - the Lattice
> router may no longer be able to fit your design into the part !

Cypress likes to pride themselves on the ability to use completely
arbitrary pin assignments when they're trying to convince you to use their
stuff over Lattice's.  In general I think they're correct, but one thing
they don't mention is that even their pin assignments start becoming
non-arbitrary when you start utilizing over about 75% of the device. 
Better than Lattice, but definitely not as cool as they'd have you believe.

With FPGAs the problem is that you may not be able to get a signal over to
the pin you want it _fast_ enough, right?

								---Joel Kolstad

Article: 7273
Subject: Re: FPGA prototyping board
From: "Raymond E. Rogers" <rrogers@voyager.net>
Date: Wed, 20 Aug 1997 17:54:49 -0400
Links: << >>  << T >>  << A >>
Try vcc.com.  We bought one on a isa card; the software support for
general purpose win95 use was sad but it works and I am now integrating
it into win95 succesfully ( after much trial and error).  OTOH they are
activily supporting multi FPGA systems for something like "virtual"
computing or some such.

Enjoy
Ray
Article: 7274
Subject: Pamela & Tommy Lee's Secret Sex Tape
From: aflkjasdl@alfjasdfjs.com
Date: 20 Aug 97 22:08:56 GMT
Links: << >>  << T >>  << A >>

                DON'T BE FOOLED BY IMITATIONS


There is only one Pam & Tommy Sex Tape and it is available here for a
limited time only.  Others may claim to have it for sale but this is the only
Hard Core Copyrighten version in existence.  See them bare their soles
and bodies in public places, but observe closely, a very private blend
of love and sex that they thought the public would never see.



Visit:

	

			http://www.pamsex.com



			http://www.pamsex.com


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