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Messages from 7375

Article: 7375
Subject: Re: export pins from MAX+ to orcad schem symbol
From: eteam.nospam@aracnet.com (bob elkind)
Date: Thu, 4 Sep 1997 06:19:14 +0100
Links: << >>  << T >>  << A >>

bob elkind said...
> Anyone have a clue, what is the simplest and most reliable
> means for exporting post-compile pinouts from Altera's
> MAX+II to OrCad or Protel, for generating a schematic symbol
> for board design?
> 
> There must be a simple solution, since this is otherwise a
> horribly tedious, error-prone, and repetitive task.

I'll answer my own question...

1. In MAX+2, select the compiler window.
2. Check Interfaces/EDIF netlist writer
3. under Interfaces/EDIF netlist writere settings...
    a.  EDIF 2 format
    b.  map illegal characters
    c.  flatten bus
    d.  write delays constructs <somewhere else>
4. Run the compiler.  This generates a .EDO EDIF2 netlist

In Orcad Express (I don't know if this works in Capture):

5.  execute Tools/Genereate Symbol
    a. specify the EDIF2 netlist written by MAX+2
    b. check the "specify the number of pins" box, and fill
       in the number.

6.  After the part info is loaded, you have an Orcad part defined!

If you want to proceed further to Protel...

7.  In Orcad Express, save the new part information as a SDT4
    (*not* 386+) library file.

8.  Find the decomp.exe library decomposer program from old
    SDT4 (for DOS).  Run this program on the saved SDT4
    format library file.  The result is an ascii .SRC file.

In Protel,

9.  Open the .SRC file as an Orcad Library file.

10. The part is now read into Protel, and you can do with it
    what you will.

It's that simple!  If anyone has a simpler method, I'd love
to hear from you.  But at least we have *one* method that
(more or less) works.

-- Bob Elkind


****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 7376
Subject: A fpga DMA design ?
From: David Payne <davidp@freelance.gen.nz>
Date: Thu, 04 Sep 1997 20:11:59 +1200
Links: << >>  << T >>  << A >>
Hi All.

I am looking at using a fpga do do a simple DMA controller,
is there any designs out there that would help me to get a start.

it is for a 32bit 68000 micro working on a 16bit bus between an 8 bit
port and 16bit ram so I only need one counter and start & stop
registers and the 8 bit port pointer register

any advice any could give would be helpfull

regards David.

--
David Payne   email_davidp@freelance.gen.nz_


Article: 7377
Subject: Re: ANNOUNCE: VHDL Synthesis for $495
From: Uwe Bonnes <bon@hertz.ikp.physik.th-darmstadt.de>
Date: 4 Sep 1997 10:09:25 GMT
Links: << >>  << T >>  << A >>
In comp.cad.synthesis Kevin Bush <kevin.bush@minc.com> wrote:
...

: VHDL EASY is currently available for Windows 95 and Windows NT,
: although we are considering Linux. We still need to look at the 
: impact on our GUI, etc.

: What other EDA type tools are available on Linux?

Hallo,

have a look at http://SAL.KachinaTech.COM/, which is a comprehensive listing
of available applicatiuons for Linux. 
At present, for most EDA Work I have to do,  I have to shut down Linux and
boot Win95. But I would like to have this situation changed.


Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.th-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 7378
Subject: Re: daisy-chained bitstreams
From: johna@dvorak.amd.com (John Archambeault)
Date: 4 Sep 1997 15:17:57 GMT
Links: << >>  << T >>  << A >>


I had the same problem only with 3100A.  The way around it is a bit convaluted,
but it does work.  Use the prom makeing tool to set it up as if a monster PROM
was going to perform a serial download.  Then, juse feed that PROM file into
the XCHECKER (name?) PC download cable.  It will accept PROM files.

Good Luck,
John

BTW:  I documented this a while back, but am going from memory right now.  If
you still can't get it, e-mail and I'll check the old documents.
-- 
John Archambeault
Article: 7379
Subject: Re: daisy-chained bitstreams
From: bill smith <bill@bill.inc>
Date: Thu, 04 Sep 1997 10:15:30 -0700
Links: << >>  << T >>  << A >>
Neil wrote:
> 
> Ive been working with the old Xilinx XC2064 LCA's for a while, using the PC
> to download bitstreams to the LCA in Master Serial mode.
> 
> What I'm trying to do now however is to daisy-chain a second LCA in Slave
> Serial mode. Although the hardware seems quite straight forward I haven't
> been able to daisy-chain the bitstream file for download in a serial
> format...
> 
> Has anybody out there come across this problem (and hopefully solved it) ?
> 
> I would be grateful if anybody with any suggestions could drop me a mail.

Neil,
you used the keywords "download" and "PC" in the same sentence, so i'm
going to assume that you were using xchecker.exe to deal with the cable. 

Xilinx screwed-up the build of xchecker.exe, and it will not do daisy
chains.  try using the copy of xck88.exe from the command line, it will
work.

bill
email is bill@2ez.com
Article: 7380
Subject: Re: ISP Stories
From: "Joel Kolstad" <Joel.Kolstad@Techne-Sys.com>
Date: 4 Sep 1997 19:53:04 GMT
Links: << >>  << T >>  << A >>
Daniel Elftmann <dane@usinternet.com> wrote in article 
> Management started pushing designs into layout with designs 50% complete
> and no simulation on a regular basis arguing that with ISP the risk was
> minimal.

I can see doing this so long as they don't actually start _selling_ those
boards until everything has been verified.  The whole reason that
management pushes this kind of thing is because they know that skilled
engineers such as you :-) will, most of the time, get all the major stuff
correct the first time around anyway and will only need to make minor
changes -- which ISP can do just fine.

								---Joel Kolstad

Article: 7381
Subject: September 8th Meeting - The PARALLEL Processing Connection
From: m-node@ix.netcom.com (B. Mitchell Loebel, Executive Director)
Date: Thu, 04 Sep 1997 17:20:36 -0700
Links: << >>  << T >>  << A >>
What is a CPU ³instruction²? What consequences do  the organization of 
³instruction resources" have on computing efficiency? MATRIX is a 
research project at UC Berkeley which addresses these questions. Its 
instruction resources consist of an array of 8-bit ALU and register-file 
building blocks interconnected via a byte-wide network. The MATRIX 
architecture defers the binding of instruction resources until run time, 
allowing the application to organize resources according to its needs. With 
today¹s silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-
bit ops).  A 0.6u CMOS university prototype running at 50MHz delivers 
1.8 Gop/s (8-bit ops) in 130 sq. mm.

In his presentation, André Dehon will describe a simple model of 
instruction resource organization and computing efficiency which can help 
us understand the architectural space in which we build programmable 
computing devices (Processors, FPGAs, VLIW, Vector, SIMD, MIMD...). 
We¹ll see that rigid, fabrication-time organization of instruction resources 
significantly narrows the range of efficiency for conventional 
architectures. 


The main meeting starts promptly at 7:30PM at Sun Microsystems at 901 
San Antonio Road in Palo Alto.  This is just off the southbound San 
Antonio exit of 101.  Northbound travelers also exit at San Antonio and 
take the overpass to the other side of 101.  A discussion of member 
projects currently underway and other issues of interest to entrepreneurs 
follows immediately thereafter at 9:15PM.


Please be prompt; as usual, we expect a large attendance; don't be left out 
or left standing.  There is a $12 fee for non-members and members will be 
admitted free.  Yearly membership fee is $65.

-- 
B. Mitchell Loebel
Executive Director
The PARALLEL Processing Connection
408 732-9869 (USA)
Article: 7382
Subject: The PARALLEL Processing Connection - What Is It?
From: m-node@ix.netcom.com (B. Mitchell Loebel, Executive Director)
Date: Thu, 04 Sep 1997 17:34:38 -0700
Links: << >>  << T >>  << A >>
Subject:  The PARALLEL Processing Connection - What Is It?



The PARALLEL Processing Connection is an entrepreneurial association; 
we mean to assist our members in spawning very successful new 
businesses involving parallel processing.

Our meetings take place on the second Monday of each month at 7:30 PM 
at Sun Microsystems at 901 South San Antonio Road in Palo Alto, 
California. Southbound travelers exit 101 at San Antonio ; northbound 
attendees also exit at San Antonio and take the overpass to the other side 
of 101. There is a $12  visitor fee for non-members and members ($65 per 
year) are admitted free. Our phone number is (408) 732-9869 for a 
recorded message about upcoming meetings; recordings are available for 
those who can't attend - please inquire.

Since the PPC was formed in late 1989 many people have sampled it, 
found it to be very valuable, and even understand what we're up to. 
Nonetheless, certain questions persist. Now, in our seventh year of 
operation, perhaps we can and should clarify some of the issues. For 
example:


Q.  What is PPC's raison d'etre?

A.  The PARALLEL Processing Connection is an entrepreneurial 
organization intent on facilitating the emergence of new businesses. PPC 
does not become an active member of any such new entities, ie: is not 
itself a profit center.



Q.  The issue of 'why' is perhaps the most perplexing. After all, a $65 
annual membership fee is essentially free and how can anything be free in 
1997? What's the payoff? For whom?

A.  That's actually the easiest question of all. Those of us who are active 
members hope to be a part of new companies that get spun off; the payoff 
is for all of us -- this is an easy win-win! Since nothing else exists to 
facilitate hands-on entrepreneurship, we decided to put it together 
ourselves.



Q.  How can PPC assist its members?

A.  PPC is a large technically credible organization. We have close to 100 
paid members and a large group of less regular visitors; we mail to 
approximately 400 engineers and scientists (primarily in Silicon Valley). 
Major companies need to maintain visibility in the community and 
connection with it; that makes us an important conduit. PPC's strategy is to 
trade on that value by collaborating with important companies for the 
benefit of its members. Thus, as an organization, we have been able to 
obtain donated hardware, software, and training and we've put together a 
small development lab for hands-on use of members at our Sunnyvale 
office. Further, we've been able to negotiate discounts on seminars and 
hardware/software purchases by members. Most important, alliances such 
as we described give us an inside opportunity to JOINT VENTURE 
SITUATIONS.



Q.  As an attendee, what should I do to enhance my opportunities?

A.  Participate, participate, participate. Many important industry principals 
and capital people are in our audience looking for the 'movers'!

For further information contact:

-- 
B. Mitchell Loebel
Executive Director
The PARALLEL Processing Connection
408 732-9869 (USA)
Article: 7383
Subject: user access to BSCAN
From: Andreas Doering <doering@iti.mu-luebeck.de>
Date: Fri, 05 Sep 1997 07:56:26 +0200
Links: << >>  << T >>  << A >>
Hi,
a lot of modern FPGA architectures have boundary scan build in,
e.g. ALTERA FLEX and MAX9K, XILINX XC9K, XC 4K and so on.
Sure, this is for testing the PCBs after manufacturing but can 
be used for design debugging too.
In the debugging process it would be desirable to make 
explicitly coded scan paths available via the normal
BSCAN interface. This would not be expensive at all, 
it is just an additional register select and  two 
programmable connections.
The only problem is, that if the design of the "custom
scan path" is done wrong, the scan path chain may be broken.

May be, some of the devices have already such an 
access point, I only now ALTERA, and they seem to have not.
Andreas
-- 
---------------------------------------------------------------
                        Andreas Doering
                        Medizinische Universitaet zu Luebeck
                        Institut fuer Technische Informatik
		        Email: doering@iti.mu-luebeck.de
----------------------------------------------------------------
Article: 7384
Subject: Re: A fpga DMA design ?
From: z80@ds.com (Peter)
Date: Fri, 05 Sep 1997 07:48:21 GMT
Links: << >>  << T >>  << A >>
This sort of thing is very simple.

Start with a binary counter, running at say 4x your transfer rate. So,
for each byte (word?) transferred, the Q0,Q1 outputs of the counter
produce the following combinations

 00
 01
 10
 11

and you can decode these to produce the read signals for the source
device, and the write signals for the destination device.

The higher order counter outputs are the address.

It gets slightly more complex if you need separate address ranges for
the source and destination, but that is just two loadable counters,
clocked from Q2 of the above counter.

The data does not pass through the DMA. When the source device places
the data on the data bus, you issue a write pulse to write the same
data to the destination device. This is called "fly-by" DMA.

Wait states are also easy to do. You sample the /wait input only at
the byte transfer boundary, and if you find it TRUE you stop clocking
the counter.

I recently did a DMA controller which did 1M transfers/second at 4MHz
clock.

>I am looking at using a fpga do do a simple DMA controller,
>is there any designs out there that would help me to get a start.
>
>it is for a 32bit 68000 micro working on a 16bit bus between an 8 bit
>port and 16bit ram so I only need one counter and start & stop
>registers and the 8 bit port pointer register
>
>any advice any could give would be helpfull


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 7385
Subject: fpga configuration over PCI
From: Martin Vorbach <Martin.Vorbach@SCRAP.de>
Date: Fri, 5 Sep 1997 10:01:40 +0200
Links: << >>  << T >>  << A >>

> In article <5u7v21$5d8@neptune.myri.com>,
> Wen-King Su <wen-king@myri.com> wrote:
> >In a previous article jhallen@world.std.com (Joseph H Allen) writes:
> >:
> >;It would be really nice if PCI controller FPGAs could be configured
> over the
> >:PCI bus.  One way of doing it is to use configuration writes with
> the fpga
> >;data encoded in the address.
> 
> >Why not just do it through JTAG.
> 
> I don't know anything about JTAG or JTAG on the PC.  Is it board by
> board
> addressable?  I'll have to learn more about it.
> 
	[M.Vorbach]  Forget JTAG. What should I do with JTAG in my PC
(if I want to configure FPGAs using PCI)? 
	JTAG is a simply serial interface, which can address one or
multiple devices in a chain. However it is slow and I need (a small)
extra logic to generate JTAG signals.
	But I believe the idea of this discussion is to configure FPGAs
simply by a direct connect to PCI.
	 
	Probably there will be FPGAs in future days, which have a direct
PCI interface. Depending on their internal register-set (there have to
be registers for configuration 
	and for the configured FPGA functions!), which could be fixed
and not reconfigurable,  it seems to be possible to configure the
devices without any electrical problems (R,C, ...).

Article: 7386
Subject: Re: daisy-chained bitstreams
From: johna@dvorak.amd.com (John Archambeault)
Date: 5 Sep 1997 16:59:51 GMT
Links: << >>  << T >>  << A >>


	Oh yeah.  If forgot.  If you are TRULY masochistic, you could convert
the bitstream to a text representation of the binary.  (so it looks on a
normal text viewer as 001110011100, etc).  Then manually append the bitstream
for each fpga, removing the header for each and modifying the header for the
first to include to total number of bits (of the total bitstream) and then
either covert the "text 0110011" to real binary or just leave it in the "text
0110011" and download it.
	With patience you could get a small script (program) to do it, but (for
us at least) it was much simpler to do what I said before.  (copied below)

	Enjoy,
	John
	

I had the same problem only with 3100A.  The way around it is a bit convaluted,
but it does work.  Use the prom makeing tool to set it up as if a monster PROM
was going to perform a serial download.  Then, juse feed that PROM file into
the XCHECKER (name?) PC download cable.  It will accept PROM files.

Good Luck,
John

BTW:  I documented this a while back, but am going from memory right now.  If
you still can't get it, e-mail and I'll check the old documents.
--
John Archambeault
End of article 7946 (of 7957) -- what next? [npq]

-- 
John Archambeault
Article: 7387
Subject: FPGA-to-ASIC Conversion Advice Appreciated
From: bdipert@aol.com (BDipert)
Date: 5 Sep 1997 17:31:37 GMT
Links: << >>  << T >>  << A >>
I'm interested in hearing from any of you who have considered or even
'taken the plunge' and completed a FPGA-to-ASIC design conversion. Did it
go as you expected it would, was it easier or more difficult? What company
or companies did you work with? Did the expected cost savings materialize,
and if not, why not? Thanks in advance for sharing your experiences
Article: 7388
Subject: VSI Specs Posted for Review
From: sbaker@best.com (Stan Baker)
Date: Fri, 05 Sep 1997 20:21:37 GMT
Links: << >>  << T >>  << A >>
The VSI Alliance has posted two specifications for review by its
membership.

Comment on "Structural Netlist and Hard VC Physical Data Types" is due
by Oct. 2, 1997.

Comment on "Analog Mixed-Signal VSI Extension" is due by Sept. 29,
1997.

If your company is a VSIA member you can download these documents from
http://www.vsi.org/membersonly/library/specrev.htm

If you don't know your company password, ask nancy@vsi.org.

If you are not a VSIA member and you work with system-level chip
development, you should join.  Membership information is available at
http://www.vsi.org.  The VSIA is dedicated to developing
specifications for interfacing virtual components on system-level
chips - mix and match, plug and play.

The Alliance is also holding its Fall Worldwide Member Meeting in
which all of  its work will be explained and discussed.  Non-members
are invited.  Info at http://www.vsi.org/events/100397.htm.


best regards,
Stan Baker
Executive Director,
VSI Alliance







Article: 7389
Subject: Binary to Intel Hex
From: Gareth Baron <gbaron@eng.efi.com>
Date: Fri, 05 Sep 1997 18:15:44 -0700
Links: << >>  << T >>  << A >>
Hi guys and gals.

Sorry It's been along time since I accessed newsgroups but I've moved. 
Not just around the corner but to a new country.  The US of A!

Anyway I was wondering if any of you kind people might help.

I'm after a file converter or source which will convert a raw binary
file into Intel Hex format.  I have a IHEX deconstructor but not a
constructor.

Please Email me with any info. or source code.

Many thanks.

Gareth Baron.
Direct Tel: 415 286 7943

Electronics For Imaging. 2855 Campus Drive, San Mateo, CA 94403
Tel: 415 286 8600         Fax: 415286 8545
Article: 7390
Subject: Re: export pins from MAX+ to orcad schem symbol
From: Gareth Baron <gbaron@eng.efi.com>
Date: Fri, 05 Sep 1997 18:19:30 -0700
Links: << >>  << T >>  << A >>
bob elkind wrote:
> 
> Anyone have a clue, what is the simplest and most reliable
> means for exporting post-compile pinouts from Altera's
> MAX+II to OrCad or Protel, for generating a schematic symbol
> for board design?
> 
> There must be a simple solution, since this is otherwise a
> horribly tedious, error-prone, and repetitive task.
> 
> Thank you for your help!
> 
> -- Bob Elkind
> 
> ****************************************************************
> Bob Elkind                              mailto:eteam@aracnet.com
> 7118 SW Lee Road               part-time fax number:503.357.9001
> Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
> ****** Video processing, R&D, ASIC, FPGA design consulting *****

Can't you just tie your pins in your FPGA design (especially Altera). 
You won't have to re-route you PCB then.  Name your Schematic symbol
with generic pin names and not signal names.  This should stop you
having to change the symbol everytime.

Am I missing the point ?
-- 



Regards,

Gareth Baron.
Direct Tel: 415 286 7943

Electronics For Imaging. 2855 Campus Drive, San Mateo, CA 94403
Tel: 415 286 8600         Fax: 415286 8545
Article: 7391
Subject: arte
From: "JOSE MANUEL DIAZ RIVERA" <JMDIAZ@teleline.es>
Date: 6 Sep 1997 01:59:29 GMT
Links: << >>  << T >>  << A >>

-- 
RECIBE UN CORDIAL SALUDO
JMDIAZ@teleline.es
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end

Article: 7392
Subject: ANNOUNCE APS Low cost LUCENT FPGA Kits
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 05 Sep 1997 22:31:37 -0400
Links: << >>  << T >>  << A >>

APS will soon be releasing its Lucent development kits. These kits
will include ORCA Router / VHDL synthesis and VHDL Simulator
options at very good prices. All kits come the APS-L84 board which will
include programmbale DDS clock, SRAM socket and 2Cxx FPGA
The board will come with a There are several configurations. See:

http://www.associatedpro.com/aps/L84.html


--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7393
Subject: Re: export pins from MAX+ to orcad schem symbol
From: TMA <tmaconway@worldnet.att.net>
Date: Fri, 05 Sep 1997 21:38:22 -0500
Links: << >>  << T >>  << A >>
Gareth Baron wrote:
> 
> bob elkind wrote:
> >
> > Anyone have a clue, what is the simplest and most reliable
> > means for exporting post-compile pinouts from Altera's
> > MAX+II to OrCad or Protel, for generating a schematic symbol
> > for board design?
> >
> > There must be a simple solution, since this is otherwise a
> > horribly tedious, error-prone, and repetitive task.
> >
> > Thank you for your help!
> >
> > -- Bob Elkind
> >
> > ****************************************************************
> > Bob Elkind                              mailto:eteam@aracnet.com
> > 7118 SW Lee Road               part-time fax number:503.357.9001
> > Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
> > ****** Video processing, R&D, ASIC, FPGA design consulting *****
> 
> Can't you just tie your pins in your FPGA design (especially Altera).
> You won't have to re-route you PCB then.  Name your Schematic symbol
> with generic pin names and not signal names.  This should stop you
> having to change the symbol everytime.
> 
> Am I missing the point ?
> --
> 
> Regards,
> 
> Gareth Baron.
> Direct Tel: 415 286 7943
> 
> Electronics For Imaging. 2855 Campus Drive, San Mateo, CA 94403
> Tel: 415 286 8600         Fax: 415286 8545
But what about the first time through?  The point is that you go 
through the trouble of assigning and locking the pins in the MaxPlusII
software, now you have to go to the schematic capture and do a whole
other process.  
The other problem is making things look neat.  Let's say you have a
bus that is not on consecutive pins.  It's nice to tie the bus on
the schematic consecutively.  To do this you would have to create
a unique symbol for the part.  It is nice to have this automated.
I have worked with two home-grown versions of a utility that reads
a device pinout, and creates a unique symbol for it (Mentor and
Viewlogic).  Orcad Capture which is what I'm using now, is not that
flexible
(or expensive either).  Bob pointed out that he could use EDIF to 
get into Orcad Express.  Orcad Capture does not have EDIF *import*
capability (export yes).  
Any help there?
Thanks,
Tim Conway
Who does not speak for
Prima Facie, Inc.
Article: 7394
Subject: Announce APS-Synth-All Multi-Vendor kits
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 05 Sep 1997 22:44:48 -0400
Links: << >>  << T >>  << A >>
APS is shipping its Synth-All Multi-vendor VHDL/FPGA kits. The kits
come with VHDL synthesis, VHDL simulation with VITAL support,
FPGA board options, 100 Mhz POD logic Analyzer option, and router
options.

The synthesis covers:
Xilinx 3K, 4K, 4Ke, 4Kex, 5K, 7K, 9K XNF, EDIF
                   Altera All devices EDIF
                 Lucent ORCA EDIF
                AMD/Vantis MACH Devices DSL
              Actel ACT1, ACT2, ACT3, ACT-32 EDIF
              Quicklogic pASIC EDIF
              Lattice PLSI EDIF

All for one low price of 4200.00 !!!!!

Kit packages are available. One example:

XILINX  PAK

Synth-All  VHDL Simulation (all vendors)

plus:
  option1: VHDL Simulator
  option2: XILINX M1 router
  option 2a: APS-X84 FPGA development board
  option 4 Pod-A-Lyzer 100 Mhz Logic Analyzer pod

All for:....... $7500.00 !!!


details can be seen at:

http://www.associatedpro.com/aps/premium.html

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7395
Subject: Which FPGA ?
From: Bulent UNALMIS <unalmis@club-internet.fr>
Date: Fri, 05 Sep 1997 21:31:48 -0700
Links: << >>  << T >>  << A >>
Hello,

Help please for choising FPGA.

I am new for fpga, I am using (know) only lattice isplsi 2032. This IC
has has 44 pin and 32 registers.

I used three 2032 at my project but i want to use only one fpga. (96
register) 
[Becouse I want simplified printed circuit board.]


I am looking  48 or 64 pin FPGA, but this fpga must be have MINUMUM 96
register.

For example : Lattice ispLSI2096 has 96 Flipflop,  but has 128 pin. !!!

Therfore,  I dont like from this IC.

Do you know any  FPGA for this purpose ? (From any company)

Best Reagrds.
Article: 7396
Subject: Re: export pins from MAX+ to orcad schem symbol
From: jhallen@world.std.com (Joseph H Allen)
Date: Sat, 6 Sep 1997 07:34:34 GMT
Links: << >>  << T >>  << A >>

Here's a small turbo-C program for inserting pin numbers from Xilinx XACT
report files into OrCAD library source files (I'm sure many people have
written variations of this).  I don't know about MAX+ or Windows versions of
OrCAD, but this program might work- especially if MAX+ makes some text file
with the pin name and numbers, one per line (just about any punctuation will
work).  You can make a little DOS shell script to decompile the library, run
this program and compile it again.

/* Stuff pin assignments from XACT report file into OrCAD lib source file */

#include <stdio.h>
#include <string.h>

extern void *malloc();
extern void *realloc();

struct pin
 {
 char *name;
 char *num;
 } *pins;	/* List of pins */

int npins;	/* No. pins on part */
int pinssiz;	/* Malloc size of pins */

/* Compare first strlen(b) chars of a */

int cmp(a,b)
char *a, *b;
 {
 while(*b && *a==*b) ++a, ++b;
 if(!*b) return 0;
 else return 1;
 }

main(argc,argv)
char *argv[];
 {
 FILE *f, *g;
 char buf[1024];
 char bf[128];
 int x, y, z, q;
 if(argc!=4)
  {
  fprintf(stderr,"pins decompiled-library-name part-name report-file-name\n");
  return 1;
  }
 /* Pass 1 through library: find part and collect pin names */
 /* Part begins with 'part-name' at beginning of line */
 sprintf(bf,"\'%s\'",argv[2]);
 /* Allocate space for pins */
 pins=malloc((pinssiz=64)*sizeof(struct pin));
 /* Open library */
 if(!(f=fopen(argv[1],"r")))
  {
  fprintf(stderr,"Couldn't open %s\n",argv[1]);
  return 1;
  }
 /* Scan library */
 while(fgets(buf,1023,f))
  if(!cmp(buf,bf))
   break;
 if(cmp(buf,bf))
  {
  fprintf(stderr,"Part %s not found\n",argv[2]);
  return 1;
  }
 /* Skip header line */
 fgets(buf,1023,f);
 /* Collect pin names */
 while(fgets(buf,1023,f) && strlen(buf)>23)
  {
  for(x=23;buf[x] && buf[x]!='\'';++x);
  buf[x]=0;
  if(npins==pinssiz) pins=realloc(pins,(pinssiz*=2)*sizeof(struct pin));
  pins[npins].name=strcpy(malloc(strlen(buf+23)+1),buf+23);
  pins[npins].num=0;
  ++npins;
  }
 fclose(f);

 /* Scan report file */
 f=fopen(argv[3],"r");
 if(!f)
  {
  fprintf(stderr,"Couldn't open report file\n");
  return 1;
  }
 /* Find lines with a number and a pin name on them */
 while(fgets(buf,1023,f))
  {
  for(x=0;buf[x];++x)
   if(buf[x]>='0' && buf[x]<='9')
    { /* Check if one of our pins was mentioned in this line... */
    for(q=x;buf[q]>='0' && buf[q]<='9';++q);
    if(buf[q]!=0 && buf[q]!=' ' && buf[q]!='\t' && buf[q]!=':' &&
       buf[q]!=',' && buf[q]!='|' && buf[q]!=';')
     {
     x=q;
     goto next;
     }
    for(y=0;buf[y];++y)
     for(z=0;z!=npins;++z)
      /* Search for name seperated with non-identifier character on
         the left and whitespace on the right */
      if((!y || !(buf[y-1]>='a' && buf[y-1]<='z' ||
                  buf[y-1]>='A' && buf[y-1]<='Z' ||
                  buf[y-1]>='0' && buf[y-1]<='9' ||
                  buf[y-1]=='_' || buf[y-1]=='$')) &&
         !cmp(buf+y,pins[z].name) &&
         (buf[y+strlen(pins[z].name)]==' ' ||
          buf[y+strlen(pins[z].name)]=='\t' ||
          buf[y+strlen(pins[z].name)]=='|' ||
          buf[y+strlen(pins[z].name)]==';' ||
          buf[y+strlen(pins[z].name)]==',' ||
          buf[y+strlen(pins[z].name)]==':' ||
          buf[y+strlen(pins[z].name)]==0))
       { /* Pin name was found! */
       /* Skip if we already found pin number */
       if(pins[z].num) goto done;
       /* Make sure number we found is not in pin name */
       if(q>=y && q<=y+strlen(pins[z].name))
        {
        x=q;
        goto next;
        }
       /* Store pin number */
       buf[q]=0;
       pins[z].num=strcpy(malloc(strlen(buf+x)+1),buf+x);
       goto done;
       }
    next:;
    }
  done:;
  }
 /* Print pin assignments */
 for(x=0;x!=npins;++x)
  {
  printf("%15s %3s",pins[x].name,pins[x].num?pins[x].num:"---");
  if((x&3)==3) printf("\n");
  else printf(" ");
  }
 if(x&3) printf("\n");
 /* Pass 2 through library - copy it to tmp.tmp as we scan */
 if(!(f=fopen(argv[1],"r")))
  {
  fprintf(stderr,"Couldn't open %s\n",argv[1]);
  return 1;
  }
 if(!(g=fopen("tmp.tmp","w")))
  {
  fprintf(stderr,"Couldn't open tmp.tmp\n");
  return 1;
  }
 /* Find part in library */
 while(fgets(buf,1023,f))
  {
  fputs(buf,g);
  if(!cmp(buf,bf)) break;
  }
 if(cmp(buf,bf))
  {
  fprintf(stderr,"Part not found on second pass... huh?\n");
  return 1;
  }
 fgets(buf,1023,f);
 fputs(buf,g);
 /* Overlay pin numbers */
 while(fgets(buf,1023,f))
  if(strlen(buf)>23)
   {
   for(y=0;y!=npins;++y)
    if(!cmp(buf+23,pins[y].name))
     {
     char ff[10];
     sprintf(ff,"%3s",pins[y].num);
     if(pins[y].num)
      {
      buf[6]=ff[0];
      buf[7]=ff[1];
      buf[8]=ff[2];
      }
     break;
     }
   fputs(buf,g);
   }
  else
   {
   fputs(buf,g);
   break;
   }
 /* Copy rest of file */
 while(fgets(buf,1023,f)) fputs(buf,g);
 if(ferror(f) || fclose(f))
  {
  fprintf(stderr,"Error reading file\n");
  return 1;
  }
 if(ferror(g) || fclose(g))
  {
  fprintf(stderr,"Error writing file\n");
  return 1;
  }
 /* Now copy temporary file into library */
 if(!(f=fopen("tmp.tmp","r")))
  {
  fprintf(stderr,"Couldn't open tmp.tmp\n");
  return 1;
  }
 if(!(g=fopen(argv[1],"w")))
  {
  fprintf(stderr,"Couldn't open %s\n",argv[1]);
  return 1;
  }
 while(fgets(buf,1023,f)) fputs(buf,g);
 fclose(f); fclose(g);
 unlink("tmp.tmp");
 fprintf(stderr,"Pin assignments complete\n");
 return 0;
 }

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7397
Subject: FREE PICS THROUGH E-MAIL
From: Funstore<Funstore@sod.nl>
Date: 6 Sep 1997 13:41:50 GMT
Links: << >>  << T >>  << A >>

It is free, it is amazing.
Visit http://www.funstore.nl and
put yourself on our xxx-pics mailinglist
You will receive free pictures. You tell
us what you want and we send them to you.
It is new and it is HOT and its FREE
http://www.funstore.nl
http://www.funstore.nl

Article: 7398
Subject: Hard-soft development for reconfig computing?
From: Joachim Strömbergson <watchman@ludd.luth.se>
Date: Sat, 06 Sep 1997 11:50:20 -0700
Links: << >>  << T >>  << A >>

Hi!

While working on my master´s thesis, which touches on Reconfig
computing, I got into a discussion about application development for
fully reconfigurable hardware. As I see it, software development and
hardware development will have to merge, though not really in the
co-development sence, but rather like a symbiosis: Tne difference
between the software tranformation and the hardware synthesis gets
blurred.

I can imagine having a dev-system that allows me to write code and
contains a database of selectable hardware features. The system then
assembles the hardware, generates appropriate code and compiles control
so that the HW-features will linked in execution time to the software.
This would not be very different from todays tools, just merged
together. But what would an automatic system look like, a system that
makes away with the difference between HW and SW? A system that instead
generates the appropriate combination automatically based on an (say)
object-oriented description of the problem.

(After this lengthy chat) I'm wondering if I'm totally lost, or are
there any developments/reseach being done in this direction? What's your
view on this?

Looking forward to any comments/information and discussion.
-- 
Cheers!
Joachim - Alltid i harmonisk svängning
---------------------------------------------------------
Joachim Strömbergson  MSCE student, nice to CUTE animals.
c/o Flodén            PC   e-mail : watchman@ludd.luth.se
Emilsborg 1030
412 79 Göteborg      C64      phone: +46(0)31 - 166 419
Sweden           -FairLight-  alt:   +46(0)70 - 694 78 53
---------------------------------------------------------
Article: 7399
Subject: Re: Which FPGA ?
From: jhallen@world.std.com (Joseph H Allen)
Date: Sat, 6 Sep 1997 20:38:33 GMT
Links: << >>  << T >>  << A >>

In article <3410DCB4.4E6C@club-internet.fr>,
Bulent UNALMIS  <unalmis@club-internet.fr> wrote:
>Hello,
>
>Help please for choising FPGA.
>
>I am new for fpga, I am using (know) only lattice isplsi 2032. This IC
>has has 44 pin and 32 registers.
>
>I used three 2032 at my project but i want to use only one fpga. (96
>register) 
>[Becouse I want simplified printed circuit board.]
>
>
>I am looking  48 or 64 pin FPGA, but this fpga must be have MINUMUM 96
>register.
>
>For example : Lattice ispLSI2096 has 96 Flipflop,  but has 128 pin. !!!
>
>Therfore,  I dont like from this IC.
>
>Do you know any  FPGA for this purpose ? (From any company)


Xilinx has the 3030pc44 - a 44 pin PLCC FPGA with 100 logic blocks, 200
internal flip-flops and about 68 I/O (pad) flip-flops.  I costs about $20 in
single quantities, but the development system costs about $1000.  This is
not a PAL-like FPGA, instead it is made of logic blocks which take up to 5
inputs: more inputs require logic blocks to be placed in series with a
corresponding increase in delay.  Routing resources are limited (it's not
fully connected), so if the chip is nearly full, you may have to run the
compiler over and over again until you find a design which routes.  Data
buses are more doable in this type of FPGA.  Binary counters use up lots of
space, so non-binary counters are often used (linear feedback shift-register
counters use only a single xor gate, but they count in a random sequence). 
Also you have more than 1 global clock line (actually each flip-flop can be
separately clocked from logic or other I/O pins- binary ripple counters and
other non-synchronous designs are possible).  You can get versions of this
chip where the internal flip flops run over 300MHz, but an entire design
works usually between 20 and 90MHz depending on how deep the logic is
between flip-flops.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}


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