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Messages from 7450

Article: 7450
Subject: RFP: Reconfigurable Tool
From: Danny Kumamoto <kumamoto@austin.apc.slb.com>
Date: Thu, 11 Sep 1997 11:36:06 -0500
Links: << >>  << T >>  << A >>

DARPA has just announced (yesterday) a request for a reconfigurable
computing tool:


        http://www.darpa.mil/baa/BAA97-46


Anyone here going to apply for it?  I don't think my employer would
allow us to bid for it, but we would be interested in working together
on such a project, since we are interested in such a tool as well.


Thank you for any leads and info,
----
Danny


kumamoto1@slb.com    TEL: +1 512-331-3727   FAX: +1 512-331-3760
End-to-End Simulation, Schlumberger Austin Product Center-Research
8311 North RR 620, P.O. Box 200015, Austin, TX 78726, U.S.A.




Article: 7451
Subject: SYNC RAM in XCilinx/Altera...
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Thu, 11 Sep 1997 13:47:10 -0700
Links: << >>  << T >>  << A >>

I have data on XC4000, and Flex 10K, showing the RAM features.


Of these, the Xilinx looks straight forward, as effectively an
array of D Flip Flips - this is what we need. 


The Flex has Async, and Sync modes, but it is NOT clear if it can run
in the same manner as the Xilinx. ( ie the SYNC mode has registers
on both sides of the RAM, introducing a CLK delay to Load Address.Data
one to WRITE and one to LOAD the output regsiter...


Q:
 Has anyone used FLEX Sync RAM, in the same manner as Xilinx ?
 Can the Flex 256 x 8 Block be configured for ASYNC Adr,Data IN, 
 SYNC ( Clocked ) Write, and ASYNC data out ?
 ( ie, our Array of D/FF's ) ?


Thanks.. Jim. G


Article: 7452
Subject: Cheap (sub $10) hardwired FPGA? Which manufacturers?
From: "Bjoern Wesen" <bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME>
Date: 11 Sep 1997 22:08:17 GMT
Links: << >>  << T >>  << A >>

I'm looking at the possibilities for implementing medium sized (4-800
flipflops, 10-16000 gates, maybe some SRAM) non-speedcritical FPGA designs
in cheap (preferably below $10 in volumes) factory programmed FPGA's. It is
useful to do this with FPGA's instead of conventional gate arrays or asic's
because the final chip would be identical to the prototype (which could use
the more expensive SRAM/FLASH based FPGA version). 


I know that Xilinx XC4000 and XC5200 exist in so called "HardWire" versions
called XC4400 and XC5400, but the price of the 4000 series is way way too
much and the 5200 series lacks SRAM. I don't know the actual price for the
4400 and 5400 series though, perhaps it is cheap. Supposedly Altera and
Actel have hardwired versions as well but both Xilinx, Altera and Actel's
web-pages are so badly designed that you need to spend 30 minutes looking
for their "Products" link so I haven't found any info there. 


Lucent has their mask programmed ORCA series, MACO, but I haven't found any
press releases suggesting a price for them. 


Any comments or suggestions?


Regards,
Bjorn Wesen
 

-------
Please mail me at bjorn@sparta.lu.se and dont use the reply-to adress
since I've scrambled it to avoid junk mails. 
Article: 7453
Subject: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
From: Jason.Wright@ebu.ericsson.com (Jason T. Wright)
Date: Thu, 11 Sep 1997 22:20:38 GMT
Links: << >>  << T >>  << A >>

On 11 Sep 1997 22:08:17 GMT, "Bjoern Wesen"
<bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote:


>I'm looking at the possibilities for implementing medium sized (4-800
>flipflops, 10-16000 gates, maybe some SRAM) non-speedcritical FPGA designs
>in cheap (preferably below $10 in volumes) factory programmed FPGA's. It is
>useful to do this with FPGA's instead of conventional gate arrays or asic's
>because the final chip would be identical to the prototype (which could use
>the more expensive SRAM/FLASH based FPGA version). 
>
>I know that Xilinx XC4000 and XC5200 exist in so called "HardWire" versions
>called XC4400 and XC5400, but the price of the 4000 series is way way too
>much and the 5200 series lacks SRAM. I don't know the actual price for the
>4400 and 5400 series though, perhaps it is cheap.


We are looking at the possibility of using hard-wire; your main cost
issues will be volume (10k? 100k? 1M?) and package (208QFP, 240QFP,
..)  The smaller [standard] packages and the larger  volume orders
can easily bring unit recurring costs below $10.  Check with your
Xilinx rep (& Altera, Actel, Lucent, etc.) to get specifics.


> Supposedly Altera and
>Actel have hardwired versions as well but both Xilinx, Altera and Actel's
>web-pages are so badly designed that you need to spend 30 minutes looking
>for their "Products" link so I haven't found any info there. 
>
>Lucent has their mask programmed ORCA series, MACO, but I haven't found any
>press releases suggesting a price for them. 
>
>Any comments or suggestions?
>
>Regards,
>Bjorn Wesen
> 
>-------
>Please mail me at bjorn@sparta.lu.se and dont use the reply-to adress
>since I've scrambled it to avoid junk mails. 


Article: 7454
Subject: Re: Text Book and VHDL Simulator $50.00
From: "JOHN MCGIBBON" <fpga@worldnet.att.net>
Date: 12 Sep 1997 00:00:54 GMT
Links: << >>  << T >>  << A >>







Richard Schwarz <aaps@erols.com> wrote in article
<3416CF8A.ACFA9D27@erols.com>...
> For those looking for a solid VHDL Text Book and a useable VHDL
> Simulator,
> APS is now selling the Prentice Hall text by Pellerin and Taylor, along
> with a limited
> version of PeakVHDL simulator (perfect for learning) for $49.99. Some
> details on the
> text are shown below see the full details at:


http://www.bookpool.com   has the same book and CD for $36.95
Article: 7455
Subject: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
From: "Richard B. Katz" <stellere_nospam@erols.com>
Date: 12 Sep 1997 00:34:05 GMT
Links: << >>  << T >>  << A >>



hi


i've looked into the actel stuff and they do have a hardwired product and
it is described with a spec and app note in their databook.  instead of the
www, you may wish to call them and speak to a human.


another approach is to use a process such as chip expresses.  you can
convert your fpga to their format and do 'laser programmed' prototypes. 
for higher volumes, you can go to a cheap "one-mask" process and for higher
volumes a more traditional route.  in my other life (not home 'puter) we're
going from lpga prototypes (all first past successes) to one mask with no
additional engineering.  the performance between lpga and one mask are the
same as they use the same wafers and cut the metal in the same spot.  nre
is moderate.  and they have models w/ sram, their cx2001 series.  and for
certain volumes, they'll throw in some design iterations.  an interesting
niche sharing some design principles with fpga's and other's with asics.


just another idea,


rk


"there's nothing like real data to screw up a great theory" - hey, i said
that!


-----------------------------


Bjoern Wesen <bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote in article
<01bcbeff$b95dee50$f3f12fc2@zeus>...
> 
> I'm looking at the possibilities for implementing medium sized (4-800
> flipflops, 10-16000 gates, maybe some SRAM) non-speedcritical FPGA
designs
> in cheap (preferably below $10 in volumes) factory programmed FPGA's. It
is
> useful to do this with FPGA's instead of conventional gate arrays or
asic's
> because the final chip would be identical to the prototype (which could
use
> the more expensive SRAM/FLASH based FPGA version). 
> 
> I know that Xilinx XC4000 and XC5200 exist in so called "HardWire"
versions
> called XC4400 and XC5400, but the price of the 4000 series is way way too
> much and the 5200 series lacks SRAM. I don't know the actual price for
the
> 4400 and 5400 series though, perhaps it is cheap. Supposedly Altera and
> Actel have hardwired versions as well but both Xilinx, Altera and Actel's
> web-pages are so badly designed that you need to spend 30 minutes looking
> for their "Products" link so I haven't found any info there. 
> 
> Lucent has their mask programmed ORCA series, MACO, but I haven't found
any
> press releases suggesting a price for them. 
> 
> Any comments or suggestions?
> 
> Regards,
> Bjorn Wesen
>  
> -------
> Please mail me at bjorn@sparta.lu.se and dont use the reply-to adress
> since I've scrambled it to avoid junk mails. 
> 
Article: 7456
Subject: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
From: "Steven K. Knapp" <sknapp @ optimagic.com>
Date: 12 Sep 1997 05:19:48 GMT
Links: << >>  << T >>  << A >>

Bjoern Wesen <bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote in article
<01bcbeff$b95dee50$f3f12fc2@zeus>...
..
.. [snip]
..
| web-pages are so badly designed that you need to spend 30 minutes looking
| for their "Products" link so I haven't found any info there. 
| 


I had the Xilinx page bookmarked.  It's
'http://www.xilinx.com/products/hardwire/hardwire.htm'.  Pricing depends a
lot on your package and volume requirements.  I would highly recommend
contacting your local Xilinx sales office which, if I'm guessing correctly
by your reply address would be at:


'http://www.xilinx.com/company/sales/int_reps.htm#SWEDEN'




-- 
Steven Knapp
OptiMagic, Inc.
E-mail:  sknapp @ optimagic.com
Programmable Logic Jump Station:  http://www.optimagic.com
Article: 7457
Subject: Re: Text Book and VHDL Simulator $50.00
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 12 Sep 1997 08:15:14 -0400
Links: << >>  << T >>  << A >>



JOHN MCGIBBON wrote:


> Richard Schwarz <aaps@erols.com> wrote in article
> <3416CF8A.ACFA9D27@erols.com>...
> > For those looking for a solid VHDL Text Book and a useable VHDL
> > Simulator,
> > APS is now selling the Prentice Hall text by Pellerin and Taylor,
> along
> > with a limited
> > version of PeakVHDL simulator (perfect for learning) for $49.99.
> Some
> > details on the
> > text are shown below see the full details at:
>
> http://www.bookpool.com   has the same book and CD for $36.95


Wow that's a good price. However we offer an additional CD with the
latest Simulatoron it (so you get two CDs, the one in the book and the
latest) plus we offer limited email support since we are the auth.
distributors of the PeakVHDL simulator. It is much more advantageous to
purchase the Book and CD(s) through us.




--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760


__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




Article: 7458
Subject: pellerin@seanet.com
From: Richard Schwarz <aaps@erols.com>
Date: Fri, 12 Sep 1997 16:19:12 -0400
Links: << >>  << T >>  << A >>

Hey Dave,


Did you know that BookPool is selling your book and disk fort $36.00?


Is it any different than what you or I are selling?


--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: aaps@erols.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760


__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




Article: 7459
Subject: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
From: spp@bob.eecs.berkeley.edu
Date: 13 Sep 1997 01:35:42 GMT
Links: << >>  << T >>  << A >>



Not sure what your rationale is for not wanting to go to a
gate-array version.   In the past at least, Orbit Semiconductor
would translate your Xilinx design to gate array and put it
in any package you like.  Their volume pricing would meet your
requirements.  Just ask them for a quote.


The hardwired products from Xilinx/Altera/Actel are an
attempt to hang on to some of that market, but it is
hard to believe they can under-price a gate array version,
except maybe for quantities under a thousand or so.


Steve
Article: 7460
Subject: Re: SYNC RAM in XCilinx/Altera...
From: spp@bob.eecs.berkeley.edu
Date: 13 Sep 1997 03:51:28 GMT
Links: << >>  << T >>  << A >>

jim granville  <DesignTools@xtra.co.nz> wrote:


>The Flex has Async, and Sync modes, but it is NOT clear if it can run
>in the same manner as the Xilinx. ( ie the SYNC mode has registers
>on both sides of the RAM, introducing a CLK delay to Load Address.Data
>one to WRITE and one to LOAD the output regsiter...
>
>Q:
> Has anyone used FLEX Sync RAM, in the same manner as Xilinx ?
> Can the Flex 256 x 8 Block be configured for ASYNC Adr,Data IN, 
> SYNC ( Clocked ) Write, and ASYNC data out ?


There are four answers to your question.


(1) Yes, the part can be programmed to have registers on the
DIN, the Address lines, and the Write control, but not on the DOUT.


(2) Yes, the Altera "genmem" program will generate a simulateable
module for the RAM.


(3) Yes, MaxPlus2 will infer the RAM thus configured.


(4) No, the Altera databook does not define the timing of the 
RAM in this mode.


Good luck --


Steve
Article: 7461
Subject: Q: Lattice Synario and ISPLSI1048
From: Bulent UNALMIS <unalmis@club-internet.fr>
Date: Sat, 13 Sep 1997 02:39:56 -0700
Links: << >>  << T >>  << A >>

Hello,


I have " Lattice  Synario System ".
Can I extend this system for ISPLSI1048 FPGA. ?
Did you know any way ? (I search economic solve)


Thanks
Article: 7462
Subject: DES implementation
From: Erika Van Baelen <erika.vbaelen@club.innet.be>
Date: Sat, 13 Sep 1997 19:37:09 +0200
Links: << >>  << T >>  << A >>

Hi,


I'm searching for a hardware implementation of the
DES-algorithm, for instance the VHDL code.


If anyone could help me, please mail to:
erika.vbaelen@club.innet.be


Thanks!
Article: 7463
Subject: Re: Text Book and VHDL Simulator $50.00
From: "Richard B. Katz" <stellere_nospam@erols.com>
Date: 13 Sep 1997 19:35:53 GMT
Links: << >>  << T >>  << A >>

ok, we have book + 1 cd
and now we have book + 2 cd's
anybody got book + 3 cd's?
 

----------------------------------------------------------------------------
------------------
rk


"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
----------------------------------------------------------------------------
------------------


Richard Schwarz <aaps@erols.com> wrote in article
<34193252.3CCE1914@erols.com>...
> JOHN MCGIBBON wrote:
> 
> > Richard Schwarz <aaps@erols.com> wrote in article
> > <3416CF8A.ACFA9D27@erols.com>...
> > > For those looking for a solid VHDL Text Book and a useable VHDL
> > > Simulator,
> > > APS is now selling the Prentice Hall text by Pellerin and Taylor,
> > along
> > > with a limited
> > > version of PeakVHDL simulator (perfect for learning) for $49.99.
> > Some
> > > details on the
> > > text are shown below see the full details at:
> >
> > http://www.bookpool.com   has the same book and CD for $36.95
> 
> Wow that's a good price. However we offer an additional CD with the
> latest Simulatoron it (so you get two CDs, the one in the book and the
> latest) plus we offer limited email support since we are the auth.
> distributors of the PeakVHDL simulator. It is much more advantageous to
> purchase the Book and CD(s) through us.
> 
> 
> --
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> 
> Richard Schwarz, President              EDA & Engineering Tools
> Associated Professional Systems (APS)   http://www.associatedpro.com
> 3003 Latrobe Court                      richard@associatedpro.com
> Abingdon, Maryland 21009
> Phone: 410.569.5897                     Fax:410.661.2760
> 
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> 
> 
> 
Article: 7464
Subject: Re: Text Book and VHDL Simulator $50.00
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 13 Sep 1997 16:05:25 -0400
Links: << >>  << T >>  << A >>



Richard B. Katz wrote:


> ok, we have book + 1 cd
> and now we have book + 2 cd's
> anybody got book + 3 cd's?
>
> --------------------------
> -------------------------------------------------
> ------------------
> rk
>
> "there's nothing like real data to screw up a great theory"
> - me (modified from original, slightly more colorful version)
> -------------------------------------------------------------
> --------------
> ------------------
>
> Richard Schwarz <aaps@erols.com> wrote in article
> <34193252.3CCE1914@erols.com>...
> > JOHN MCGIBBON wrote:
> >
> > > Richard Schwarz <aaps@erols.com> wrote in article
> > > <3416CF8A.ACFA9D27@erols.com>...
> > > > For those looking for a solid VHDL Text Book and a useable VHDL
> > > > Simulator,
> > > > APS is now selling the Prentice Hall text by Pellerin and
> Taylor,
> > > along
> > > > with a limited
> > > > version of PeakVHDL simulator (perfect for learning) for $49.99.
>
> > > Some
> > > > details on the
> > > > text are shown below see the full details at:
> > >
> > > http://www.bookpool.com   has the same book and CD for $36.95
> >
> > Wow that's a good price. However we offer an additional CD with the
> > latest Simulatoron it (so you get two CDs, the one in the book and
> the
> > latest) plus we offer limited email support since we are the auth.
> > distributors of the PeakVHDL simulator. It is much more advantageous
> to
> > purchase the Book and CD(s) through us.
> >
> >
> > --
> > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> __/
> >
> > Richard Schwarz, President              EDA & Engineering Tools
> > Associated Professional Systems (APS)   http://www.associatedpro.com
>
> > 3003 Latrobe Court                      richard@associatedpro.com
> > Abingdon, Maryland 21009
> > Phone: 410.569.5897                     Fax:410.661.2760
> >
> > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> __/
> >
> >
> >


 Yes,


We'll through in Slim Whitman's favorite hits, and a set of Ginsu
knives. They slice they dice, they're made in America, and they make
Julie Ann fries!


But seriously, the second CD is just an updated one which always came
with the book when you buy it from us. This is not a change, I just
wanted to point out the advantage of buying it through us. Wherever you
get it, the book and usable Simulator for under $50.00 is a great
bargain and should help new users to get up to speed very quickly and at
a reasonable price. Plus if you have questions and have purchased the
book from us we will do limited support via email. You can't go wrong
with all that for under 50 bucks.


--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760


__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




Article: 7465
Subject: WANT A FREE PAGER? LOOK HERE!
From: info@pgrs.com
Date: 13 Sep 97 22:35:44 GMT
Links: << >>  << T >>  << A >>

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Article: 7466
Subject: Re: Cheap (sub $10) hardwired FPGA? Which manufacturers?
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Sun, 14 Sep 1997 10:34:48 GMT
Links: << >>  << T >>  << A >>

On 13 Sep 1997 01:35:42 GMT, spp@bob.eecs.berkeley.edu wrote:


>The hardwired products from Xilinx/Altera/Actel are an
>attempt to hang on to some of that market, but it is
>hard to believe they can under-price a gate array version,
>except maybe for quantities under a thousand or so.


Why should they under-price a gate array?


There are advantages to conversion by the FPGA vendor that you need to
weigh against outright unit cost. For example, if your first iteration
doesn't work, will Orbit (or other) ship you FPGA's at the same price
while fixing the issues? Can they guarantee exact I/O characteristic
matching? Are they suitable for conversion of more esoteric bits of
the FPGA such as dual port memories? Will the conversion fit in the
same board socket as the FPGA did without change?


If your intention is to turn your design to gate array before
production release, then you are on a program of ASIC prototyping with
your FPGA vendor, rather than migration due to high volumes kicking
in. If this is the case, then write your VHDL, simulate it, stick it
in an FPGA if you have to to prove it on a board, then push the go
button on your ASIC vendor.


However, I would be surprised if any vendor, ASIC or FPGA, would spin
you 1000 hardwired/gate array type conversions to cost sub $10.


Think about it. Less than $10,000 of business? Some supermodels don't
get out of bed for that!


Stuart
Article: 7467
Subject: Re: Text Book and VHDL Simulator $50.00
From: "Richard B. Katz" <stellere_nospam@erols.com>
Date: 14 Sep 1997 19:56:20 GMT
Links: << >>  << T >>  << A >>



hi rich,


always wanted a set of Ginsu knives.  slim whitman you can keep.  how about
some motown or good rock for us 30-somethings?


glad you got my *slightly* sarcastic humor!
 

---------------------------------------------------------------
rk


"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
---------------------------------------------------------------


Richard Schwarz <aaps@erols.com> wrote in article
<341AF204.7E4ADE74@erols.com>...


<major snipping>


>> ok, we have book + 1 cd
>> and now we have book + 2 cd's
>> anybody got book + 3 cd's?
> 
>  Yes,
> 
> We'll through in Slim Whitman's favorite hits, and a set of Ginsu
> knives. They slice they dice, they're made in America, and they make
> Julie Ann fries!
> 
> --
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
> 
> Richard Schwarz, President              EDA & Engineering Tools
> Associated Professional Systems (APS)   http://www.associatedpro.com
> 3003 Latrobe Court                      richard@associatedpro.com
> Abingdon, Maryland 21009
> Phone: 410.569.5897                     Fax:410.661.2760
> 
> __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 7468
Subject: scsi device implementation in Xilinx FPGA
From: "Brad Simeral" <Brad_Simeral@Brown.edu>
Date: Mon, 15 Sep 1997 03:33:41 -0400
Links: << >>  << T >>  << A >>







I am hoping to develop a very simple SCSI device for instructional purposes.
The function of the device will be a solid state hard drive. I am planning
on using a Xilinx FPGA for the SCSI-2 implementation. I was wondering what
information might be available on projects of a similar nature.






Brad Simeral


Research Assistant


Brown University


Engineering Department


Laboratory for Engineering Man/Machine Systems








Article: 7469
Subject: Re: Q: Lattice Synario and ISPLSI1048
From: Tim Forcer <tmf@ecs.soton.ac.uk.nojunk>
Date: Mon, 15 Sep 1997 08:39:38 +0100
Links: << >>  << T >>  << A >>



Bulent UNALMIS wrote:
>
>I have " Lattice  Synario System ".
>Can I extend this system for ISPLSI1048 FPGA. ?
>Did you know any way ? (I search economic solve)


I assume you have the low-cost "starter" system (sometimes available on
free CD-ROM) which does not support 1048, only 1016 and 2032.  This can
be "extended" to support all Lattice devices, but only by purchasing the
full system.  This costs a lot, and is unlikely to be "economic"!


Lattice are not the only programmable logic manufacturere to provide a
limited "starter" system at low cost, in the hope that users will find
they want to upgrade to a full system.  It is a legitimate business
strategy, and buyers should always be aware that they will be investing
learning time in a system which could require substantial money
investment if it proves useful.


I don't know of any universal system (ie capable of supporting multiple
manufacturers and architectures) which can be bought as a low-cost
starter, then upgraded by buying modules to suit new design
requirements.   Anybody got suggestions?  By "low-cost" I mean low for
an individual working as a student, contractor or freelance - a company
with a regular flow of design work will find it easier to justify the
cost of the standard systems.  Perhaps one of the VHDL teach-yourself
systems fits this requirement now?


Tim Forcer               tmf@ecs.soton.ac.uk
Department of Electronics & Computer Science
The University of Southampton, UK


The University is not responsible for my opinions
Article: 7470
Subject: Re: Large FPGA
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 15 Sep 1997 09:51:36 +0000
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Here is the straight scoop about the Xilinx XC4085-3 BG560


The die size is 19.4 x 21.9 mm, big but not as humungous as quoted.


The single-piece listed price  is $ 1520.- , and the people in this
newsgroup will be smart enough to guess a production-volume price and a
future price from that.
Larger-capacity devices are in development. The world seems to want
them, and cost issues just resolve themselves with time.


Peter Alfke, Xilinx Applications


Article: 7471
Subject: how generate xilinx 3020 EPROM?
From: PeopleSoft <Allusers@cc.uab.es>
Date: Mon, 15 Sep 1997 13:59:52 +0200
Links: << >>  << T >>  << A >>

Hello!


I am looking any information about XILINX 3020
homemade programmer. Now, I am working with
Alliance v3.0 but I have not idea how generate
the external ROM.


Please, write to ea3ghs@lleida.hnet.es


eduardo alonso
http://lleida.hnet.es/~ea3ghs


Thanks in advance


Article: 7472
Subject: Re: Large FPGA
From: Erik Widding <Widdine@polaroid.com>
Date: Mon, 15 Sep 1997 09:40:11 -0300
Links: << >>  << T >>  << A >>

Martin Vorbach wrote:
> 
> > When I served a booth at EuroDac '96, across from us there
> > was a small European FPGA company that was touting a 20x30mm
> > FPGA die.
> >
> > I would like a contact if anyone knows who I am talking about.
> > Anyone knowing of an alternative largish source would
> > be greatly appreciated as well.
> >
> > Many thanks.
> >
> >
>         [M.Vorbach]  The last thing I heard was, that this company
> doesn´t exist any longer.
>         Their chip vendor was not able to implement the design.




A Xilinx sales rep popped the lid off a 4085XL when I was in his
office recently.  While I didn't take out calipers, I would have
to say that the die was atleast 20mm x 30mm.


I was utterly amazed, until of course I heard the price.  In a
559 pin PGA they are about $2000.  With prices like that, the 
parts must not be yielding, yet.  But as a venue for prototyping
ASIC, one must admit that the price isn't too obscene.




Erik Widding
Polaroid Consumer Hardware
Article: 7473
Subject: 6809 in FPGA?
From: Alfred Fuchs <alfred.fuchs@siemens.at>
Date: Mon, 15 Sep 1997 10:00:43 -0500
Links: << >>  << T >>  << A >>

We are redesigning a board with telecommunication stuff, that contains a
6809 processor.
The processor is being discontinued and we are looking for a way to
avoid major SW-rework.
Has anyone put this processor into an FPGA? 
Are there estimations how many resources in an FPGA it would take
(Altera FPGAs)?
It seems that none of the IP-companies offers such a core at the present
time.




Alfred Fuchs
Siemens PSE EZE TNT


-- 
My little grey cells speak for themselves, not for my company.
But have a look at http://www.siemens.at, .de or .com
Article: 7474
Subject: Programmable Logic News Site Update
From: Murray <mdisman@ix.netcom.com>
Date: 15 Sep 1997 15:36:30 GMT
Links: << >>  << T >>  << A >>

The site for Programmable Logic News & Views has been update with 
summaries of the June 1997 and July 1997 newsletters.


http:/www.plnv.com


Murray Disman




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