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Messages from 7550

Article: 7550
Subject: Re: Hacking bitstream formats
From: s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb)
Date: Sun, 21 Sep 1997 13:37:30 GMT
Links: << >>  << T >>  << A >>
On 21 Sep 1997 00:41:57 GMT, "Bjoern Wesen"
<bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote:

>I'd guess the FPGA manufacturers could very well release that info but then
>the synthesis software houses couldn't charge $3000 for each fpga-type
>back-end module could they, and they would get pissed at the FPGA
>manufacturers then. 

Disagree. The synthesis tools map to a logical netlist using
architecture specific library components. They do not generate a
bitstream. You still need the vendor tools for that.

>Another reason is that if a lot of public-domain unsupported generation
>tools became available, the FPGA manufacturers tech-support could get
>swamped with all the complaints from the "broken" fpga's that are just
>badly programmed because a bit in the format was "hacked" wrongly. So they

Agree.

>want only the real licensed tool companies to be able to program their
>chips.

Don't know that there is anybody left doing mainstream third party P&R
+ bitstream tools. If there were, they would have to charge a fortune,
like synthesis tool vendors, because they would not see any long term
silicon revenue.

Stuart
--
For Email remove "die.spammer." from the address
Article: 7551
Subject: Re: Hacking bitstream formats
From: s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb)
Date: Sun, 21 Sep 1997 13:37:32 GMT
Links: << >>  << T >>  << A >>
On Sun, 21 Sep 1997 03:35:29 GMT, Henry Spencer
<henry@zoo.toronto.edu> wrote:

>In article <01bcc627$b638a100$f3f12fc2@zeus>,
>There is definitely a smell of financial considerations here. :-(  It would
>sure be nice if the FPGA manufacturers would decide they were in the chip
>business and wanted to sell as many chips as possible, instead of trying to
>make money on the support software too.  Some of them have started to come 
>around, but not nearly far enough...

Did you get your compiler for your latest "turbo-nutter"
microprocessor for free?

If you are in the position to spend money on chips, you will probably
get free P&R tools from the majority of vendors.

>Oddly enough, some of said manufacturers also sell EPROMs, and print the
>programming algorithms for *those* chips in every datasheet...  There is
>just a wee hint of inconsistency here.  It couldn't have anything to do
>with the fact that EPROMs are a highly competitive market with many
>alternate sources, of course. :-)

The "programming algorithm" for FPGA's is published. It's how you get
the bitstream in. Generating the actual bitstream, like generating
your micro's hex file for your EPROM, is something completely
different.

Stuart
--
For Email remove "die.spammer." from the address
Article: 7552
Subject: Re: Hacking bitstream formats
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Sun, 21 Sep 1997 16:03:37 GMT
Links: << >>  << T >>  << A >>
In article <01bcc678$cee3ebf0$f3f12fc2@zeus>,
Bjoern Wesen <bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote:
>> Oddly enough, some of said manufacturers also sell EPROMs, and print the
>> programming algorithms for *those* chips in every datasheet...
>
>But in what way can an EPROM fail? There is a much larger error margin with
>FPGA's because they are a thousand times more complex. Get one bit wrong in
>some place, and a routing goes haywire or a row of output cells decide to
>reconfigure as large dataword matchers. 

Get one bit wrong in an EPROM, and (say) your Mars rover points its
antenna at the ground and is never heard from again.  Engineers cope with
this sort of complexity all the time. 
-- 
The operating systems of the 1950s will be out  |     Henry Spencer
next year from Microsoft.  -- Mark Weiser       | henry@zoo.toronto.edu
Article: 7553
Subject: Re: Hacking bitstream formats
From: Henry Spencer <henry@zoo.toronto.edu>
Date: Sun, 21 Sep 1997 16:17:38 GMT
Links: << >>  << T >>  << A >>
In article <34251f07.74403520@nntp.netcruiser>,
Stuart Clubb <s_clubb@die.spammer.netcomuk.co.uk> wrote:
>>There is definitely a smell of financial considerations here. :-(  It would
>>sure be nice if the FPGA manufacturers would decide they were in the chip
>>business and wanted to sell as many chips as possible...
>
>Did you get your compiler for your latest "turbo-nutter"
>microprocessor for free?

Actually, it's by no means unheard-of for microprocessor builders to hand
out free compilers (typically, code generators for GCC), to encourage
people to use their chips.  Only the smart ones do this, of course...

>If you are in the position to spend money on chips, you will probably
>get free P&R tools from the majority of vendors.

You left a word out of that sentence:  "If you are in the position to
spend *big* money on chips..."  But if I'm in the position to spend big
money on chips, I probably don't care about the cost of the software
anyway. 

>>Oddly enough, some of said manufacturers also sell EPROMs, and print the
>>programming algorithms for *those* chips in every datasheet...
>
>The "programming algorithm" for FPGA's is published. It's how you get
>the bitstream in...

The feed-the-bits-in algorithm for *some* FPGAs is published.  Not all.
And with an EPROM, that's all I need to take advantage of the parts,
including the possibility of misprogramming or even destroying them by
being sloppy.  For some reason, the problem of supporting badly-designed
programming hardware/software doesn't stop the EPROM builders from full
disclosure...

>Generating the actual bitstream, like generating
>your micro's hex file for your EPROM, is something completely
>different.

If I've got (say) a gate-level design, I really don't care whether there's
one step or two between that and the chip.  If some of the information
needed to build the necessary software is secret, it doesn't matter just
which step it's needed for.
-- 
The operating systems of the 1950s will be out  |     Henry Spencer
next year from Microsoft.  -- Mark Weiser       | henry@zoo.toronto.edu
Article: 7554
Subject: Window CE news group ? ?
From: hugohh3h@aol.com (Hugohh3h)
Date: 21 Sep 1997 22:57:42 GMT
Links: << >>  << T >>  << A >>
 Hi:
      Is  there  other  News  group   talk  about  Window  CE  besides

  Microsoft  Window CE  operating  system. 
       

Article: 7555
Subject: Xilinx M1 Back Annotated SDF Problem
From: david.storrar@gecm.com (David Storrar)
Date: 22 Sep 1997 08:02:09 GMT
Links: << >>  << T >>  << A >>
Hi,

Does anyone know if there is a problem (feature?) with the SDF 
back annotation of IOB flip-flops from Xilinx M1.

I'm targeting a XC4062XL and when I generate the VHDL netlist and 
associated SDF files, all the timing check values for the IOB 
flip-flop are zero - other than the pulse width, which is 6 ns.  
This is somewhat at odds with the data sheet where there _are_ 
values given for setup and hold (surprisingly enough :-))and a 
_3_ns_ pulse width (given for output flip-flops only).

This only manifests itself in the IOB flip-flops, the values are 
all present for flip-flops in the CLBs.

Can anyone help?

Dave

--
David Storrar
Development Engineer
GEC-Marconi Avionics
--

Article: 7556
Subject: Re: Hacking bitstream formats
From: s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb)
Date: Mon, 22 Sep 1997 11:23:55 GMT
Links: << >>  << T >>  << A >>
On Sun, 21 Sep 1997 16:17:38 GMT, Henry Spencer
<henry@zoo.toronto.edu> wrote:

>Actually, it's by no means unheard-of for microprocessor builders to hand
>out free compilers (typically, code generators for GCC), to encourage
>people to use their chips.  Only the smart ones do this, of course...

I wonder if it really benefits them financially?

GCC is usually unsupported by the chip manufacturers tech support.
Occasionally you might get help from a "generous/enthusiastic" apps
guy (or girl), but by and large, users are on their own. I don't think
the FPGA world is ready for that yet. (Plus, it's a much smaller
market to support such philanthropy anyway).

>You left a word out of that sentence:  "If you are in the position to
>spend *big* money on chips..."  But if I'm in the position to spend big
>money on chips, I probably don't care about the cost of the software
>anyway. 

Maybe your definition of *big* is different to mine. With most vendors
having starter kits at one level or another, under $1000, I don't see
the entry level as too high. They also have educational programs too.
Many vendors re-sell tools, and have expensive software teams to
maintain their own tools. However, as it all costs money, I ask this
question to all:

What value of annual business would you expect to do with your
customer if (say) you gave him $1,000 worth of "product" for free up
front, and on-going design support?

>The feed-the-bits-in algorithm for *some* FPGAs is published.  Not all.

You mean some aren't? How are they programmed?

>And with an EPROM, that's all I need to take advantage of the parts,
>including the possibility of misprogramming or even destroying them by
>being sloppy.  For some reason, the problem of supporting badly-designed
>programming hardware/software doesn't stop the EPROM builders from full
>disclosure...

OK, but I figure you hang the EPROM off a micro, so you need something
to generate code for the micro...

>If I've got (say) a gate-level design, I really don't care whether there's
>one step or two between that and the chip.  If some of the information
>needed to build the necessary software is secret, it doesn't matter just
>which step it's needed for.

Now we are getting closer. You have a front-end tool to generate the
"design", and need the place and route tools. Try the same approach
with FPGA vendors, and you may be pleasantly surprised. As far as I
can see, the bitstream information is always going to be proprietary
to help in preventing reverse-engineering.

Stuart
--
For Email remove "die.spammer." from the address
Article: 7557
Subject: cpld and fpga help needed
From: Teun Docter <teund@htsa.hva.nl>
Date: Mon, 22 Sep 1997 13:42:58 +0200
Links: << >>  << T >>  << A >>
Hello,

I am an electrical engeneering student and I need to do a presentation
on cpld's
and fpga.. Now I don't know what exactly these devices are.

So what I am looking for is a description of these devices, which
does'nt
immideatly go in to too much technical details..

Is dis available somewhere on the web??

The main questions I need awnsered are:

What is a CPLD and how is it built up..

What is the difference between a CPLD and an FPGA??


Tanx alot..

Teun Docter
teund@htsa.hva.nl
Article: 7558
Subject: Re: Hacking bitstream formats
From: "Rich K." <rich.katz-nospam@gsfc.nasa.gov>
Date: 22 Sep 1997 15:02:04 GMT
Links: << >>  << T >>  << A >>
hi guys,

please see the embedded comments.

------------------------------------------------------------
rk
"there's nothing like real data to screw up a great theory,"
- me, modified from the slightly more colorful original
------------------------------------------------------------

Stuart Clubb <s_clubb@die.spammer.netcomuk.co.uk> wrote in article
<34258728.101064353@nntp.netcruiser>...
> On Sun, 21 Sep 1997 16:17:38 GMT, Henry Spencer
> <henry@zoo.toronto.edu> wrote:
> 
> >Actually, it's by no means unheard-of for microprocessor builders to
hand
> >out free compilers (typically, code generators for GCC), to encourage
> >people to use their chips.  Only the smart ones do this, of course...
> 
> I wonder if it really benefits them financially?
> 
> GCC is usually unsupported by the chip manufacturers tech support.
> Occasionally you might get help from a "generous/enthusiastic" apps
> guy (or girl), but by and large, users are on their own. I don't think
> the FPGA world is ready for that yet. (Plus, it's a much smaller
> market to support such philanthropy anyway).
> 

for fpgas, i don't want to be on my own.  and i don't want to have what
i call the cable-tv problem.  back in the '70s, when we first got cable,
and the reception was no good, we'd call the cable guy.  of course he would
blame the tv.  then the tv guy would come and he would blame the cable
signal.
i think it's best to have ONE place to call and get your problem solved -
and
having the software guys and the chip guys in one place is critical to
gettting
problems solved fast and accurately.  for hi-rel applications, i don't
think I
want to be using 'hacked' architectural documents for the design of the
design
tool.  and in the case where the architectural details are made public
domain
there needs to be careful checking that free lance s/w guys' products are 
compatible with the fpgas, as manufacturers update models, revise mask
sets, 
programming algorithms, upgrade processing, etc. also, other tools need to
be 
included in this discussion, such as static timing analyzers.

> >You left a word out of that sentence:  "If you are in the position to
> >spend *big* money on chips..."  But if I'm in the position to spend big
> >money on chips, I probably don't care about the cost of the software
> >anyway. 
> 
> Maybe your definition of *big* is different to mine. With most vendors
> having starter kits at one level or another, under $1000, I don't see
> the entry level as too high. They also have educational programs too.
> Many vendors re-sell tools, and have expensive software teams to
> maintain their own tools. However, as it all costs money, I ask this
> question to all:
> 
> What value of annual business would you expect to do with your
> customer if (say) you gave him $1,000 worth of "product" for free up
> front, and on-going design support?
> 

i see starter kits for many fpga's, including sample plug-in boards, for
low cost *advertised* in this NG all of the time.  and vendor s/w seems
pretty affordable and is priced for just a few thousand dollars.  actel
stuff, which i use primarily, has *free* p&r software, static timing 
analyzer, libraries, hdl compiler, etc. for <= 8,000 gates.  for the 
unlimited version, it's just a few thousand $.  i don't see how anybody
could be in business (gov't or private) that won't spend that amount of
money on tools and don't see how we can expect up-to-date, QUALITY and
GUARANTEED and SUPPORTED tools for free.

> >The feed-the-bits-in algorithm for *some* FPGAs is published.  Not all.
> 
> You mean some aren't? How are they programmed?
> 

uh, using the magic activator, that's how!


> >And with an EPROM, that's all I need to take advantage of the parts,
> >including the possibility of misprogramming or even destroying them by
> >being sloppy.  For some reason, the problem of supporting badly-designed
> >programming hardware/software doesn't stop the EPROM builders from full
> >disclosure...
> 
> OK, but I figure you hang the EPROM off a micro, so you need something
> to generate code for the micro...
> 

i think that there's a MAJOR leap between understanding an EPROM and an
FPGA and wouldn't group them in the same architectural class.

> >If I've got (say) a gate-level design, I really don't care whether
there's
> >one step or two between that and the chip.  If some of the information
> >needed to build the necessary software is secret, it doesn't matter just
> >which step it's needed for.
> 
> Now we are getting closer. You have a front-end tool to generate the
> "design", and need the place and route tools. Try the same approach
> with FPGA vendors, and you may be pleasantly surprised. As far as I
> can see, the bitstream information is always going to be proprietary
> to help in preventing reverse-engineering.

is this reverse engineering the design or the manufacturers architecture
and implementation details.

Article: 7559
Subject: Circuit Board & FPGA Designers
From: "Hunter Int." <cleaner@starnetinc.com>
Date: 22 Sep 97 16:45:08 GMT
Links: << >>  << T >>  << A >>
Hi,

We have an opportunity for an individual who has done some complex Circuit
Board/FPGA design to work at a place where cutting edge technology is the
norm, and one of the very best design staffs in the country awaits.

This position is for someone who has between 3-10 years of high performance
custom circuit design under his/her belt.  You will be working on some of
the "neatest" projects you've ever seen, and will become a stellar hardware
designer for your efforts.

Some of the "buzz":  We are looking for High Speed Digital Designers,
having some experience with PLD's, FPGA's (ASICS), complex designs (nothing
simple at this place), understands timings, etc...  Not a person who still
needs a lot of instruction, we are hoping to find an individual who can
stand alone and bring a project in from scratch to production.

This is a great company!  Our guarantee is this:  If you go in and chat
with these people, you WILL want to work there, especially if you can do
this type of work.

They are located on the North side of Chicago, near Skokie or Evanston,
just off the Kennedy.  Salary will be very nice, they're not cheap, as
they're looking for the best we can bring in.

Please E-mail or Fax us at:

Hunter International
E-mail: cleaner@starnetinc.com
Fax: (815)356-9225

Thanks,

Dave... 
Article: 7560
Subject: Re: cpld and fpga help needed
From: "Steven K. Knapp" <sknapp @ optimagic.com>
Date: 22 Sep 1997 16:48:54 GMT
Links: << >>  << T >>  << A >>
Teun Docter <teund@htsa.hva.nl> wrote in article
<342659C2.5406@htsa.hva.nl>...
| Hello,
| 
| I am an electrical engeneering student and I need to do a presentation
| on cpld's
| and fpga.. Now I don't know what exactly these devices are.
| 
[snip]
| Is dis available somewhere on the web??
Yes.  You might find some of the information that you are looking for on
The Programmable Logic Jump Station at 'http://www.optimagic.com'.
| 
| The main questions I need awnsered are:
| 
| What is a CPLD and how is it built up..

See the page under construction at
'http://www.optimagic.com/faq.html#CPLD'.
| 
| What is the difference between a CPLD and an FPGA??

See 'http://www.optimagic.com/comparison.html'
| 
| 
| Tanx alot..
| 
| Teun Docter
| teund@htsa.hva.nl
| 
Article: 7561
Subject: Re: Q: Lattice Synario and ISPLSI1048
From: Kevin Bush <kevin.bush@minc.com>
Date: Mon, 22 Sep 1997 12:02:59 -0600
Links: << >>  << T >>  << A >>
Tim Forcer wrote:
> 
> I don't know of any universal system (ie capable of supporting multiple
> manufacturers and architectures) which can be bought as a low-cost
> starter, then upgraded by buying modules to suit new design
> requirements.   Anybody got suggestions?  By "low-cost" I mean low for
> an individual working as a student, contractor or freelance - a company
> with a regular flow of design work will find it easier to justify the
> cost of the standard systems.  Perhaps one of the VHDL teach-yourself
> systems fits this requirement now?

I missed the beginning of this conversation, but our VHDL EASY product
may be an acceptable alternative. It won't solve your place-and-route
problems, but it does offer a full VHDL synthesis engine, an interactive
VHDL training tool, and your choice of one device module for $495.
Additional device modules can be added for $495 each. For more
information, please see www.minc.com.  KB.

-- 

--------------------------------------------------
Kevin Bush                       MINC Incorporated
VP Marketing                       6755 Earl Drive
719-532-7103                      Colorado Springs
719-590-7330 FAX                     Colorado, USA
kevin.bush@minc.com                          80918
--------------------------------------------------
Article: 7562
Subject: Re: Hacking bitstream formats
From: nstrater@mcmail.com
Date: Mon, 22 Sep 1997 20:14:03 GMT
Links: << >>  << T >>  << A >>
Hi again,

thanks for all those posts, interesting discussion. 
How about a little interlude...

V = fpga-chip vendor

P = private, non-firm, non-big-bucks kind of person

------------------
V: Look kiddo what I've got... (dangles a beautiful little black
beetle in the air, with lots of legs on it)

P: What is it, what is it, lemme see!

V: It's a new chip! And you can do anything you want with it!

P: Really??? (incredulous) Oooh - I want it!! I want it now! How much
is it?

V: Er, not that cheap. We've got to live on something and all that,
you know. But since it's you, I'll give it to you for, say, $$$$$$ !

P: That much - oh well, if it *can* do *anything* I want it. Here.
(gives him all his pocket money)

V: (hands it over, plus the data on it, counts the money, very
carefully...)

P: (marvels at his new chip, leafing through the data excitedly,
starts fiddling with wires and pcbs...)

V: (shifting uneasily, not quite sure whether he ought to make a run
for it, or not)

P: Er, hang on, there's a few parts missing here in the data you gave
me. How do I actually use the thing?

V: Oh, that bit.

P: Whaddayya mean *that* bit! That's the whole point, isn't it?

V: Hang on, ok. I know this guy, right?

P: Yeees? (getting suspicious)

V: (sweating) Well, he writes software, beautiful software, ok. He's
got it all written for you, and this design tool and that add-on,
and...

P: Ok, ok, how much is it then?

V: (loosening his collar and shifting all over the place) Erm, well,
it's a lot of work doing all that programming, you know. Not to
mention testing, debugging, writing manuals ... - anyway, you really
ought to speak to him, you know.

P: (getting impatient) Skip the details, man. How much???

V: Not all that much, considering. Just $$$$$$$$$$$$$$

P: You're kidding.

V: (not looking as if he were) Erm, that's plus tax...

P: No way - I'd rather write my own software, if you don't mind. Just
pass over the missing bits of info, and we're done.

V: Of course, no problem. Right away.

P: (waiting and staring at him)

V: (waiting and staring back)

P: Well?

V: (getting out his notebook) So what kind of volume were we talking
about here? (starting to scribble)

P: What? (surprised) 

V: Volume. You know, how many?

P: What, 1 of course.

V: (snapping his notebook shut and getting serious) You're not a
hobbyist or a student, are you? (not without a certain disgust in his
voice)

P: Look, I've got to try out a few things first. Later, maybe I'll buy
a few more.

V: Ah! (brightening up) Why didn't you say so in the first place!
(getting out his notebook again and scribbling) How many more, was
that?

P: Er, well, 2 or 3. They are expensive you know.

V: (frowning again, fiddling with his coat) There's just no doing
business with you, is there! Well, thank you so much for your time.
Have to run... (moving off)

P: (panicking) But what about the formatting data? 

V: (further away now) Come on, be reasonable! You've got the chip
haven't you?

P: (crying out) You're telling *me* to come on! What am I supposed to
do then? Borrow an electron microscope to see what's going on? You
can't be serious!!
 
V: (from the distance) You'll be alright - just speak to that fellow I
mentioned. Bye now...

P: (forlornly) Come on - you can't leave me here like this. I'm low on
bucks just now. What am I going to do without the data? Come on - I'll
even buy 4 of your chips, maybe 5 ... Don't go!

V: (gone)

P: This is the end. (jumps off the nearest cliff)
----------------




 




Article: 7563
Subject: I2C bus in an ALTERA FPGA (FLEX 10K50)
From: jolly.ayse@removethis.hol.fr (Emmanuel Jolly)
Date: Mon, 22 Sep 1997 20:38:06 GMT
Links: << >>  << T >>  << A >>
I am currently working on an ALTERA 10K50 FPGA in AHDL. Some registers
in this FPGA will have to be accessed (read and written) through an
I2C link. If anybody has such a design available, I will be very
interested.

Thanks in advance.
E. JOLLY
Article: 7564
Subject: Circuit Board & FPGA Designers
From: "Hunter Int." <cleaner@starnetinc.com>
Date: 22 Sep 97 23:07:23 GMT
Links: << >>  << T >>  << A >>
Hi,

We have an opportunity for an individual who has done some complex Circuit
Board/FPGA design to work at a place where cutting edge technology is the
norm, and one of the very best design staffs in the country awaits.

This position is for someone who has between 3-10 years of high performance
custom circuit design under his/her belt.  You will be working on some of
the "neatest" projects you've ever seen, and will become a stellar hardware
designer for your efforts.

Some of the "buzz":  We are looking for High Speed Digital Designers,
having some experience with PLD's, FPGA's (ASICS), complex designs (nothing
simple at this place), understands timings, etc...  Not a person who still
needs a lot of instruction, we are hoping to find an individual who can
stand alone and bring a project in from scratch to production.

This is a great company!  Our guarantee is this:  If you go in and chat
with these people, you WILL want to work there, especially if you can do
this type of work.

They are located on the North side of Chicago, near Skokie or Evanston,
just off the Kennedy.  Salary will be very nice, they're not cheap, as
they're looking for the best we can bring in.

Please E-mail or Fax us at:

Hunter International
E-mail: cleaner@starnetinc.com
Fax: (815)356-9225

Thanks,

Dave... 
Article: 7565
Subject: Re: Hacking bitstream formats
From: daveb@iinet.net.au (David R Brooks)
Date: Mon, 22 Sep 1997 23:17:58 GMT
Links: << >>  << T >>  << A >>
"Bjoern Wesen" <bjorn@sparta.lu.se.REMOVE.THIS.TO.MAIL.ME> wrote:
[Snipped discussion of FPGA hacking]

:Even normal small PALCE22V10's programming algorithms are tradesecrets,
:I've only heard about the GAL16V8's having a public programming algorithm.
:It sucks, but that's the way it is I guess :(

 Is that GAL algorithm online anywhere? Could someone post a URL?


--  Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34
 What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7566
Subject: Re: Hacking bitstream formats
From: db <"brandis<NO-SPAM>"@dlcc.com>
Date: Mon, 22 Sep 1997 19:14:48 -0700
Links: << >>  << T >>  << A >>
Joseph H Allen wrote:
> 
>
> 
> I think it's pretty clear that they are just protecting their software
> monopolies.  Why else would Xilinx have bought neocad, for example?  If you
> don't know, neocad was a company which reverse engineered the bitstream
> formats and came out with their own improved place & route software.

Is this true?  I believe that Neocad could have placed & routed a Xilinx
FPGA and output a .lca file, which is just a netlist-like description of
the final design.  At that point the user would run the Xilinx Makebits
utility to create the actual bitstream.  You would not need to know the
actual bitstream format.  Of course, you would still have to buy
software from Xilinx.  However, I never used Neocad so I am not sure of
any of this...I'm only guessing.  Am I right?

> Note
> they didn't get sued, they just got bought.  Keep that in mind if you do
> successfully reverse-engineer the bitstream formats: your prize will be
> Xilinx buying you for millions of dollars.
> 

Just curious,

-db
Article: 7567
Subject: Re: I2C bus in an ALTERA FPGA (FLEX 10K50)
From: "Daniel K. Elftmann" <dane@usinternet.com>
Date: 23 Sep 97 04:24:39 GMT
Links: << >>  << T >>  << A >>
Check out www.macrocad.com.  They have a 8584 I2C Controller.  I believe
they have either Verilog or VHDL source available.  

Emmanuel Jolly <jolly.ayse@removethis.hol.fr> wrote in article
<3426d5dc.20803942@news.hol.fr>...
> I am currently working on an ALTERA 10K50 FPGA in AHDL. Some registers
> in this FPGA will have to be accessed (read and written) through an
> I2C link. If anybody has such a design available, I will be very
> interested.
> 
> Thanks in advance.
> E. JOLLY
> 
Article: 7568
Subject: Re: Lattice Synario and ISPLSI1048
From: "Daniel K. Elftmann" <dane@usinternet.com>
Date: 23 Sep 97 04:28:11 GMT
Links: << >>  << T >>  << A >>
Actel has free software downloadable off the web site for FPGA devices up
to 8K.  This includes ActMap VHDL synthesis, ActGen module generator, and
Designer Place and Route.

Daniel Elftmann
Actel FAE

Bulent UNALMIS <unalmis@club-internet.fr> wrote in article
<341A5F6C.359A@club-internet.fr>...
> Hello,
> 
> I have " Lattice  Synario System ".
> Can I extend this system for ISPLSI1048 FPGA. ?
> Did you know any way ? (I search economic solve)
> 
> Thanks
> 
Article: 7569
Subject: Re: Lattice Synario and ISPLSI1048
From: Achim Gratz <gratz@ite.inf.tu-dresden.de>
Date: 23 Sep 1997 08:44:11 +0200
Links: << >>  << T >>  << A >>
"Daniel K. Elftmann" <dane@usinternet.com> writes:

> Actel has free software downloadable off the web site for FPGA devices up
> to 8K.  This includes ActMap VHDL synthesis, ActGen module generator, and
> Designer Place and Route.

Oh, did you mention that you can't use the 3200 series _with_ RAM,
because they start at 10K gates (the 32100DX).  You can generate
macros with RAM allright, but then you're stuck.  Could Actel please
consider raising the bar to 10K (that would just add the 14100 and the
32100, IIRC) or limiting to the gates used instead of available?


Achim Gratz.

--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW:    http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 463 - 8325
Article: 7570
Subject: Efficient test design for XC4000 devices ?
From: Johannes Sølhusvik <jso@nocrc.abb.no>
Date: Tue, 23 Sep 1997 10:39:55 +0200
Links: << >>  << T >>  << A >>
For safety reasons, before configuring my Xilinx (xc4000 series) with my
design, I must test "all" (or as much as possible) of the CLB's in the
circuit. Does anyone know of an efficient test design that does this ? I
have not succeeded in finding any application notes on this.
Article: 7571
Subject: Re: I2C bus in an ALTERA FPGA (FLEX 10K50)
From: Rune Baeverrud <r@acte.no>
Date: Tue, 23 Sep 1997 11:49:49 +0200
Links: << >>  << T >>  << A >>
Emmanuel Jolly wrote:
> 
> I am currently working on an ALTERA 10K50 FPGA in AHDL. Some registers
> in this FPGA will have to be accessed (read and written) through an
> I2C link. If anybody has such a design available, I will be very
> interested.

I have designed an I2C bus controller macrofunction that is available
for free at my web site http://www.acte.no/freecore 

I was not sure from reading your message if you wanted a master or
slave, but I think I will design an I2C slave also to be available soon
on my web site. I know for sure that my I2C master function has already
been successfully implemented in some consumer products, so there should
be a low risk in trying to use it.

Regards,
Rune Baeverrud
Article: 7572
Subject: Xilinx M1 Back Annotated SDF Question
From: david.storrar@gecm.com (David Storrar)
Date: 23 Sep 1997 15:17:35 GMT
Links: << >>  << T >>  << A >>
Hi,


Does anyone know if there is a problem (feature?) with the SDF 
back annotation of IOB flip-flops from Xilinx M1.


I'm targeting a XC4062XL and when I generate the VHDL netlist and 
associated SDF files, all the timing check values for the IOB 
flip-flop are zero - other than the pulse width, which is 6 ns.  
This is somewhat at odds with the data sheet where there _are_ 
values given for setup and hold (surprisingly enough :-))and a 
_3_ns_ pulse width (given for output flip-flops only).


This only manifests itself in the IOB flip-flops, the values are 
all present for flip-flops in the CLBs.


Can anyone help?


Dave


--
David Storrar
Development Engineer
GEC-Marconi Avionics
--
Article: 7573
Subject: Re: Hacking bitstream formats
From: jhallen@world.std.com (Joseph H Allen)
Date: Tue, 23 Sep 1997 15:26:42 GMT
Links: << >>  << T >>  << A >>
In article <34272618.4AF3@dlcc.com>, db  <NO-SPAM> wrote:
>Joseph H Allen wrote:

>> I think it's pretty clear that they are just protecting their software
>> monopolies.  Why else would Xilinx have bought neocad, for example?  If you
>> don't know, neocad was a company which reverse engineered the bitstream
>> formats and came out with their own improved place & route software.

>Is this true?  I believe that Neocad could have placed & routed a Xilinx
>FPGA and output a .lca file, which is just a netlist-like description of
>the final design.  At that point the user would run the Xilinx Makebits
>utility to create the actual bitstream.  You would not need to know the
>actual bitstream format.  Of course, you would still have to buy
>software from Xilinx.  However, I never used Neocad so I am not sure of
>any of this...I'm only guessing.  Am I right?

I've never used neocad either, so I'm not absolutely sure.  This is the
impression I got from the discussions that went on here at the time.

It's interesting because the makebits program is not protected by the
hardware key (only the place & route programs are: ppr and apr).  If it's
not that important a program, they should give it and documentation about
the .LCA format out as freeware.  We would all trust them then and this
issue would be dead.  Yep, I'm dreaming.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 7574
Subject: Re: HELP: FIFO's on an FPGA
From: andym@trend.demon.co.uk (Andrew Morley)
Date: Tue, 23 Sep 97 15:47:33 GMT
Links: << >>  << T >>  << A >>
In article <341D6FE0.256B8C63@xilinx.com>
           peter.alfke@xilinx.com "Peter Alfke" writes:

> FIFOs are very simple at the global and conceptual level, but quite
> demanding in their details, especially when implemented in silicon that
> is not infinitely fast.

:-0

You mean there's silicon available which is infinitely fast?  I guess I haven't 
been keeping abreast of the latest technology.

-- 
 -----------------------------------------------------------------------------
| Andrew Morley, Design & Development, Trend Communications Ltd, High Wycombe.|
| email: andrew.morley@trendcomms.com  Phone +44 1628-524977        Bucks, UK.|
 -----------------------------------------------------------------------------



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