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Messages from 7950

Article: 7950
Subject: Re: Altera EPC1 and Chipmaster 6000
From: Russell Magee <bigruss@cheetah.spots.ab.ca>
Date: 2 Nov 1997 04:00:02 GMT
Links: << >>  << T >>  << A >>
Ying C. <ying@soda.CSUA.Berkeley.EDU> wrote:


> Russell,

> What version of Max+plus II are you using to generate the pof file? I know
> in in the newester version, 8.1, the default POF file generated for 10k10,
> 10k20 and 10k30 is for EPC1441, not EPC1. You have to perform combine
> programming file to covert it to EPC1 format. Perhaps that is your
> problem?

  I will check this, that is a distinct possibility. Thanks for the info!
  (We're using version 8.0 -- haven't gotten around to installing 8.1 yet)

  -Russ

Article: 7951
Subject: Re: Questions about FPGA hardware design
From: Ho Siu Hung <eg_hsh@stu.ust.hk>
Date: Mon, 3 Nov 1997 01:52:08 +0800
Links: << >>  << T >>  << A >>
On 31 Oct 1997, Cotton Seed wrote:
> Partially inspired by Jan Gray's site on Homebrew RISCs in FPGAs, I'd
> like to start doing FPGA-based hardware design.  But I'm not sure

What is the address of that site?

By the way, I have the following problem:
I need to download the bitstream to FPGA which is in PGA411 (maybe larger)
socket (XC4062XL).  However, I have got only a Xilinx Demo board (with
XC4003-PC84) and the XChecker cable and software.  What is the fastest way
to do this?  Here comes the problem of voltage (5V 4003, 3V XL) and socket
difference....
-------------------------------------------------------------------------------
| Best Regards, 	  +--------+   | Campus: eg_hsh@stu.ust.hk	      |
| David Ho		  | к |   |	 cshosh@cs.ust.hk	      |
| Ho Siu Hung		  +--------+   |   	                              |
| University of Science and Technology |    ICQ: 798357                       |
| Computer Engineering Year 3 (CPEG)   =======================================|
-------------------------------------------------------------------------------


Article: 7952
Subject: $1000/wk Donating Sperm
From: luke@kdine.com
Date: Sun, 02 Nov 1997 19:13:52 GMT
Links: << >>  << T >>  << A >>
visit  http://206.155.252.182/index.html   for more detailed information on 
how you can partake in the sperm donor program... 




=<<>==<>=<=><><<=>><
Article: 7953
Subject: Re: XILINX pin compatible replacements
From: arnim@atlantis.actrix.gen.nz (Arnim Littek)
Date: 2 Nov 97 19:50:44 GMT
Links: << >>  << T >>  << A >>
In article <34551D1A.B5DB5A29@xilinx.com>,
Peter Alfke  <peter.alfke@xilinx.com> wrote:
>there might be devices that happen to have their supply pins in the same
>location, whatever significance that has.

And the XC6200 has that level of pin compatibility too.  Now, if one could
get a non-volatile part with that level of pin-compatibility, without 
having to commit to mask volumes...  

Arnim.> 
> 
> 
>


-- 
Arnim Littek                                    arnim@actrix.gen.nz
Actrix Networks Ltd.                            fax +64-4-801-5335
uucp/PPP/SLIP/BBS accounts                      tel +64-4-801-5225
Article: 7954
Subject: Re: 'compatible' fpgas
From: Peter Alfke <peter@xilinx.com>
Date: Sun, 02 Nov 1997 13:32:38 -0800
Links: << >>  << T >>  << A >>
Richard B. Katz wrote:

> hi pete,
>
> i think there is some significance for getting pins to line up and
> i'll add clock and other special pins to the supply pins.  i have had
> feedback from customers that they like the flexibility to potentially
> expand capabilities in the future w/out having to make new boards.

I agree.
Maybe I was addressing the wrong question.
Within Xilinx we believe very much in pin-out compatibility. Take any
package, and any XC4000 or XC5200 device available in that package has
the same pin-out. So you can start with a larger chip, then streamline
to a smaller chip, or the other way 'round, expand your design, or even
go to a cheaper family, like XC5200, all without changing your pc-board.

I was, perhaps erroneously, addressing the issue of different
manaufacturers second-sourcing each other's parts.
I can understand why Atmel copies the Xilinx pin-out ( it would be silly
not to do that and thus take advantage of a de facto standard), but that
does not mean that a completely different architecture can allow you to
implement a compatible design.

Peter Alfke, Xilinx Applications

Article: 7955
Subject: Re: Questions about FPGA hardware design
From: Cotton Seed <cottons@lcs.mit.edu>
Date: 02 Nov 1997 21:05:02 -0500
Links: << >>  << T >>  << A >>
Ho Siu Hung <eg_hsh@stu.ust.hk> writes:
> On 31 Oct 1997, Cotton Seed wrote:
> > Partially inspired by Jan Gray's site on Homebrew RISCs in FPGAs, I'd
> > like to start doing FPGA-based hardware design.  But I'm not sure
> 
> What is the address of that site?

http://www3.sympatico.ca/jsgray/homebrew.htm

        - Cotton
Article: 7956
Subject: deleted spam
From: IntimateSVC@GetPaid.com
Date: Mon, 3 Nov 1997 07:57:03
Links: << >>  << T >>  << A >>
>>>>>>> SPAM DELETED BY ARCHIVE OWNER (better late than never)


Article: 7957
Subject: deleted spam
From: IntimateSVC@GetPaid.com
Date: Mon, 3 Nov 1997 07:57:06
Links: << >>  << T >>  << A >>
>>>>>>> SPAM DELETED BY ARCHIVE OWNER (better late than never)


Article: 7958
Subject: Re: Altera EPC1 and Chipmaster 6000
From: David Pashley <david@fpga.demon.co.uk>
Date: Mon, 3 Nov 1997 16:22:49 +0000
Links: << >>  << T >>  << A >>
In article <6340eo$m00@nr1.calgary.istar.net>, Russell Magee
<bigruss@cheetah.spots.ab.ca> writes
> Hi all,
>
>   We've hit a snag here at work, trying to program the Altera EPC1 
>configuration
>EPROM using the Chipmaster 6000 from Logical Devices Inc. Logical Devices says 
>they
>have verified the 6000 with the EPC1, but we can't seem to program any with our 
>unit
>(it always fails on verify pass).
>   Has anyone else experienced problems with the EPC1 part? We've heard rumours
>(from another EPROM programmer maker) that Altera has somehow changed the 
>programming
>requirements of the EPC1 *without* changing the part number! If so, all I can 
>say is
>"$%@#!$!". We would have bought Altera's own programming unit, but the delivery 
>lead
>time was many weeks. Sigh..
>
>  Any advice appreciated,
>   -Russ Magee
>
>

Programmable device vendors constantly change the programming algorithm
without changing the device number or informing users - it's an accepted
practice. However, the information is available to programmer vendors
(sometimes only under NDA).

Data I/O estimates that for 68% of devices the programming spec. changes
at least 4 times (source: Application Note "Why using outdated
programming algorithms is risky" - Data I/O Corp.)
-- 
David Pashley
Article: 7959
Subject: Re: Pin compatible
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 03 Nov 1997 09:16:17 -0800
Links: << >>  << T >>  << A >>
APS wrote:

> It does appear that using the FFs in the XILINX CLB, that at least one
> require the use of an LUT, while all the ATMEL FFs are available
> without using LUTs.

One slight correction:In XC4000, you can use the two flip-flops and the
two LUTs completely independently. You drive one flip-flop with DIN and
the other with H1, through the THIRD look-up table.  So technically APS
was right, but I want to make sure that everybody understands: there
need not be any connection between the two main 4-input LUTs and the two
flip-flops. They can be independent.

Peter Alfke, Xilinx Applications

>   

Article: 7960
Subject: interface between FPGA & user?
From: Zhi Ye <ye@ece.nwu.edu>
Date: Mon, 03 Nov 1997 14:01:37 -0600
Links: << >>  << T >>  << A >>
Hi,
   I'm going to work on some compiler, the goal is to make a C program
run on a FPGA integrated system.
   As I see it,I have some questions:
   1. What is going on with FPGA integrated system now? Is there any
product ?
    (What I mean by 'FPGA integrated system', is some computer with a
CPU and a FPGA, the CPU can dynamicly change the FPGA's function,
ie:when CPU tries to run a MPEG program, the FPGA can be a MPEG
card;when CPU tries to run a JPEG program, the FPGA can then be a JPEG
card.) 
   2. How to change the function of a FPGA? How long does it take?Is
there a standard among all the products from different companies?  
Assume there is a function library, containing the pre-designed FPGA
configuration file for the functions.
   3. What language can I use to generate a FPGA design? There seems to
be several choices:VHDL,X-BLOX ?
   4. How can I know some more about FPGA?

Thanks.

-- 
Z. Alex Ye
Article: 7961
Subject: Re: Configuration of XC4000 FPGAs with JTAG
From: daveb@iinet.net.au (David R Brooks)
Date: Mon, 03 Nov 1997 23:47:43 GMT
Links: << >>  << T >>  << A >>
britta.becker@t-online.de (Rainer Becker) wrote:

[snip]
:Is there any tool for configuring the XC4000 devices over
:the JTAG interface?
:
 See my website (URL below) for how to configure XC4000 over the JTAG.
Follow the "free stuff" pointer on the homepage.


--  Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34
 What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7962
Subject: Re: Questions about FPGA hardware design
From: daveb@iinet.net.au (David R Brooks)
Date: Mon, 03 Nov 1997 23:49:38 GMT
Links: << >>  << T >>  << A >>
Ho Siu Hung <eg_hsh@stu.ust.hk> wrote:

[snip]
:I need to download the bitstream to FPGA which is in PGA411 (maybe larger)
:socket (XC4062XL).  However, I have got only a Xilinx Demo board (with
:XC4003-PC84) and the XChecker cable and software.  What is the fastest way
:to do this?  Here comes the problem of voltage (5V 4003, 3V XL) and socket
:difference....

 See my website for doing this via the JTAG port. Being serial, you
need only a few voltage shifters. Follow the "free stuff" pointer on
the homepage.


--  Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34
 What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 7963
Subject: I'm interested in FPGAs. How do I start ?
From: Darxus <darxus@monet.op.net>
Date: Mon, 3 Nov 1997 21:36:23 -0500
Links: << >>  << T >>  << A >>

I know very little about FPGAs, and I wish to remedy this.

I believe this technology may be within my price range, in fact, it may be
possible for me to be able to get a setup with a number of these chips.

I could not find a FPGA FAQ on ftp://rtfm.mit.edu, and unfortunately there
seem to be bad connections between me and http://www.plnv.com (somewhere
in the netcom.com domain) at the moment.

I am interested in the possibility of porting such things as:
 * OpenGL (http://www.sgi.com/Technology/OpenGL)
 * general (substantial?) floating point acceleration
 * MPEG video & audio (other formats as well)
 * distributed computing projects, including:
    + the RC5 Challenge (http://www.rsa.com/rsalabs/97challenge/),
      specifically the Bovine Project (http://rc5.distributed.net)
    + distributed Chess
    + the Great Internet Mersenne Prime Search (GIMPS)
      (http://www.mersenne.org/)
    + searching for optimal Golomb rulers
      (http://members.aol.com/golomb20/index.html)

  and, most importantly, the V3 cross-platform open distributed networking
  protocol, being developed by the distributed.net folks.


From what I have found, it seems that Xilinx makes good chips, but I do
not know if there are commercially available PCI cards available with
these chips.  If not, I am willing to get some schematics an learn to
build a PCI card of my own.

Whatever it takes.

My operating system of choice is Linux on an x86 platform, but I can do
Windows 95 as well, if necessary.

I like what I've heard of this technology, and it blows my mind that it is
not much more commonplace.

Any and all information you can give me on where I can get this stuff, how
much this technology will cost me, how much power I can get for this cost
(I'm looking for around $500 ?), and what I can do with it -- and how I
can learn how to do what I can do with it, will be most greatly
appreciated.

________________________________________________________________________
***PGP fingerprint = D5 EB F8 E7 64 55 CF 91  C2 4F E0 4D 18 B6 7C 27***
               darxus@op.net / http://www.op.net/~darxus 
         "You shall know the truth, and it shall make you odd."

Article: 7964
Subject: Re: Anyone using Protel Schematic 3 for XILINX?
From: "Erik de Castro Lopo" <e.de.castro@fairlightesp.com.au>
Date: 4 Nov 1997 02:55:00 GMT
Links: << >>  << T >>  << A >>


Peter <z80@ds.com> wrote in article
<345c33e9.34419192@news.netcomuk.co.uk>...
> Just wonder how well this works. Xilinx sales reps don't know much
> about it.

I'm using Protel 2.4. We have got version 3 but are not happy with some of
the changes (although minor). 

As far as a way to develope for Xilinx with schematic based tools, this is 
the best I've seen. Protel 2.4 is a really well designed, intuitive tool.

Hope this helps,
Erik
Article: 7965
Subject: Re: viewlogic question
From: William White <will@fpga.demon.co.uk>
Date: Tue, 4 Nov 1997 11:35:51 +0000
Links: << >>  << T >>  << A >>
Rick

There are two approaches. The first is basically the way you expect it
to work, but instead of attaching a special NC symbol you simply attach
a dangling net to the unconnected pin and add an attribute name "NC" to
that net. No attribute value is necessary. The "NC" attribute on a
single pin net prevents the "Single net pin" warning (see the .cfg
file).

Alternatively you can add the following line to the .cfg file for the
PCB interface you are using ( There is an explanation about this at the
top of the cfg file ):

ExcludeNums 6094

This will then exclude all error/warning numbers 6094 which is the
offending warning number for unconnected pins. 

Hope this helps.

Will

In article <01bcd88f$ccd40060$6e0db780@Rich>, "Rich K." <rich.katz-
nospam@gsfc.nasa.gov> writes
>hi guys and gals,
>
>this might be a bit off topic and i hope that the net-religious-zealots
>don't get too upset.
>
>anyways,
>
>i imagine that there a lot of viewlogic users out there.  what we would
>like to do is to be able to attach something to a pin of a component (that
>is not used) which will tell the pcb netlister that the pin is
>intentionally not used and not to complain about it.  getting a billion pin
>unconnected messages is sort of useless and very time consuming to
>disposition each one - i'd rather once deliberately put on the schematic my
>intention not to use a pin - then the netlister will complain about real
>mistakes.  also, it shouldn't affect simulation nor should it appear in the
>netlist.  i know that orcad has the little 'x' you attach which does this. 
>is there a way to do this in viewlogic?
>
>currently we are adding nets to the pins and labelling them all 'nc' and
>then manually going into the netlist to remove the 'nc' net.
>
>any better ideas?
>
>thanks for the help,
> 
>------------------------------------------------------------
>rk
>"there's nothing like real data to screw up a great theory,"
>- me, modified from the slightly more colorful original
>------------------------------------------------------------

-- 
William White
Article: 7966
Subject: Vital files generated by maxplus2
From: Oliver WOOD <o.wood@mmu.ac.uk>
Date: Tue, 04 Nov 1997 15:53:22 +0000
Links: << >>  << T >>  << A >>
Has anyone found any differences between the timming values seen in the
maxplus2 (altera version 8.0) simulator and that of the *.sdo files
generated for simulation in a third party simulator.

There seems to be a difference of a factor of 2 :
eg : 10 ns in maxplus2 simulator .. becomes a 20 ns delay when
simulating using the V-system simulator.


Can anyone help


Thanks in advance

Oliver J. WOOD
Article: 7967
Subject: The Top UK Opportunities in ASIC, Systems & Hardware R&D, ECM
From: ECM Selection Ltd <vanessa@ecmcel.demon.co.uk>
Date: Tue, 4 Nov 1997 15:54:35 +0000
Links: << >>  << T >>  << A >>


        The Top UK Opportunities in ASCI, FPGA, Systems & Hardware R&D


For the pick of the UKs top Resarch & Design opportunities in
applications ranging from:

                Advanced Video Systems
                Telecommunications
                Graphics Processing
                DSP
                High Speed Networks
                Broadcast Video Systems
                Consumer Products

visit:          http://www.ecmsel.co.uk


 
For further information on ECM and to search our ONLINE VACANCY DATABASE visit
http://www.ecmsel.co.uk.

Please contact us by Email (CVs in plain ASCII text - not coded!) 
topjob@ecmsel.co.uk.

Alternatively Snail, Fax or Phone:
ECM Selection Ltd, The Maltings, Burwell, Cambridge, CB5 0HB
Phone: 01638 742244                             Fax: 01638 743066
Article: 7968
Subject: Re: Anyone using Protel Schematic 3 for XILINX?
From: arnim@atlantis.actrix.gen.nz (Arnim Littek)
Date: 4 Nov 97 19:38:34 GMT
Links: << >>  << T >>  << A >>
In article <345c33e9.34419192@news.netcomuk.co.uk>, Peter <z80@ds.com> wrote:
>Just wonder how well this works. Xilinx sales reps don't know much
>about it.

Protel has not yet discovered what hierarchy means.  Multiple instantiations
of a single library part means ridiculous workarounds.  Until that's fixed,
I won't touch it for FPGA work.

FWIW,

Arnim.

-- 
Arnim Littek                                    arnim@actrix.gen.nz
Actrix Networks Ltd.                            fax +64-4-801-5335
uucp/PPP/SLIP/BBS accounts                      tel +64-4-801-5225
Article: 7969
Subject: 64 BIT PCI bridge in FPGA?
From: Dave Blair <DBlair@phbtsus.com>
Date: Tue, 04 Nov 1997 18:27:54 -0700
Links: << >>  << T >>  << A >>
Hi, I have a requirement to build a 64 bit, 33 MHz PCI to PCI bridge
along with some additional special functions incorporated into a single
FPGA. Is this possible with any FPGA that is currently available? I know
that there are third party "mega-functions" that are available for 32
bit PCI interfaces. Has anyone done work on 64 bit versions of these? Is
it possible or practical to incorporate two if these in one FPGA?

Kind regards,
Dave Blair
---------------------------------------------------------------
| Dave Blair            Voice:  (801)977-1640
| Principal Engineer    Fax:    (801)977-1602
|                             E-Mail: mailto:DBlair@phbtsus.com
| Philips Broadcast Television Systems Company
| http://www.PhilipsBTS.com
| 2300 South Decker Lake Blvd.
| Salt Lake City, Ut. 84119
---------------------------------------------------------------


Article: 7970
Subject: Help with 64 bit 33MHz PCI bridge in singe FPGA?
From: Dave Blair <DBlair@phbtsus.com>
Date: Tue, 04 Nov 1997 18:30:39 -0700
Links: << >>  << T >>  << A >>
Hi, I have a requirement to build a 64 bit, 33 MHz PCI to PCI bridge
along with some additional special functions incorporated into a single
FPGA. Is this possible with any FPGA that is currently available? I know
that there are third party "mega-functions" that are available for 32
bit PCI interfaces. Has anyone done work on 64 bit versions of these? Is
it possible or practical to incorporate two if these in one FPGA?

Kind regards,
Dave Blair
---------------------------------------------------------------
| Dave Blair            Voice:  (801)977-1640
| Principal Engineer    Fax:    (801)977-1602
|                             E-Mail: mailto:DBlair@phbtsus.com
| Philips Broadcast Television Systems Company
| http://www.PhilipsBTS.com
| 2300 South Decker Lake Blvd.
| Salt Lake City, Ut. 84119
---------------------------------------------------------------

Article: 7971
Subject: Help with 64 bit, 33MHz PCI bridge in FPGA?
From: Dave Blair <DBlair@phbtsus.com>
Date: Tue, 04 Nov 1997 18:31:32 -0700
Links: << >>  << T >>  << A >>
Hi, I have a requirement to build a 64 bit, 33 MHz PCI to PCI bridge
along with some additional special functions incorporated into a single
FPGA. Is this possible with any FPGA that is currently available? I know
that there are third party "mega-functions" that are available for 32
bit PCI interfaces. Has anyone done work on 64 bit versions of these? Is
it possible or practical to incorporate two if these in one FPGA?

Kind regards,
Dave Blair
---------------------------------------------------------------
| Dave Blair            Voice:  (801)977-1640
| Principal Engineer    Fax:    (801)977-1602
|                             E-Mail: mailto:DBlair@phbtsus.com
| Philips Broadcast Television Systems Company
| http://www.PhilipsBTS.com
| 2300 South Decker Lake Blvd.
| Salt Lake City, Ut. 84119
---------------------------------------------------------------

Article: 7972
Subject: Help with 64 bit, 33MHz PCI bridge in FPGA?
From: Dave Blair <DBlair@phbtsus.com>
Date: Tue, 04 Nov 1997 18:33:42 -0700
Links: << >>  << T >>  << A >>
Hi, I have a requirement to build a 64 bit, 33 MHz PCI to PCI bridge
along with some additional special functions incorporated into a single
FPGA. Is this possible with any FPGA that is currently available? I know
that there are third party "mega-functions" that are available for 32
bit PCI interfaces. Has anyone done work on 64 bit versions of these? Is
it possible or practical to incorporate two if these in one FPGA?

Kind regards,
Dave Blair
---------------------------------------------------------------
| Dave Blair            Voice:  (801)977-1640
| Principal Engineer    Fax:    (801)977-1602
|                             E-Mail: mailto:DBlair@phbtsus.com
| Philips Broadcast Television Systems Company
| http://www.PhilipsBTS.com
| 2300 South Decker Lake Blvd.
| Salt Lake City, Ut. 84119
---------------------------------------------------------------

Article: 7973
Subject: Help with 64 bit, 33MHz PCI bridge in FPGA?
From: Dave Blair <DBlair@phbtsus.com>
Date: Tue, 04 Nov 1997 18:36:21 -0700
Links: << >>  << T >>  << A >>
Hi, I have a requirement to build a 64 bit, 33 MHz PCI to PCI bridge
along with some additional special functions incorporated into a single
FPGA. Is this possible with any FPGA that is currently available? I know
that there are third party "mega-functions" that are available for 32
bit PCI interfaces. Has anyone done work on 64 bit versions of these? Is
it possible or practical to incorporate two if these in one FPGA?

Kind regards,
Dave Blair
---------------------------------------------------------------
| Dave Blair            Voice:  (801)977-1640
| Principal Engineer    Fax:    (801)977-1602
|                             E-Mail: mailto:DBlair@phbtsus.com
| Philips Broadcast Television Systems Company
| http://www.PhilipsBTS.com
| 2300 South Decker Lake Blvd.
| Salt Lake City, Ut. 84119
---------------------------------------------------------------

Article: 7974
Subject: Re: Anyone using Protel Schematic 3 for XILINX?
From: "Erik de Castro Lopo" <e.de.castro@fairlightesp.com.au>
Date: 5 Nov 1997 02:39:13 GMT
Links: << >>  << T >>  << A >>


Arnim Littek <arnim@atlantis.actrix.gen.nz> wrote in article
<345f79ba.0@news.actrix.gen.nz>...
> In article <345c33e9.34419192@news.netcomuk.co.uk>, Peter <z80@ds.com>
wrote:
> >Just wonder how well this works. Xilinx sales reps don't know much
> >about it.
> 
> Protel has not yet discovered what hierarchy means.  Multiple
instantiations
> of a single library part means ridiculous workarounds.  Until that's
fixed,
> I won't touch it for FPGA work.
> 

Do you mean multiple instantiations of a single library part or a single 
sheet? I've had no problems with the former and found a rather easy (IMHO)
workaround for the second. Basically if I've got something on a sheet that
I 
would like to instantiate a number of times, I generate a library part for 
the sheet and then use the library part. This works for me.

Erik


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2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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