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Richard Schwarz wrote: > > Check at http://www.associatedpro.com/aps for some great FPGA informatioon > and deals on low cost eda software. > > Adam Seychell wrote: > > > Ok, as great as the internet is with information, I couldn't find any > > online documentation, (or PDFs) that would answer me with basic > > questions to start me off on learning about this great technology. > > > > Are FPGAs re-porgrammable ? > > > > If so is there a limit to the number programming ? > > > > Where does the word "field" come from in FPGA ? > > > > I've heard of people using programmable logic devices for building > > hardware that has the capability to be reconfigured at any time. Would > > this be FPGA ? > > Does this implementation have a name ? > > > > Obviously I am a beginner to programmable logic. Over the last few > > weeks of looking at whets around I see its a huge and growing > > industry. For some reason FPGAs seem to be most popular over other > > technologies. the antifuse technology (actel, quicklogic) can only be programmed once, the eprom based parts (lattice, amd, alterra 7000, ect..) can be reprogrammed a finite number of times based on he technology used ( however some of the reprogram in circuit), the ram based fpga by nature is reprogrammed every time power is applied, hence has the most flexibity, but conversly, the least security. bob engle embedded solutions rengle@ix.netcom.comArticle: 8051
hi pete, Peter Alfke <peter@xilinx.com> wrote in article <345CEE7E.A4D7BC52@xilinx.com>... > Richard B. Katz wrote: > > > hi pete, > > > > i think there is some significance for getting pins to line up and > > i'll add clock and other special pins to the supply pins. i have had > > feedback from customers that they like the flexibility to potentially > > expand capabilities in the future w/out having to make new boards. > > I agree. > Maybe I was addressing the wrong question. > Within Xilinx we believe very much in pin-out compatibility. Take any > package, and any XC4000 or XC5200 device available in that package has > the same pin-out. So you can start with a larger chip, then streamline > to a smaller chip, or the other way 'round, expand your design, or even > go to a cheaper family, like XC5200, all without changing your pc-board. $$$$ yup, them seem to like that capability. i can push the designs closer $$$$ to the limit of the device without having to have spare gates for $$$$ req't changes, oopses, new features, etc. keeps component costs to the $$$$ bare minimum. > > I was, perhaps erroneously, addressing the issue of different > manaufacturers second-sourcing each other's parts. > I can understand why Atmel copies the Xilinx pin-out ( it would be silly > not to do that and thus take advantage of a de facto standard), but that > does not mean that a completely different architecture can allow you to > implement a compatible design. $$$$ well, two points here. first, having identical pinouts may allow different $$$$ architectures for different products. say i'm doing a dsp board with a $$$$ standard analog interface and digitzer on one side (aka, the guzinta) and $$$$ a standard digital interface for getting the data out (aka, the goezouta). $$$$ depending on the functions desired, i might want to pick fpga's with $$$$ different architectures. now, i haven't fully exploited this yet, but, $$$$ for example, we have some plans for using a regular act 2 device as a $$$$ standard unit and with some new product features, use the DX family $$$$ with it's dual port sram. it's conceivable that i might want to use $$$$ a register rich architecture for some products (say atmel at6000) but $$$$ for some others i might want to have lots of ripple counters for binning $$$$ samples coming in and then buffer up the counts for later collection $$$$ (say a3200dx family). i guess it would be nice if as many fpga's as $$$$ possible would have their pins line up for a standard package, where $$$$ applicable. i know i appreciate being able to take virtually ANY $$$$ video card with virtually ANY capability and ram it into the same pci $$$$ slot. and i can buy the video card i want and software driver to fit $$$$ the application intended; it would be nice to do the same with fpga's. $$$$ $$$$ (not intending to start a flame war) : i didn't know that the xilinx pin $$$$ out is a "de facto standard." in my previous post i stated that it was $$$$ very interesting that the new atmel parts are not 'atmel compatible' but $$$$ are 'xilinx compatible.' what other fpga's are 'xilinx compatible' other $$$$ than second sourced parts? ok, i'm lazy and i don't have all my fpga books $$$$ here at home to go through them. :-) > > Peter Alfke, Xilinx Applications > ------------------------------------------------------------ rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) -------------------------------------------------------------Article: 8052
$$ FREE TO START - $000s PER MONTH $$ NO CHARGE TO JOIN ------------------------------------------------------------------------------------------------------------------------ If you're reading this, then you may be looking for a business that's different, and really works and that's so NEW it's only just being promoted by e-mail. You can run it entirely on line, in your spare or full time and it works anywhere throughout the world. I am very committed into earning a Great 2nd Income from a business that has been running very successfully for the past few years, until recently just by using regular mail. The business was adapted and made available to others in July 1997 by UK based Gemini Publishing International to operate purely by e-mail (although it can still be run by regular mail as well). What you will see here represents an incredible legal money making business that anyone can run from their kitchen table. You will receive full instructions - it's so easy to work even the kids could do it. Plus I'm always available to give help and answer your questions. I have been earning substantial profits from regular mail but the earnings from e-mail promotions will make this look like small change! Plus the savings on printing and postage! My present monthly income is over $5000 and growing by the week. I confidently expect my annual earnings to exceed $60,000 in my first year, purely from regular mail within the UK. Just think what this will rise to with the power of e-mail advertising on a global scale? This is a genuine home business, not a chain letter, money game, telecom scheme or any of the multitude of dubious 'business' offers that come through your emailbox. And to prove my sincerity I make NO CHARGE to join me in my business until you find your first customer - yes there is a product to sell and it's something of value to everyone, particularly newcomers, involved in any home business. If you want more information and follow my success to make it your own, reply to mop13851@mail.telepac.pt insert "SHOWME" in the subject box and put your full name and e-mail address in the message body. I will send you a file by e-mail attachment so please specify whether you want this as a plain text document (*.txt) or if you prefer it as Html (*.html) or Microsoft Word (*.doc). With my warmest greetings Vitor Manuel mop13851@mail.telepac.ptArticle: 8053
The Lighthouse of Your Guardian Angel on the Wishing Tower. Do you want all your whishes to come true ?! Do you want to be happy ?! Then light the flame of the Lighthouse of Your Guardian Angel on the Wishing Tower and all of your wishes and dreams will come true! visit it at: http://www.carigroup.com/lighthouse/Article: 8054
In article <Pine.OSF.3.96.971108145307.24746A-100000@miller.cs.uwm.edu>, "Steven(Xunhua) Wang" <xwang@cs.uwm.edu> writes... >Who has some electronic materials about the lastest development of the >Digital's Alpha AXP? > >Please give replies to my own email box. Thanks! > E-mail on my reader does not work. Post to newsgroup, get reply on newsgroup. Try www.alphapowered.com Daniel Lang dbl@hydra0.caltech.eduArticle: 8055
I would suggest looking at Symbios (formerly NCR). These folks have been great with providing info. about their parts.....In fact, I spoke with an engineer there who claimed "It was their business to spread the knowledge". The others have been nothing but trouble for me. Good Luck, Bruce PirgerArticle: 8056
--------------E287F9C7D227E88E8F4C14E1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, does anyone has experience in using the xilinx PCI LogiCORE within the xilinx xc4kE family? I intend to build up a board with a PCI slave interface. One idea is to integrate the PCI- compilant core (module) with the user application in one large FPGA. Yet the back-end (application) itself is a high demanding design with a critical timing. I personally have doubts that the timing requirements of both of the parts (PCI module and user application) can be met when implementing this in one xilinx FPGA. The question remains weather this is a practical solution or not? Thanks for your advices. Norbert. -- --------------------------------------------------------------------- Norbert Kroth GMD FOKUS Kaiserin-Augusta-Allee 31 D-10589 Berlin Tel. FOKUS : +49-30-3463-7195 E-Mail : kroth@fokus.gmd.de WWW : www.fokus.gmd.de/usr/kroth --------------------------------------------------------------------- --------------E287F9C7D227E88E8F4C14E1 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> Hi, <P>does anyone has experience in using the xilinx PCI LogiCORE within the xilinx xc4kE <BR>family? <P>I intend to build up a board with a PCI slave interface. One idea is to integrate the PCI- <BR>compilant core (module) with the user application in one large FPGA. Yet the back-end <BR>(application) itself is a high demanding design with a critical timing. <P>I personally have doubts that the timing requirements of both of the parts (PCI module <BR>and user application) can be met when implementing this in one xilinx FPGA. The question <BR>remains weather this is a practical solution or not? <P>Thanks for your advices. <P>Norbert. <PRE>-- --------------------------------------------------------------------- Norbert Kroth GMD FOKUS Kaiserin-Augusta-Allee 31 D-10589 Berlin Tel. FOKUS : +49-30-3463-7195 E-Mail : kroth@fokus.gmd.de WWW : www.fokus.gmd.de/usr/kroth ---------------------------------------------------------------------</PRE> </HTML> --------------E287F9C7D227E88E8F4C14E1--Article: 8057
Hi! For a seminar I have chosen the topic "Runtime Configurable FPGAs". I've found some articels on the web but there's still some information that some of you might be able to answer or provide me with a pointer to where I can find some documents. 1) Are there any commersial available FPGAs, except Atmel and Xilinx, which are runtime configurable? 2) Are there any design tools that support simulation, synthesis, map, place and route of runtime configurable FPGAs? 3) Is it possible to use VHDL or Verilog to describe a runtime configurable design for both simulation and synthesis? Thanks! Jonas Thor i93-jtr@sm.luth.seArticle: 8058
Most of the time while using the M1 software for Xilinx (viewdraw, epic, etc..) I get the message : "Dr Watson : application error " followed by "not enough storage to complete this operation". Anyone having similar problems ? The platform I'm using : PentiumII, NT4.0 Setting the registry higher didn't seem to solve the problem. Anyone a solution ? Tnx in advance !Article: 8059
Hello,
Some time ago somebody mentioned that the default eprom output
of Maxplus2 (ed 8.11) is not any more for the EPC1. Unfortunately
I have lost that info.
I think Maxplus2 now generates by default output for the EPC1441.
Can anyone tell me how I make MaxPlus2 use EPC1 as default, or
what I have to do to generate outputs for the EPC1 ?
Thanks
--
Koenraad SCHELFHOUT
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VH14 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 47 \ / /
mailto:ksch@sh.bel.alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
Article: 8060
Help me !
I will convert a bitfile to a user-readable ASCII without use the
Makebits. How do you make?
Thank you for you help.
Laurent Gauch
\\://
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Laurent Gauch
Ecole d'Ingenieurs du Valais (EIV)
Route du Rawyl 47
CH - 1950 Sion
tel:++41 27 / 32 43 363
fax:++41 27 / 32 43 315
E-mail: laurent.gauch@eiv.vsnet.ch
http://www.vsnet.ch:80/eiv/electro/micro/
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Article: 8061Thanks for the suggestions, Steve. Your suggestion of looking into the Linux code for data on the host adapter might well be effective. The time required could streach out a bit, though. Several people here suggested looking into the Symbios.com web site for info on their SCSI chips. That appears to be a good possibility. Unfortunantly, the internet service provider I'm using has trouble with Symbios' available commands and can't download their PDF files. The simpliest solution has been to make a host adapter from scratch. Since a simple polling interface is all the application requires, for now anyway, this looks like the quickest path. - Hul In article <EJB0yA.CDD@iglou.com>, Hul Tytus <htytus@iglou1.iglou.com> writes > > Anyone know of a SCSI-1 host adapter for the PC ISA buss for which a >listing of the control & data ports and their functions is available? This >would seem a simple quest but the opposite appears true. I too had difficulty finding information on SCSI adaptors. I had a look at the Linux source listings which do contain the kind of information you need but are not really structured in a way that makes it easy to get at. Maybe you could see if the Adaptec 1505 or 1510 have drivers within Linux. In the end I used the ASPI interface as my unit ran under DOS and that has helped with multi sourcing 'cos every adaptor you can buy has an ASPI driver. Whether its an appropriate copurse for you is obviously another matter. Good luck anyway and I'd be interested in anything you did find. Regards --Article: 8062
IUF International Users' Forum (VIUF)
Fall 1998
CALL FOR TOPICS
"Idea Factory: VHDL for Power Users"
Over the past ten years, the EDA Industry has seen VHDL and some of
its satellite standards evolve from infancy to maturity. The VHDL
International Users' Forum (VIUF) has contributed significantly toward
the introduction of VHDL and its companion standards to the user
community. However, feedback from users has indicated that VIUF must
do more to address the needs of the "experienced" user. In light of
this, the Steering Committee for VIUF Fall 1998 has chosen to devote
the majority of its focus to the needs of experienced users and the
practical, real-world applications of VHDL. (Of course, we promise
not to forget the novice user in our plans, so don't worry if you're
just getting started using VHDL.)
The format of the Fall Forum is also changing, i.e., in addition to
providing a forum for instruction and presentation of the latest
information available concerning the practical application of VHDL,
the Steering Committee is working on a format for VIUF Fall 1998 that
will promote information interchange among the attendees. We also
hope to offer you more, in a tangible sense, than just a copy fo the
"Proceedings" to take home with you. However, in order to better meet
your needs, we need your help. In short, we need to know which topics
related to VHDL and its companion standards are of the greatest
interest to you.
The VIUF Fall 1998 Steering Committee invites you to submit one or
more topics that are of interest to you and/or your colleagues.
Please send your suggestions to the Program Chair, Peter Ashenden, via
electronic mail to:
petera@ececs.uc.edu
or by regular mail to:
Peter Ashenden
Dept ECECS, PO Box 210030
University of Cincinnati
Cincinnati, OH 45221-0030
USA
Phone: (513) 556 4756
Fax: (513) 556 7326
Submit your suggestions by no later than December 1, 1997.
Subsequent to receiving your suggestions, the official "Call for
Participation" will be distributed later this year. This is your
forum, so please assist us in serving you better by offering your
suggestions. Thanks in advance for your help.
Article: 8063I am trying to download the MAX7000S via the JTAG port, but I cannot get the correct downloading file with MAX PLUS 2. What is the correct binary file to send down: .jed, .hex file or what? and how do I get it? thank youArticle: 8064
asdArticle: 8065
I donr know In article <64fg1v$rs$1@news3.mr.net>, KarlS@ontrack.com says... > >I am trying to download the MAX7000S via the JTAG port, but I cannot get >the correct downloading file with MAX PLUS 2. What is the correct >binary file to send down: .jed, .hex file or what? and how do I get it? > >thank you >Article: 8066
I have programmed a Altera Flash FX780 by the JTAG port before, and I am trying to do the same with the MAX7000S EPM7128. Does anyone know how to get the files from MAX PLUS 2 into the correct binary form to send to the JTAG ports??Article: 8067
Austin Franklin <dark9room@ix.netcom.com> wrote in article <01bcec67$874628c0$59625ecf@drt1>... > Hul Tytus <htytus@iglou1.iglou.com> wrote in article > <EJB0yA.CDD@iglou.com>... > > > > Anyone know of a SCSI-1 host adapter for the PC ISA buss for which a > > listing of the control & data ports and their functions is available? > This > > would seem a simple quest but the opposite appears true. > > Adaptec & Data Technology won't disclose details. Must be others who > > will, though - if you know of a source for a simple 8/8 bit (polling only > is > > fine) adapter (with a listing of the ports) in single units, do let me > know. > > I'd sure hate to spend 3 or 4 days wrapping a few 20v8's together for > > this! > > Go to the Adaptec web site (www.adaptec.com) and poke around a bit. > > The 7880 is their PCI based SCSI chip: > > http://www.adaptec.com/scsichip/d_sheets/980236-011.html > > But you have to call them to get a data sheet, I don't believe one is > available on line. > > Austin Franklin > darkroom@ix.netcom.com Duh, I just realized you asked for SCSI-I/ISA....sorry about that.. I have a SCSI-I adapter from Rancho Technologies. It is the RT1000. The Rancho board uses an NCR 53C400. They have a web site, http://www.rancho.com/. If you call them (1-909-987-3966), I'm sure they have some of these cards still around, and would probably be able to give you a chip spec for the NCR 53C400... It seems that the NCR SCSI chips are now done by Symbios. The appear to have a new(er) version of that chip, the SYM53C416 and it is on an ISA card, SYM20402. Claims to be OEM only though. Good Luck! Austin Franklin darkroom@ix.netcom.comArticle: 8068
Norbert Kroth <nok@fokus.gmd.de> wrote in article <3469D27F.28B384B9@fokus.gmd.de>... > Hi, > > does anyone has experience in using the xilinx PCI LogiCORE within the > xilinx xc4kE > family? > > I intend to build up a board with a PCI slave interface. One idea is to > integrate the PCI- > compilant core (module) with the user application in one large FPGA. Yet > the back-end > (application) itself is a high demanding design with a critical timing. I have used both the LogiCore module and one of my own design in 6 PCI FPGA implementations I have done. A simple, non burst target easily fits in a 4013 with about 80% of the resources available for your back end. It will also fit into a 4005/6 if you use the feature of the horizontal long lines that allows them to be split in two. You put 16 bits in each half of the chip. That takes up about %60 of the chip. Remember, the larger the chip, the slower the chip.....because there 'can be' more distance between resources. The horizontal long lines and global buffers are longer, and therefore slower. What is the speed of your back end? > I personally have doubts that the timing requirements of both of the > parts (PCI module > and user application) can be met when implementing this in one xilinx > FPGA. The question > remains weather this is a practical solution or not? PCI timing can be critical, but for a Target only application, is easily done if you use very good logic design and floorplanning. Not knowing how fast your back end has to be, I can't speculate on it. Austin Franklin darkroom@ix.netcom.comArticle: 8069
Hi people, I'm looking for dynamically reprogrammable FPGA's, like the Xilinx XC6200 series. I need to be able to manipulate individual cells and routing during run-time. Also, I'm looking to maximise the number of I/O pins. Is the XC6200 the only viable option for me? Thanks, Mark Remove nospam in email replies -- Mark de Wit University of Glasgow Computing Science Department dew@nospam.dcs.gla.ac.uk http://www.dcs.gla.ac.uk/~dew Office phone: +44-(0)141-339 8855 ext. 8479 Wally: "stupidity is like nuclear power; it can be used for good or evil" Dilbert: "And you don't want to get any on you"Article: 8070
Do anyone know the moehod of Digital PLL?Article: 8071
Mark de Wit wrote: > > Hi people, > > I'm looking for dynamically reprogrammable FPGA's, like the Xilinx XC6200 > series. I need to be able to manipulate individual cells and routing > during run-time. Also, I'm looking to maximise the number of I/O pins. Is > the XC6200 the only viable option for me? > > Thanks, > Mark, The Atmel 6K and the new Atmel 40K devices also support partial reconfiguration (ie the logic on part of the device can be changed while the rest of the logic is still functioning). The 6K is a design dating back to the late 80's, but still holds its own in certain applications. It is a fine grain architecture (each cell is basically a half adder with a flip flp on the sum output and some extra gating to get other 2 and 3 input functions) The 40K improves on the 6K by providing more functionality to each cell and vastly improving the route resources. The 40K is being billed as cheap too. I've been playing a little with the design software for the 40K...looks like a pretty nice chip, esp for heavy computational type stuff. The fine grain makes it fast too. The 6K, being the pioneer in the partial reconfig thing, has a few foibles that can make things interesting (and smokey) if you are not careful in the configuration. Both the XC6200 and the AT40K devices incorporate safeguards to prevent illegal and potentially damaging configurations. National Semi also has a variant of the AT6K called the CLAy family that is partially reconfigurable (both the NSC and Atmel are descendants of the Concurrent Logic device). National is rumoured to be working on a next generation too...they presented some overviews last spring at FCCM. I wouldn't hold you breath for commercial availability on the NSC stuff yet, but if you're in research programs you might be able to get in the ground floor for some really neat stuff. Person to contact there is Tim Garverick, garv@berlioz.nsc.com. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 8072
I`m looking for a State Machine basics material in Internet. Could you help me, please? -- Victor Levandovsky Technological University of Podolia Khmelnitsky, UkraineArticle: 8073
cephas@mail.ttn.com.tw (Cephas Lin) wrote: >Do anyone know the moehod of Digital PLL? > Assuming you're more interested in a digital implimentation methodology. . . One way to construct a PLL is to use an accumulator to accumulate phase -phase error/n. As an example, suppose you have a reference clock edge coming every 16 micro seconds. You could add 1/16 of the overflow value of your accumulator, to the accumulator every microsecond. This would make your accumulator overflow and wrap around every 16 micro seconds. Now you sample the phase of the accumulator every time your reverence edge arrives and hold the result in a register. If there were no phase error your register would contain all zeros. If the phase of the accumulator is late, your register will have a positive value, and if your accumulator is early, your accumulator will have a negative value. Divide the error value by some amount, say 256 by shifting the bits to the right, 8. Subtract from the 1/16 overflow value, before adding to the accumulator. Now your accumulator will tend to reduce its phase error by 1/256th, of the error value, 16 times each cycle. If your reverence pulses are sometimes missing, such as is the case with data edges, you may need to zero the error register after a fixed number of accumulator clock cycles, say 15, so that one phase error measurement doesn't exert too much correction, just because the next reverence edge is a long time coming. If you need your error to go to zero, in the face of large frequency offsets, you may want to integrate (accumulate) the error values, and also feed back some portion of that value. I hope this shows you how to construct a simple PLL. Naturally, you will have to adapt to your individual case. Cheers, Dave Decker Diablo Research Co. LLC ddecker@diabloresearch.com Dave Decker Diablo Research Co. LLC Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 8074
Hi all! We are currently planning to do an FPGA design that is loaded with registers to all of which a processer would need read and possibly write access. We therefore came up with the idea of using a reconfigurable device with a memory-like CPU interface (like the XC6200) since it would provide us for free with all the datapaths to access the registers. Using a regular FPGA, it seems that we would just waste too much space for the "little functionality" of accessing the registers. Is this reasoning correct or are there regular (non- reconfigurable, that is) FPGA families that are better suited to this kind of design with maybe a higher density? Related to this, if we were going to use reconfigurable devices, does anyone know of a good and seamless VHDL design flow for them? The problem here is, for simulation you'd need a model of the internal datapaths of the FPGA (those used for reconfiguration), and the synthesis tool would have to be able to interface to them in a way that would make it possible to signal external read/write accesses to the internal synthesized logic. Overall, the question is: What's better, using a regular highest-density FPGA and designing the datapaths on your own (with a proven design flow), or using a reconfigurable device with given datapaths (and possibly a dubious design flow)? Appreciating your help Markus -- ----------------------------------------------------------------------- Markus Leberecht, Ph.D. student, TU Muenchen, Germany ##### ##### www : http://wwwbode.informatik.tu-muenchen.de/~leberech/ # # # # # phone: +49-89-289-25357 fax: +49-89-289-28232 # #### # #
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