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Messages from 8425

Article: 8425
Subject: Re: RC5-64 on FPGA
From: doug@netcom.com (Doug Merritt)
Date: Sat, 13 Dec 1997 23:41:49 GMT
Links: << >>  << T >>  << A >>
In article <Pine.GUL.3.95.971212130608.1533A-100000@po.EECS.Berkeley.EDU> Eyal Soha <barrel@po.EECS.Berkeley.EDU> writes:
>Furthermore, I've received at least two emails from people looking at my
>design that claim switching to bit-serial processing would allow me to
>full pipeline my design such that 12 boards would double the entire
>throughput of the project (which currently stands at around the power of
>14,000 Pentium Pro/200s).

I said that, but I meant it as a (unlikely) upper bound if one managed an
effective 1ns clock speed, and managed by hook-or-by-crook to pipeline
and parallelize everything so as to crank out one result per clock.
That would be ideal, and hence is the thing to shoot for -- but I'd
never say flat out that it's possible, merely a good goal. :-)

A 300 Mhz Pentium II with SDRAM manages not quite 1 million results per
second, so that scenario would indeed hypothetically have 12 boards
(12 giga results/sec) equal to 12-16,000 Pentiums. I was a bit over-
enthusiastic at the thought of that.

But even at 10-100 million results per second, you'd have a nice fast board.
	Doug
-- 
Doug Merritt				doug@netcom.com
Professional Wild-eyed Visionary	Member, Crusaders for a Better Tomorrow
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Article: 8426
Subject: Re: what is metastability time of a flip_flop
From: John Woodgate <jmw@jmwa.demon.co.uk>
Date: Sun, 14 Dec 1997 07:21:09 +0000
Links: << >>  << T >>  << A >>
In article <34931A20.44247290@CatenaryScientific.com>, Chuck Parsons
<chuck@CatenaryScientific.com> writes
>
>
>John Woodgate wrote:
>
>> I won't argue with your reasoning: questions of probability often have
>> counter-intuitive answers. However, looking at the subject another way,
>> the resistor/integrator device seems to be able to extract noise energy,
>> and that means thermal energy, from the resistor and store a net amount
>> of it in the capacitor. What happens then to the temperature of the
>> resistor? What is wrong with this crazy result?
>
>  Well lets not get sidetracked on that. John, I think you may be trying to 
>exhaust
>me ;-)
No, Im not. But I'm quite willing to abandon this thread. IT seems to
have become just a 2-way discussion.
-- 
Regards, John Woodgate, Phone +44 (0)1268 747839 Fax +44 (0)1268 777124. 
OOO - Own Opinions Only. It is useless to threaten a strong man - he will
ignore you. It is dangerous to threaten a weak man - he will kill you if he can.

Article: 8427
Subject: Re: bus design in Altera 10K, how to increase speed
From: songsong <ss@zjumail.ml.org>
Date: Sun, 14 Dec 1997 16:13:04 +0800
Links: << >>  << T >>  << A >>
muzo wrote:
> 
> hi,
> I have a design which uses %55 of a 10K100 and within this design I have 12 8 bit
> registers which need to be selectively loaded into another register, IOW, I have
> an 8 bit bus from which 12 8 bit registers hang. Because 10K doesn't have
> internal tristates, I have a big mux which selects the register. Currently this
> mux is the bottleneck in my design which limits my speed to  11 MHz in a -3 part.
> Any ideas how to increase the speed in this design? The design is in Verilog.
> 
> Are there any ways to get more performance by using the floor plan tool ? I am
> already using FAST synthesis and maximum speed in the compiler options.
> 
> thanks
> 
> muzo
> 
> WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>

Hi, muzo:

I meet a similar problem, but I use 8K. My method is that you can assign
the function which should be connected to the same LAB. In your design,
you can split the 12 8 bit registers to 12 groups, mux to 12 groups, and
the destination register to 12groups. Then you can use floorplan to drag
the same group to the LAB as near as possibly.

Regards.

Ss.
Article: 8428
Subject: Re: bus design in Altera 10K, how to increase speed
From: alex.koegel@dspis.co.il (Alex Koegel)
Date: 14 Dec 1997 14:58:21 GMT
Links: << >>  << T >>  << A >>
In article <3491bc91.80619134@news.walltech.com>,
   muzok@pacbell.net (muzo) wrote:
>hi,
>I have a design which uses %55 of a 10K100 and within this design I have 12 8 
bit
>registers which need to be selectively loaded into another register, IOW, I 
have
>an 8 bit bus from which 12 8 bit registers hang. Because 10K doesn't have
>internal tristates, I have a big mux which selects the register. Currently 
this
>mux is the bottleneck in my design which limits my speed to  11 MHz in a -3 
part.
>Any ideas how to increase the speed in this design? The design is in Verilog.
>
>Are there any ways to get more performance by using the floor plan tool ? I 
am
>already using FAST synthesis and maximum speed in the compiler options.
>
>thanks
>
>muzo
>
>WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>

Most probably your Flex10K100 device has sufficient pins (12x8=96) to create
an EXTERNAL tri-state bus, provided that your board isn't laid-out yet, and
that you have sufficient (internal) OE to control the 12 tri-state selection
lines. In case the device doesn't support 12 OEs, you may consider having a
16-bit wide tristate bus with a 2x8 -> 1x8 mux at the receiving side, and
implementing only 6 OEs.

Another option is to use an internal EAB as a 12 x 8-bit wide internal RAM.

Alex Koegel
DSPC Inc.
Article: 8429
Subject: Re: combinational multipliers
From: "Martin Mason" <mtmason@ix.netcom.com>
Date: Sun, 14 Dec 1997 11:04:08 -0800
Links: << >>  << T >>  << A >>


Carmen Baena Oliva wrote in article <348E7CE1.EF786F5B@cnm.us.es>...

>I'm trying to obtain a combinational multiplier using a Xilinx FPGA.
>Can anybody give me some references about good structures for the
>multiplier?
>
>Thanks in advance.
>Carmen
>
Carmen,
    For the fastest - most efficient array multipliers check out the DSP
optimised AT40K architecture.  http://www.atmel.com


Martin Mason



Article: 8430
Subject: Re: dynamic power in Xilinx designs
From: "Erik de Castro Lopo" <e.de.castro@fairlightesp.com.au>
Date: 14 Dec 1997 21:56:19 GMT
Links: << >>  << T >>  << A >>


G. Herrmannsfeldt <gah@u.washington.edu> wrote in article
<66shkq$16uc$1@nntp6.u.washington.edu>...
> I am working on a design for an XC4013 with 30 16bit adders, plus
> lots of latches, in an XC4013.  It should be able to go up to about
> 30MHz with the 4013-2, but I am wondering about the dynamic power.
> If on the average a signal changes every other clock cycle, 
> how much power should I expect out of this?
> 
> I don't want a big heatsink and fan for each chip!
> 
> I tried to find this in "the programmable logic data book," but
> I didn't find it.  I only need rough numbers right now, but I don't
> even have that,

There's an application note covering the estimation of dynamic power
on Xilinx's web site. Go to the XC4000 series page and it should be 
down the bottom somewhere. 

Hope this helps,
Erik
Article: 8431
Subject: Re: combinational multipliers
From: Peter Alfke <peter@xilinx.com>
Date: Sun, 14 Dec 1997 14:46:40 -0800
Links: << >>  << T >>  << A >>
I sent Carmen the following reply, but got no answer:

Carmen, here are some questions:

What array size?
What speed is required?
Can you pipeline ?
Are both factors variables, or is one of them a constant? ( Makes a huge

difference)
Positive or 2-s complement numbers?

If you e-mail me that info, I can point you to a good solution.

Peter Alfke, Xilinx

Article: 8432
Subject: Re: JTAG configuration of Xilinx XC4000E FPGAs?
From: daveb@iinet.net.au (David R Brooks)
Date: Sun, 14 Dec 1997 23:13:00 GMT
Links: << >>  << T >>  << A >>
"Peter Fenn" <PeteFenn@iafrica.com> wrote:

:JTAG configuration of Xilinx XC4000E FPGAs?
:
:Urgent! I need to do JTAG configuration of a single FPGA (Xilinx XC4013E).
:Can anyone advise/supply 3rd-party software to do this?
:
:Xilinx documentation details that it's indeed possible to configure a XC4000
:FPGA via its JTAG interface, but Xilinx does not extend their Xchecker
:software to support of this. Any suggestions ?
:
There's a design (and software) to do this for a XC4005, on my
website. URL below, then the "Free Stuff" pointer.
 Should work on the XC4KE also.


--  Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34
 What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 8433
Subject: Re: Xilinx Configuration Problem
From: Peter Alfke <peter@xilinx.com>
Date: Sun, 14 Dec 1997 15:53:41 -0800
Links: << >>  << T >>  << A >>
Acromag Web Surfer wrote:

> After a number of customer complaints reporting product malfunctions,
> we
> investigated and learned that the Xilinx FPGA will not reliable
> configure
> on power up if the power supply has a slower then 4ms (typically) rise
> time
> from 3 volts to 4.75 volts.

Please send me more details, because there is no real requirement that
Vcc should rise that fast. In a daisy-chain of several FPGAs there is a
requirement that the master not get ahead of the slaves, which is most
easily achieved by interconnecting the INIT lines. Without that
interconnection, it is most effective to have a fast Vcc risetime at
least a monotonic one.Using the active Low INIT also as the active Low
RESET ( I must assume you picked that polarity, and you used Xilinx 
SPROMs, ) is the proper way to control configuration.

There is no combined SPROM and watchdog-timer device. The technological
requirements are vey different for these two functions, and both
functions are under price- and performance pressure. It is very unlikely
that they will ever be combined.

Send me details and I promise a fast response, and I can almost
guarantee a solution.
Most configuration problems are lurking elsewhere on the pc board.

Peter Alfke, Xilinx Applications
 
 
 
 
 

Article: 8434
Subject: Re: dynamic power in Xilinx designs
From: Peter Alfke <peter@xilinx.com>
Date: Sun, 14 Dec 1997 16:07:06 -0800
Links: << >>  << T >>  << A >>
 

> G. Herrmannsfeldt <gah@u.washington.edu> wrote in article
> <66shkq$16uc$1@nntp6.u.washington.edu>...

 

> > I am working on a design for an XC4013 with 30 16bit adders, plus
> > lots of latches, in an XC4013.  It should be able to go up to about
> > 30MHz with the 4013-2, but I am wondering about the dynamic power.
> > If on the average a signal changes every other clock cycle,
> > how much power should I expect out of this?
> >
>
> > I tried to find this in "the programmable logic data book," but
> > I didn't find it.

Look at page 13-12

It gives you the power consumption in mW per million transitions of:

CLBs with minimal or maximal routing,
Outputs
Longlines and
Clocks.

The values for clock power are extremely ( ridiculously, and it's my
fault !) worst-worst-case, assuming that 100% of all on-chip flip-flops
are connected to that clock, which rarely is the case. As a first
approximation, derate the clock power by the relative number of
flip-flops connected to that clock.

You mention latches, I hope you mean flip-flops, since latches are
painful to implement and cause terrible simulation problems.

Once you have  a feel for the power, look up the thermal impedance
values for different packages and different airflows ( page 10-8 ), and
I am sure that you don't need a fancy heatsink.
By the way, XC4013XL at 3.3 V consumes only half the power, and is
faster.

Peter Alfke, Xilinx Applications
 
 

Article: 8435
Subject: Re: combinational multipliers
From: Bill Lenihan <lenihan3we@earthlink.net>
Date: Sun, 14 Dec 1997 16:32:23 -0800
Links: << >>  << T >>  << A >>
If you really need an array multiplier, look into the Baugh-Wooley
architecture. It is a good fit with the type of adders that Xilinx has
built-in to the columns of their FPGAs.


Carmen Baena Oliva wrote:

> I'm trying to obtain a combinational multiplier using a Xilinx FPGA.
> Can anybody give me some references about good structures for the
> multiplier?
>
> Thanks in advance.
> Carmen



--
=====================================================================
William Lenihan                            lenihan3we@earthlink.net

    "The greatest barrier to communication is the delusion that
     it has already occurred."       -- Peter Cummings
=====================================================================


Article: 8436
Subject: ' MA-Boston ASIC/FPGA FULL RELO provided to qualified candidates.
From: evanst@sourcesvc.com
Date: Sun, 14 Dec 1997 20:47:34 -0700
Links: << >>  << T >>  << A >>
MA-Boston metro area - several companies including 2 startups (stock/equity incl.)

********FULL RELOCATION provided to qualified candidates!***********
COMPANIES WILL MAKE IT WORTH YOUR WHILE TO CONSIDER RELOCATION IF QUALIFIED!

(see details below - apply at bottom of page....)


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****METHODOLOGY DESIGN ENGINEER -ASIC DESIGN TOOLS
****COMMS ASIC/BOARD LEVEL DESIGN PROJ LEAD/MGR
****JUNIOR AND SENIOR COMMS ASIC HARDWARE ENGINEERS (x3)
****ASIC/CHIPSET/BOARD-LEVEL HARDWARE ENGINEER
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Most of the following skills are key to these positions:

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Synopsys, Mentor, Cadence, HPEEsof, VHDL, C/C++, event driven and cycle based simulation, floorplanning, test insertion and ATPG, hardware modeling, ASIC emulation, Spice, harmonic balance, high frequency structure simulation.
     
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Job Description: 
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Prefer:
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Article: 8437
Subject: WANTED: Electronics Company with Space Experience
From: "Sven Muencheberg" <ms@removethis.kayser-threde.de>
Date: 15 Dec 1997 08:55:59 GMT
Links: << >>  << T >>  << A >>
Hello,

my company is looking for a sub-contractor in an upcoming project. What we
are looking for is a electronics company with experience in space projects,
which can design several boards for a signal processing device on a
satellite.

The company should be experienced in the following subjects:
- Design of memory boards and extensions
- FPGA design
- Actel parts
- Dealing with requirements for space missions (reliability, environment of
launch and orbit, etc.)

The company should preferably be located in Europe.

Please mail me, if you know a company that fits our requirements.

Regards,
Sven Muencheberg
 __  __   --------------------------------------------------------
|  |/  /  Kayser-Threde GmbH  		   ms@kayser-threde.de               
| ====<   Wolfratshauser Str. 48           Tel.: +49 89/724 95-121
|__|\__\  81379 Munich, Germany            Fax:  +49 89/724 95-104


Article: 8438
Subject: Re: PCs vs. workstations
From: "Austin Franklin" <dark7room@ix.netcom.com>
Date: 15 Dec 1997 14:09:20 GMT
Links: << >>  << T >>  << A >>


Bill Lenihan <lenihan3we@earthlink.net> wrote in article
<348CE6E4.76124EF@earthlink.net>...
> Does anyone know of any cases, benchmarks, studies, etc., demonstrating
> where the envelope is for FPGA designs done on state-of-the-art PCs vs.
> state-of-the-art workstations? Has anyone had a case where a design
> couldn't compile on a PC, but could when ported to a workstation? (or
> vice-versa?)
> 
> Example: At time "A", Xilinx will strongly recommend that customers
> design their biggest chips on workstations, not PCs. Yet, at time "A + 1
> year" they give an official sanction that these chips can be designed on
> PCs of X-memory, Y-hard disk space, and Z-CPU speed ...... but PCs with
> XYZ specs were not extraordinary at time "A". Do FPGA companies just get
> skittish with the PC and lean toward the conservative workstation when
> it comes to their newer (and untested in the arena of real designs)
> FPGAs? Is there much, or any, risk with sticking to a total-PC design
> flow, even when using premium FPGAs?

Bill,

For me it has always been a matter of tools.  The PC tools were always more
mature, and out first.  Bug fixes were faster.... etc.  At least this has
been true for Xilinx and Viewlogic..

Austin Franklin
darkroom@ix.netcom.com

Article: 8439
Subject: parallel counters: which device is suitable?
From: Michael.Schumacher@pamas.de (Michael Schumacher)
Date: Mon, 15 Dec 1997 16:59:55 GMT
Links: << >>  << T >>  << A >>
Sorry the first posting was uncomplete!

Hi everybody, we are currently thinking about a project where we need
at least 16 24bit counters in one device? These counters (approx 2MHz)
have to be latched syncronously (?)  to registers. These registers
must be accessed from a microcontroller bus (C167). 
Unfortunatly, this will be our first project with FPGAs, so we would
appreciate some help. The most important step seems to be the choice
for a certain device. After looking into some data books I recognized
that you have to read every page of the description to make sure not
to choose a device that will be unsuitable for the purpose. I discoved
the FLEX 8000 family that seems to have most required features. Is
there anything I have missed in the description of the device? Is
there a better device on the market? Any help appreciated 

best regards, Michael

not THAT one :-)

This is posted from my company account 
Article: 8440
Subject: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
From: "Richard Iachetta" <iachetta@us.ibm.com>
Date: 15 Dec 1997 17:24:31 GMT
Links: << >>  << T >>  << A >>
Stuart Clubb <s_clubb@die.spammer.netcomuk.co.uk> wrote in article
<3492956b.24349988@nntp.netcruiser>...
> On Fri, 12 Dec 1997 22:43:10 GMT, muzok@pacbell.net (muzo) wrote:
> 
> >I have a design which uses %55 of a 10K100 and within this design I have
12 8 bit
> >registers which need to be selectively loaded into another register,
IOW, I have
> >an 8 bit bus from which 12 8 bit registers hang. Because 10K doesn't
have
> >internal tristates, I have a big mux which selects the register.
Currently this
> >mux is the bottleneck in my design which limits my speed to  11 MHz in a
-3 part.
> 
> What speed do you need?
> 
> >Any ideas how to increase the speed in this design? The design is in
Verilog.
> 
> So am I right in saying that a 12 to 1 multiplexer, register to
> register (hence, including routing) takes 90 ns? As Altera claims a 16
> to 1 mux takes 9.4 ns in a -3 speed grade there are three
> possibilities:
> 1
> You need a new synthesis tool (which are you using?)
> 2
> There's more than the mux in your critical path. (how many layers of
> logic and routing in the path?)
> 3
> Altera isn't up to it, has a "printing error" in it's data sheets, and
> you need a different FPGA.
> 
> 1 & 2 seem more probable.
> 
> Stuart
> --
> For Email remove "die.spammer." from the address

Hi all,  My intent is not to start an Altera vs. Xilinx war but my
experience is similar to the original poster so I think its worth posting. 
I hope you will find it professional and informative.  First let me say
that if you are getting 11MHz, then there is likely more than one problem
and you can probably improve the design at the HDL and layout level (also
check fanout) to get the speed up.  That said, I had real trouble getting
the Altera 10K100 to operate at the speed I needed it (50MHz).  I had been
told by Altera that 66MHz would be possible but after working with the part
for a while, we had to back off our expectations to 50MHz.  After weeks of
working closely with a very knowledgeable Altera FAE, we could not get the
part to run beyond 40 to 42 MHz.  We made many modifications and kept all
the logic levels to 3 or less.  After a while, it sunk in that the 10K100
architecture is just not up to the task.  The main problem is that the row
to row delay is FAR too prohibative.  You can work all you want to
partition the design so as to minimize the row to row communication, but in
a large design (why else would you use a 10K100), the rows can never be
totally independent.  If you're going to burn 10 to 15 ns just to go from
one row to another, then you're dead.  You can't even have one level of
logic if the level is on a different row from one of the inputs and the
output.  I actually had "latch to latch" delays (from input latch to latch
in another row) be greater than 20 ns!  This is so incredible from a part
that is touted as being 66MHz capable, I'll say it again -- I had latch to
latch (no logic in between) delays greater than 20 ns (almost 25 ns).  And
I'm not talking about going ALL the way across the part.  Another problem
-- the input setup, clock to out and output enable times of a 10K100 I/O
block are bad enough so that 2 10K100 could not communicate with each other
at 50MHz and meet setup and hold times.  To make a long story short, I
switched to a Xilinx 4085 -1 and the existing VHDL ran at 50MHz no problem.
 Another advantage that the 4085 has over the 10K100 is you can use both an
I/O Block Input and Output latch for a bi-di signal.  Altera only has one
latch in the IOB so you can either latch the input or the output, but not
both (in the IOB).  Another advantage if you use the on chip RAM, is that
Xilinx ram is dual ported and the Altera ram is not so you can't build a
fifo using Altera ram if you need to be able to read and write the fifo on
the same clock.  Since making the switch to the 4085, I've added much logic
(so much that the design probably would not fit in a 10K100 anymore) and
the part still runs at 50 MHz.  My opinion is that the 10K100 is ok for
33MHz type designs -- maybe 40 MHz if you work very hard.  Beyond that, use
Xilinx.  Of course, you get what you pay for -- the 4085 is more expensive
than the 10K100.

-- 
Rich Iachetta
IBM Corporation
iachetta@us.ibm.com
Article: 8441
Subject: Re: MTBF Calculation. Looking for articles on the subject
From: mjohnson@netcom13.netcom.com (Mark Johnson)
Date: Mon, 15 Dec 1997 17:51:55 GMT
Links: << >>  << T >>  << A >>
  >
  > After reading almost 95% of the mails on the MTBF,
  > i know everything but could not find a good article
  > of how to simulate a FF and extract the MTBF out of it. 
  >

There are actually THREE problems:

  (1) Figuring out what *your* reliability goals
      really are. Unlike what appears in this
      newsgroup, your goals are very likely
      going to include an aggregate probability
      of failure of a large number of flipflops,
      not P(fail) of a single flipflop.
      Something like:

         Our beloved customer American Airlines
         has a room containing 500 systems, and
         each system contains 32 of our chips,
         and each of our chips contains one
         flipflop that could go metastable.
         What is the required MTBF of each individual
         flipflop, to guarantee that there is a
         probability of > 75% that ABSOLUTELY NONE
         of the (500*32*1) = 1600 flipflops at
         American Airlines, ever has a single
         metastability failure, within three years
         of continuous operation.


  (2) Finding the metastability parameters TAU and
      T0 of your particular flipflop, including
      parasitic resistance and capacitance effects.


  (3) Writing an equation for (Pfail,aggregate)
      in terms of TAU, T0, (the number of flipflops
      in your aggregate), (the clock frequency),
      (the data frequency), (the lifetime of
      the mission-critical system, e.g. 3 years),
      and so forth.


Item (2) is the easiest of the three.  The Ph.D. thesis
by Portmann (cited earlier on this group) shows how.
So does the IEEE J.SSC paper by Hohl.  Sorry I forget
the exact issue# and page #s, you can look it up,
there aren't too many papers by authors of that name.

  -M.J.
Article: 8442
Subject: Re: bus design in Altera 10K, how to increase speed
From: Emmanuel Monnerie <monnerie@oconee.em.slb.com>
Date: Mon, 15 Dec 1997 13:51:50 -0500
Links: << >>  << T >>  << A >>
One raw of a Flex 10k100 contains enough LCELL for a 12*8 multiplexer.
Have you tried to specify a raw for this multiplexer? You can do this
before compilation by selecting it in the graphic editor and do "assign
pin/raw/...". Select an empty raw. You can also do this after
compilation with the floor plan editor but you have at least 12*8 LCELL
to move with your mouse!
If you can put all the LCELLs of the multiplexer inside one raw, you
should be able to reach 35-40MHz with a 10K100-3.
I also recommend you to apply Daniel Lang's method.

Regards,
Emmanuel
-----------------------------
Design Engineer, Schlumberger
Article: 8443
Subject: Re: Xilinx Configuration Problem
From: z80@ds.com (Peter)
Date: Mon, 15 Dec 1997 19:25:10 GMT
Links: << >>  << T >>  << A >>

>Please send me more details, because there is no real requirement that
>Vcc should rise that fast.

The rise needs to be monotonic. This implies it must be very
noise-free.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8444
Subject: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
From: berryhill@hep.uchicago.edu (Jeff Berryhill)
Date: Mon, 15 Dec 1997 20:39:27 GMT
Links: << >>  << T >>  << A >>
In article <01bd097f$6ebe3e20$6d733509@iachetta>,
	"Richard Iachetta" <iachetta@us.ibm.com> writes:

>My opinion is that the 10K100 is ok for
>33MHz type designs -- maybe 40 MHz if you work very hard.  
>Beyond that, use
>Xilinx.  Of course, you get what you pay for 
>-- the 4085 is more expensive
>than the 10K100.
>
>-- 
>Rich Iachetta
>IBM Corporation
>iachetta@us.ibm.com

I have been programming -3 Altera FLEX10K's for the past 1 1/2 years 
or so, and I would have to say that if you're trying to do anything 
the least bit complicated 30-40 MHz is about the best you can 
expect, anything faster (especially on the higher gate count chips)
will require significant fine tuning to work.  

That said, I have found that the new (and very expensive) -2 and -1
speed grades are able to do 50 MHz applications without significant
fine tuning.  

--Jeff Berryhill
Article: 8445
Subject: Re: parallel counters: which device is suitable?
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 15 Dec 1997 13:29:49 -0800
Links: << >>  << T >>  << A >>
Michael Schumacher wrote:

> Sorry the first posting was uncomplete!
>
> Hi everybody, we are currently thinking about a project where we need
> at least 16 24bit counters in one device? These counters (approx 2MHz)
>
> have to be latched syncronously (?)  to registers. These registers
> must be accessed from a microcontroller bus (C167).
>  

 Hi, Michael,
  You obviously need a programmable device with at least 17 x 24
flip-flops, or do you need 32 x 24 flip-flops ? In either case, you need
an FPGA, since CPLDs don't have enough flip-flops.

Let's first describe a straightforward design:
The smallest member of the Xilinx XC4000 family to use for that design
is the XC4008E which has an 18x18 array of logic blocks, and each of
your counters fits into 13 of the 18 blocks per column.  So you have 30%
of the chip left over for control etc. You might also find the
horizontal Longlines convenient to collect the counter values and route
them to their destination.
The XC4010E has a 20x20 array, again with two flip-flops per block.
If you really need to store each counter individually, you need a larger
device.

The 5-V XC4005E, XC4010E, XC4013E and XC4020E also come in 3.3-V
versions called XC4005XL etc.

Now fro the more elegant or sneaky design:
Since you mentioned the very slow speed of 2 MHz, there is a way to do
the counting in the distributed RAM on the XC4000E devices, by using the
RAMs as shift registers plus a serial incrementer.
That would reduce the incremental cost per counter to two blocks,(one
block as a 32-bit RAM, the other one as the adder/carry logic.) The
common overhead would be less than a dozen blocks, and the whole design
would  easily fit into half of the smallest device of our family, the
XC4003E with its 100 blocks.
But it would need a 48 MHz oscillator  ( $2.-)  and a little bit of
creative thinking.
If you accept the challenge, I'll help you. Even in German.

Peter Alfke, Xilinx Applications
 
 

Article: 8446
Subject: Re: bus design in Altera 10K, how to increase speed -- Check out Xilinx
From: "Richard Iachetta" <iachetta@us.ibm.com>
Date: 15 Dec 1997 22:35:48 GMT
Links: << >>  << T >>  << A >>
Jeff Berryhill <berryhill@hep.uchicago.edu> wrote in article
<EL901u.1D5@midway.uchicago.edu>...
> In article <01bd097f$6ebe3e20$6d733509@iachetta>,
> 	"Richard Iachetta" <iachetta@us.ibm.com> writes:
> 
> >My opinion is that the 10K100 is ok for
> >33MHz type designs -- maybe 40 MHz if you work very hard.  
> >Beyond that, use
> >Xilinx.  Of course, you get what you pay for 
> >-- the 4085 is more expensive
> >than the 10K100.
> >
> >-- 
> >Rich Iachetta
> >IBM Corporation
> >iachetta@us.ibm.com
> 
> I have been programming -3 Altera FLEX10K's for the past 1 1/2 years 
> or so, and I would have to say that if you're trying to do anything 
> the least bit complicated 30-40 MHz is about the best you can 
> expect, anything faster (especially on the higher gate count chips)
> will require significant fine tuning to work.  
> 
> That said, I have found that the new (and very expensive) -2 and -1
> speed grades are able to do 50 MHz applications without significant
> fine tuning.  
> 
> --Jeff Berryhill

Ok.  My experience was this summer (June/July) and we were using the
fastest 10k100 vs. the fastest 4085 at the time.  Both companies have come
out with new stuff since.  When you say you've been using FLEX10K's, which
ones did you use?  The 10k100?  The smaller they are, the faster they run. 
It would take a lot to convincing me that the "new" 10K100's can do 50MHz. 
If they can, that's great, but having been burned, I'm a little skeptical.

-- 
Rich Iachetta
IBM Corporation
iachetta@us.ibm.com


Article: 8447
Subject: Serial PROMs for Xilinx FPGAs
From: Duane Clark <Duane.Clark@jpl.nasa.gov>
Date: Mon, 15 Dec 1997 15:48:24 -0800
Links: << >>  << T >>  << A >>
Howdy,

Does anyone know of any 5 volt serial PROMs larger than the XC17256D,
that can be used with XC4000EX FPGAs? I notice that Xilinx has 512K and
1M bit PROMs in a 3.3V package, but apparently nothing so far in 5V.

-- 

-Duane
Article: 8448
Subject: Re: bus design in Altera 10K, how to increase speed
From: ying@soda.CSUA.Berkeley.EDU (Ying C.)
Date: 16 Dec 1997 03:10:44 GMT
Links: << >>  << T >>  << A >>

I take it that you are builting the MUX out of case statements? I did a
quick run in GDF and I was able to achieve 50MHz in a 96 to 8 mux with 
LPM_MUX. Blacking box your mux in verilog and instantiaing it in Max+Plus
design file with lpm_mux would be a quick workaround.

 
ying@csua.berkeley.edu


In article <3491bc91.80619134@news.walltech.com>,
muzo <muzok@pacbell.net> wrote:
>hi,
>I have a design which uses %55 of a 10K100 and within this design I have 12 8 bit
>registers which need to be selectively loaded into another register, IOW, I have
>an 8 bit bus from which 12 8 bit registers hang. Because 10K doesn't have
>internal tristates, I have a big mux which selects the register. Currently this
>mux is the bottleneck in my design which limits my speed to  11 MHz in a -3 part.
>Any ideas how to increase the speed in this design? The design is in Verilog.
>
>Are there any ways to get more performance by using the floor plan tool ? I am
>already using FAST synthesis and maximum speed in the compiler options.
>
>thanks
>
>muzo
>
>WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>


-- 
-----------------------------------
http://www.csua.berkeley.edu/~ying
Article: 8449
Subject: Re: bus design in Altera 10K, how to increase speed
From: ecp@focus-systems.on.ca (Eric Pearson)
Date: Tue, 16 Dec 1997 03:57:58 GMT
Links: << >>  << T >>  << A >>
In article <670s6d$jv7$1@news.netvision.net.il>,
Alex Koegel <alex.koegel@dspis.co.il> wrote:
>In article <3491bc91.80619134@news.walltech.com>,
>   muzok@pacbell.net (muzo) wrote:
>>hi,
>>I have a design which uses %55 of a 10K100 and within this design I have 12 8 
>bit
>>registers which need to be selectively loaded into another register, IOW, I 
>have
>>an 8 bit bus from which 12 8 bit registers hang. Because 10K doesn't have
>>internal tristates, I have a big mux which selects the register. Currently 
>this
>>mux is the bottleneck in my design which limits my speed to  11 MHz in a -3 
>part.
>>Any ideas how to increase the speed in this design? The design is in Verilog.
>>
>>Are there any ways to get more performance by using the floor plan tool ? I 
>am
>>already using FAST synthesis and maximum speed in the compiler options.
>>
>>thanks
>>
>>muzo
>>
>>WDM & NT Kernel Driver Development Consulting <muzok@pacbell.net>
>
>Another option is to use an internal EAB as a 12 x 8-bit wide internal RAM.
>
>Alex Koegel
>DSPC Inc.

 
1/ I hvae successfully used this idea for readback of CPU registers. Ie
shadow the registers in the EAB ram.

2/ For fast access to yoru registers, under certain circumstances, you can
just copy them into a shift register, and shift the whole thing out.

3/ One thing to watch out for in the mux's in the 10K family, is that there
is a feature that the LCELL() primitive is used, so the final output
stage will not be merged into a following ff. So in the instance of that
mux set CASCADE_CHAIN = "OFF" (just look at the lpm_mux code to see why
this works). Basically this cuts a full logic level off.

Eric Pearson

-- 
Eric Pearson -- Focus Systems -- Waterloo, Ontario
     ecp@focus-systems.on.ca  (519) 746-4918
    "We Engineer Innovative Imaging Solutions"


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