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"Ross Swanson" <swan000@erols.com> wrote: > Doesn't Atmel make a FPGA with a small (?) embedded RAM > >We are currently doing a project which requires implementation of > >around > >25K gate-logic and 2K-byte RAM. I think so. However, I know that Lattice make one too. It may be rather _larger_ than they require though. As I remember, the part is the ispLSI3192. /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\ \ Alexander Perry arperry at cts.com / / remove the nospam suffix when replying \ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/Article: 8726
On 16 Jan 1998 05:19:33 GMT, "richard katz" <stellare@erols.com.NOSPAM> wrote: >rk agrees and disagrees: >... >designs. another benefit is that it lets you use a single set of tools for >design like a good macro generator (big fan of them). then just replace Absolutely. Macro generators (e.g. Actel actgen) are the best thing since sliced bread. They let you do an RTL design in no time at all and end up with a reasonably optimized product. >into account? is there still room for good humanoid gate-slingers? :-) >i've heard a bunch of ppl say no - they haven't used a schematic in ages >and get upset at the thought of using schematics. even to hook up >reasonably sized blocks implemented in hdl. > very sad.Article: 8727
Ho Siu Hung <eg_hsh@stu.ust.hk> wrote in article <Pine.GSO.3.95L.980122165922.4645A-100000@uststu1>... > Hello, > > I go into problems making use of only one CLB to build a 5 variable > function. While tied 4 of my inputs to the FMap and GMap, the last input > theoretically can be tied to the H1 to form a LUT with 5 inputs. However, > synopsis FPGA complier always map this to 2 or 3 CLB without utilizing > HMaps. Does anyone here have tried doing that? How to explicitly specify > the use of HMaps as mux? > > A 5 variable function always matches in 1 CLB. But it depends on the equation if you can use - 1 FMAP and 1 HMAP - 2 FMAPs and 1HMAP it depends : if your function f(a1,a2,a3,a4,a5) can be split in f(f1(a1,a2,a3,a4),a5) then you can tie your 4 inputs to a FMAP and the 5th input to a HMAP But if your function has to be split in e.g f(f1(a1,a2,a4),f2(a3,a5)) then you have to tie a1,a2,a4 to a FMAP and a3,a5 to another FMAP(GMAP) and tie the outputs with the HMAP hope this helps, Kim.hofmans@barco.comArticle: 8728
Ho Siu Hung <eg_hsh@stu.ust.hk> wrote in article <Pine.GSO.3.95L.980122165922.4645A-100000@uststu1>... > Hello, > > I go into problems making use of only one CLB to build a 5 variable > function. While tied 4 of my inputs to the FMap and GMap, the last input > theoretically can be tied to the H1 to form a LUT with 5 inputs. However, > synopsis FPGA complier always map this to 2 or 3 CLB without utilizing > HMaps. Does anyone here have tried doing that? How to explicitly specify > the use of HMaps as mux? David, you have to enable the feature of the XACT Design Manager called "Generate 5-Input Functions". I think it defaults off. Its located in the Optimize & Map section of Implementation Options. -- Rich Iachetta IBM Corporation iachetta@us.ibm.comArticle: 8729
Hi Folks, I have purchased the basic Entry level of Altera's MAX+II development software. It includes schematic, VHDL and Altera's HDL front ends. However, I would like to try Verilog - My question is ... Is there a shareware Verilog compiler, a Verilog book accompanied with a CD-ROM verilog compiler or a limited time period version, which I could use ?? Ideally I would like the compiler to generate the right files for the MAX+II software for simulation purposes. While I'm here, can someone tell me the different files that are generated by ?HDL compilers ? for simulation/synthesis etc - is there a standard which most vendors are expected to follow ? Thanks in advance. atul.Article: 8730
"richard katz" <stellare@erols.com.NOSPAM> wrote:
> 2. there was a factor of 2 between timing driven placement and hand
> placement for 2t06. is that typical for this technology or just an
> artifact of this simple circuit? several commented earlier on the
> importance of floor planning, hand placement, etc.
This is typical for Orca and Xilinx (although it's been a few years
now since I did a large Xilinx design. It's possible that the software
is much better now. However, their new software is based on the same
NeoCad engine as the Orca software.)
Notice, however, that the biggest gain was from control over mapping.
This requires intimate knowledge of the Orca hardware as well as the
tools to control mapping. Currently, the Orca software doesn't have
these tools. I've had to write my own netlist flattener and floor
planner to add (reasonable) mapping and layout control to the Orca
design process.
There is now a floor planner available for the Orca chip from a company
called Morphologic. I haven't tried it yet, but they claim it's up and
working now. http://www.morphologic.com/
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Article: 8731
On Thu, 22 Jan 1998 16:24:03 +0000, Atul <use@the.newsgroup> wrote:
> Hi Folks,
>
> I have purchased the basic Entry level of Altera's MAX+II development
> software. It includes schematic, VHDL and Altera's HDL front ends.
>
> However, I would like to try Verilog - My question is ...
>
> Is there a shareware Verilog compiler, a Verilog book accompanied with
> a CD-ROM verilog compiler or a limited time period version, which I
> could use ??
>
Verilog HDL : A Guide to Digital Design and Synthesis
by Samir Palnitkar
carries a CD containing SILOS verilog compiler.
I guess it has certain limitations.
> Ideally I would like the compiler to generate the right files for
> the MAX+II software for simulation purposes.
>
>
> While I'm here, can someone tell me the different files that are
> generated by ?HDL compilers ? for simulation/synthesis etc - is
> there a standard which most vendors are expected to follow ?
>
Brief Design flow.
HDL file
.v .vhd
|
|
------------
| Compiler |--> .log for errors
------------ .dump for viewing waveforms
|
|
------------
| Synthesis|--> .edif .xnf verilog vhdl
------------ for post synthesis simulation
|
|
----------------
| place & route|--> - FPGA / ASIC library specific
---------------- files for layout / FPGA
- backannoted files for post layout
simulation.
Simulation :
vcd (value change dump) files are standard. Every vendor
normally comes out with better scheme with compression
to save time and space.
Synthesis :
EDIF XNF verilog VHDL netlist formats are common.
P&R : Every major company has their own standards. though
interoperable formats exists. I have little knowledge of
them.
Hope this helps.
Rajesh Bawankule
(rajesh@comit.com)
http://www.comit.com/~rajesh/verilog/
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Article: 8732Hello, Before I start asking stupid questions, I was wondering, is there a FAQ for this newsgroup? Knut Arne VedaaArticle: 8733
Can anyone tell me who the players are in the manufacture of RadHard FPGA's? I'm aware of efforts by ACTEL, SPEC, SEi, Honeywell, and Mission Research Corp. Are there others? Who seems to be the industry leader in terms of hardness to severe/nuclear environment specs? Thanks for the input. David LaVigna dlavigna@radium.ncsc.milArticle: 8734
not an fpga, but utmc has the UT22VP10 -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) -------------------------------------------------------------- Rip Loomis <rip@radium.ncsc.mil> wrote in article <34C7C89A.17B64362@radium.ncsc.mil>... : Can anyone tell me who the players are in the manufacture of RadHard : FPGA's? I'm aware of efforts by ACTEL, SPEC, SEi, Honeywell, and : Mission Research Corp. Are there others? Who seems to be the industry : leader in terms of hardness to severe/nuclear environment specs? : : Thanks for the input. : : David LaVigna : dlavigna@radium.ncsc.mil : :Article: 8735
Hello. Couple of days back I posted an article reagrding what device to use: Altera vs Xilinx. Our design requirement is a 2K-byte Sync RAM and approximately 22K gate-logic. I have almost decided to use 10K100 part which has 12 EABS, eight of which can be used for implementing the RAM. The remaining EABs and the 624 LABs will give me approximately 62K available gates. *) The data sheet says 10K100 has 62K-158K gates available. I never understood this.... If all EABs are used as memory, it gives me 24K gates and from 624 LABs, I get ~62K and hence, 86K.. Minimum is ~62K which is correct. Can somebody explain the maximum limit? *) However, can somebody tell me how to choode a device based on the gate count required? In other words, how much fetch factor we need to allow for FPGAs/ EPLDs. Can somebody share their experince in Xlinx and Altera devices? One more thing I'm concerned is our design has some blocks operating at 48 MHz. Is that Ok in Altera devices? What'd be the practical max CLK for altera devices assuming that I've all i/ps and o/ps registered. Thanks and regards, -- Srikanth Gurrapu, Texas Instruments, Inc. Ph: (972)-480-2318 (o) (972)889-9678 (h) Fax: (972)-480-2264 Email: gurrapu@ti.comArticle: 8736
> - trivial on the ISA bus but not on the PCI I think. Try 'http://www.plxtech.com/basic.htm' for an asic. Cheers, IANArticle: 8737
Here's my two cents worth: I've been consulting with a company for the past year now implementing a several designs in Xilinx (4062) and Altera (10K70) components. Below are several observances the design group has made relating to the pluses and minuses of the respective parts and tools: 1) Although according to the gate-count specs, the parts would appear to be similar in capabilities, we found that a 70% full Xilinx part held about 40% more logic than a 70% full Altera, for these particular designs. 2) The place and route times for Xilinx ran between 24 hours (68% full) and 53 hours (70% full). It seemed odd that a relatively small change in logic produced such a large change in place and route time. 3) The place and route for Altera took approximately 1 1/2 hours (but see item #4). A small change in utilization did not seem to make a large impact in the place and route times. 4) The Altera Maxplus II tool is not a timing driven tool. It is up to the designer to manually create 'cliques' (i.e. groups) of registers. The tool then places the registers in proximity to each other to reduce prop delay. There are no provisions to tell the tool that a certain path has lots of slack so that parts may be spread out. We found that doing a lot of synthesis timing optimization was a waste of time because Maxplus II would re-optimize things its own (twisted) way. Obviously, Maxplus II was our biggest gripe with Altera. The Xilinx M1 tool, on the other hand, is timing driven and did not require any manual intervention. 5) The Altera FPGA's do not support internal tri-state buffers as does Xilinx. They also implement combinational muxes poorly, as does Xilinx (but tri-state buses in Xilinx make good muxes if the muxes are big). 6) The RAM's within Xilinx are small, many and scattered throughout the array. The Altera RAM's are large and few. So, if you have a lot of small RAM's, Altera is probably not a good choice. Xilinx clocked RAM's also seemed more usable for our particular application than did the Altera. 7) In our application, the Altera parts ran noticeably hotter on the board than the Xilinx (sorry - I don't have actual temperature data). System clock was 33 MHz. 8) Another irritating quirk of the Altera parts that we found was that any unused I/O pins defaulted to *outputs*. We had designed the board with extra connections from the board processor to the FPGA "just in case". Since these 'unused' I/O defaulted to outputs, it caused the processor to hang up royally. We needed to tell Maxplus that these pins were inputs. The Xilinx M1 tool defaults unused I/O to inputs. 9) Our particular design had several 'versions' (i.e. we left off some functionality). We made one full-up design (VHDL) then, during synthesis, deleted the parts we didn't want for that particular version. This caused some hierarchical output ports to not be connected. This caused Maxplus II to choke (i.e. it quit with an error message). Xilinx M1 had no problem with it. This problem was reported to Altera customer support. 10) We had a difficult time meeting timing on what should have been simple counters within Maxplus. The FAE suggested that we change our general VHDL counters to the Maxplus parameterized models to improve the place and route process. This went against our desire to maintain general VHDL code that could be more easily ported to an ASIC or other FPGA technology. 11) We found that hand-editing a Xilinx routed design was pretty easy and straight-forward. We did not find Maxplus II to be a reasonable tool to manually edit a layout. However, we only performed hand-routes on the Xilinx because we didn't want to wait 1 to 2 days for an auto-route to complete. To answer the first question, we performed a gate-count analysis of our design and concluded, using the equivalent gate-count numbers from the Altera data sheet, that it should fit in a 10K70 with room to grow. In actuality, it turned out that less than half of the design fit. We estimate that we got about 30K gates into the thing. We ended up putting about 40% of the logic in the 10k70 (about 70% utilized) and the remainder in a Xilinx 4062 (about 68% utilized). This is how we obtained lots of side-by-side comparisons of the components. Disclaimer: These utilization figures are based solely on our particular design. Your mileage may vary. Hope this helps. Tom [This followup was posted to comp.lang.vhdl and a copy was sent to the cited author.] In article <34C7E444.1970@ti.com>, gurrapu@ti.com says... > Hello. > > Couple of days back I posted an article reagrding what device to use: > Altera vs Xilinx. Our design requirement is a 2K-byte Sync RAM and > approximately 22K gate-logic. > > I have almost decided to use 10K100 part which has 12 EABS, eight of > which can be used for implementing the RAM. The remaining EABs and the > 624 LABs will give me approximately 62K available gates. > > *) The data sheet says 10K100 has 62K-158K gates available. I never > understood this.... If all EABs are used as memory, it gives me 24K > gates and from 624 LABs, I get ~62K and hence, 86K.. Minimum is ~62K > which is correct. Can somebody explain the maximum limit? > *) However, can somebody tell me how to choode a device based on the > gate count required? In other words, how much fetch factor we need to > allow for FPGAs/ EPLDs. > Can somebody share their experince in Xlinx and Altera devices? > > One more thing I'm concerned is our design has some blocks operating > at 48 MHz. Is that Ok in Altera devices? What'd be the practical max CLK > for altera devices assuming that I've all i/ps and o/ps registered. > > Thanks and regards, > > -- > Srikanth Gurrapu, > Texas Instruments, Inc. > > Ph: (972)-480-2318 (o) (972)889-9678 (h) > Fax: (972)-480-2264 > Email: gurrapu@ti.com > -- Thomas Rock thomas@x-tekcorp.comArticle: 8738
I'm looking for article (or anything ) that compare or give advantage and desavantage of DSP against FPGA families (Xilinx, altera and others). My main goal is to compare both in general signal processing implementation (Speed, Complexity, etc...) It is actually for a project course. I'll even what you think about the subject.:) Please send your reply (beside this news groupe) to langlois@joule.info.uqam.ca Thanks to all. Carl Langlois UQAM MicroelectroniqueArticle: 8739
Spare time? I am working on a design for a video capturing device, I have most of the hardware designed and implemented when I found that there were some problems with the design and a CPLD would have to be developed to handle some of the high speed stuff. I hope to use the 9572 by Xilinx to do this. Basically the CPLD must look at some 8 bit data and extract embedded codes that represent new frames and new lines for the video image being digitized. Then it must shuffle some of the embedded codes along with some digitized video images off into an attached SRAM buffer. The SRAM would be address through a counter. The data comes in at around 28Mhz, so in about 30ns you must read the data and then make some decisions to write it or get some more data, the write of the SRAM may occur right away and be follow by another write immediately or may take a few cycles for the next write. I would like to hook up with a willing sole and see if we can't get this project done together. I do have Foundation at my disposal, just not the time to learn it right now. Let me know what you think by emailing me at sloan@magma.ca and we'll see if we can't make some magic happen with this beast. Thanks, Richard.Article: 8740
rajesh@NoSPAM-1606.comit.com wrote: > > On Thu, 22 Jan 1998 16:24:03 +0000, Atul <use@the.newsgroup> wrote: > > Hi Folks, > > > > I have purchased the basic Entry level of Altera's MAX+II development > > software. It includes schematic, VHDL and Altera's HDL front ends. > > > > However, I would like to try Verilog - My question is ... > > > > Is there a shareware Verilog compiler, a Verilog book accompanied with > > a CD-ROM verilog compiler or a limited time period version, which I > > could use ?? > > > Verilog HDL : A Guide to Digital Design and Synthesis > > by Samir Palnitkar > carries a CD containing SILOS verilog compiler. > I guess it has certain limitations. > > > Ideally I would like the compiler to generate the right files for > > the MAX+II software for simulation purposes. > > > > > > While I'm here, can someone tell me the different files that are > > generated by ?HDL compilers ? for simulation/synthesis etc - is > > there a standard which most vendors are expected to follow ? > > > Brief Design flow. > > HDL file > .v .vhd > | > | > ------------ > | Compiler |--> .log for errors > ------------ .dump for viewing waveforms > | > Is there a file -> | > | > generated here ------------ > | Synthesis|--> .edif .xnf verilog vhdl > ------------ for post synthesis simulation > | > | > ---------------- > | place & route|--> - FPGA / ASIC library specific > ---------------- files for layout / FPGA > - backannoted files for post layout > simulation. > I take it there isn't a standard file format you can generate from a verilog/vhdl compiler which can then be ported to any synthesis tool ? Does this mean I need to purchase the Verilog front end for the MAX+II development software - in order to write synthesiseable code ? > Simulation : > vcd (value change dump) files are standard. Every vendor > normally comes out with better scheme with compression > to save time and space. > Synthesis : > EDIF XNF verilog VHDL netlist formats are common. > P&R : Every major company has their own standards. though > interoperable formats exists. I have little knowledge of > them. > Hope this helps. > Rajesh Bawankule > (rajesh@comit.com) > http://www.comit.com/~rajesh/verilog/ > > -------------------------------------------------------------------- > Posted using Reference.COM http://WWW.Reference.COM > FREE Usenet and Mailing list archive, directory and clipping service > --------------------------------------------------------------------Article: 8741
Alternatively, Is there a tool out there for translating the verilog to VHDL and vice versa. ? > > HDL file > .v .vhd > | > | > ------------ > | Compiler |--> .log for errors > ------------ .dump for viewing waveforms > | > | > ------------ > | Synthesis|--> .edif .xnf verilog vhdl > ------------ for post synthesis simulation > | > | > ---------------- > | place & route|--> - FPGA / ASIC library specific > ---------------- files for layout / FPGA > - backannoted files for post layout > simulation. >Article: 8742
I'm looking for a source of Military temp. range (Not necessarily full Mil-Spec) 3.3V FPGA/CPLDs. So far I've come up with: ACTEL QuickLogic (3.3V ?) Lucent Xilinx Are there any others ? Which SRAM based vendors do mask programmed versions ? Any help appreciated -- _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 8743
Carl Langlois wrote: > I'm looking for article (or anything ) that compare or give advantage > and desavantage of DSP against FPGA families It is important to address this comparison with an open mind and the willingness to take a fresh look if the fundamental job. DSP processors time-share one or two arithmetic engines between many tasks. Therefore, each multiplier must handle two variables as inputs. FPGAs have up to thousands of look-up-tables, and can perform many arithmetic operations in parallel, and with any desired precision. When, for example, all multiply-accumulate operations of an FIR filter are being performed by parallel hardware ( LUTs ), one of the two factors in each multiplier usually becomes a constant. And that reduces the hardware complexity enormously. This massive parallelism is the secret behind the surprising performance of LUT-based FPGAs. Even at moderate clock rates, they can often outperform the most advanced DSP processors running at 200 MHz. But you have to take a fresh look at the problem to be solved. Peter Alfke, Xilinx ApplicationsArticle: 8744
Srikanth Gurrapu wrote: > *) However, can somebody tell me how to choode a device based on the > gate count required? In other words, how much fetch factor we need to > allow for FPGAs/ EPLDs. > Can somebody share their experince in Xlinx and Altera devices? Another to consider when choosing between Xilinx & Altera is the memory in Altera is fixed within their EAB's. Whereas Xilinx reconfigures their CLB's. If you are sure of your memory requirements and they fit within the Altera part of choice then not a problem, but if it might grow or if you require lots of small memory modules you may run out of EAB's whereas in Xilinx it converts more CLB's. (also of note Xilinx new Virtex family supports both block ram & distrubted CLB ram). Regards Glenn EngArticle: 8745
In Max+PlusII version 8.2, which started to be distributed from last week, has verilog synthesis included. One problem is when you purcahse Max+PlusII, you should select which language do you want(VHDL or Verilog HDL). So best thing you should try is to call sales person and let him know you want Verilog-HDL. Thanks D.H. Atul ÀÌ(°¡) <34C870CC.F64E8261@the.newsgroup> ¸Þ½ÃÁö¿¡¼ ÀÛ¼ºÇÏ¿´½À´Ï´Ù... >Alternatively, Is there a tool out there for translating the verilog to >VHDL and vice versa. ? > >> >> HDL file >> .v .vhd >> | >> | >> ------------ >> | Compiler |--> .log for errors >> ------------ .dump for viewing waveforms >> | >> | >> ------------ >> | Synthesis|--> .edif .xnf verilog vhdl >> ------------ for post synthesis simulation >> | >> | >> ---------------- >> | place & route|--> - FPGA / ASIC library specific >> ---------------- files for layout / FPGA >> - backannoted files for post layout >> simulation. >>Article: 8746
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Article: 8747We have seen some concerns recently about large row-to-row delays in "big" 10K devices. These delays can really cripple the available performance and getting a realistic design to run at >40MHz in a 10K100 is very hard. Also, because of the much higher power consumption in 10K parts compared to Xilinx 4K/E/EX/XL parts it is not always possible to run the devices at their maximum theoretical speed pecause of power dissipation problems. As to gate counting... The larger value for the gate count assumes 20% of the available RAM is used as RAM and that each RAM bit is equivalent to 6 gates. Also note that in a Xilinx part such as the 4036 the 36 represents 36,000 gates of usable logic with no RAM adder. Roughly double the size to find the comparable Altera part(N.B. this is for designs which are neither best suited to large block RAM or small distributed RAM.) In an attempt to combat the confusion over part comparison, rightly or wrongly, all new Xilinx families will have their size marked similarily to Altera parts e.g. the XCS20 is about the same size as the 10K20. A note on dual-port RAM... In a 10K part the EABs do not support a true dual-port mode, they emulate dual port memory by using the available logic to build the required multiplexers. This has two effects 1) dual ports use RAM and a considerable amount of logic in Altera parts 2)they require two clocks to run the mux and to de-multiplex the RAM output In a Xilinx 4K the LUTs can be configured as dual-port so your trading off logic for RAM but it's easier to work out exactly how much your using. 2 LUTs = 16x1 dual-port. Also all the multiplexing is invisible to the user.Article: 8748
Chris Bore wrote: > > Carl Langlois <langlois@joule.info.uqam.ca> wrote: > > >I'm looking for article (or anything ) that compare or give advantage > >and desavantage of DSP against FPGA families (Xilinx, altera and > >others). > > It seems clear that FPGAs can be used for signal processing tasks, > especially where high speed is required. > > The biggest limitation I have noted in proposed designs, is that an > FPGA does not actually implement a hardware multiplier - instead, they > make a multiplier by using a lookup table. This is reasonable when the > word length is small, and also if the number of values on one side of > the multiply is limited - for instance, in implementing an FIR filter > we only need the lookup table values for he number of coefficients, > not for all possible values. It could be restricting if trying, for > example, to build an FPGA with 24 bit word length and general > multiplies - the lookup table would be very large. Well, not exactly. For LUT based FPGAs, the multiplication is basically broken down into partial products, then those partial products are summed in an adder tree. A 12 x 12 integer multiply with a 24 bit output will run at a 48 MHz data rate with a 5 clock latency (no restrictions on the values of either input). Note with the 24 bit output, there is no loss of precision in the multiplier itself (you need the full 24 bits internally to get the MSBs out) The basic strategy is to multiply one input by each 2 bits of the other input (this gives 0,1,2 or 3 times the first input for each bit pair). Each of these partial products is summed in an adder tree using the appropriate bit shift for the position of the bit pairs in the input. The 12x12 multiply takes an area of 12x14 CLBs in a Xilinx 4K device. Larger Multiplies are also possible, with the associated degradation in cycle time due to the longer carry chain in the adders. The extra bits also increase the number of pipeline stages so the latency may increase. While 12x12 bits may not seem like a big multiplier, I have seen very few DSP applications that can't be done with the limited bit size if you pay attention to the poistion of the radix point throughout your process. Frankly the high bit widths and floating point capabilities of DSP micros has made DSP programmers somewhat lazy when it comes to dealing with limited precision. In Non-LUT arrays, such as the new Atmel 40K, there is generally enough resource to actually construct an array multiplier. The Atmel device has diagonal interconnects and a very fine grain architecture that help make such a design very fast. When one input of the multiplier is a constant or is limited to a small set of possible values, as is often the case in filters, some short cuts are available that will permit very high performance in very little logic. In the case of an FIR filter, the summation of the taps is accomplished in side the multiplications by using a distributed arithmetic trick. Basically, the contribution of each bit on the input is computed at each tap and summed together. I this case, there are really no physical multipliers, rather the multiplication is done through a lookup table and some rearranging of the math. The result is you can get many more filter taps into a design than would be possible using separate multipliers for each tap. As an example, a 32 tap 8 bit filter will run at a sample rate of 55MHz and occupies under 300 CLBs (Configurable logic blocks). The Xilinx 4K devices have anywhere from 64 CLB to 1032 in the E series parts, and many more in some of the newer $KEX parts. I have one design that has a pair of 12 bit by 8 tap FIR filters, three 12x12 multipliers and other logic in a single XC4025E. THat design has a 42 MHz sample rate. > > The second limitation I have noted is - again related to the > multiplier - most DSPs have extended registers to hold results of > multiplies without overflow: for instance the Motorola 56301 uses 24 > bit words but has internal 56 bit registers to hold the result of a > multiply without overflow. This means that DSP processors are more > precise when arithmetic can be confined within the device itself > (quantisation occurs when the results have to be written to memory). > To mimic such a feature in an FPGA would increase complexity. The multiplier hardware always requires full precision internally. The number of output bits is always the sum of the number of bits in the inputs. (you could throw away some of the most significant bits, but that effectively is equivalent to reducing the number of bits on one or both of the inputs too). In the FPGA, you have the option of using the lower bits or discarding them. THis is similar to what happens with your multipliers when you go off chip. Again, most DSP applications can be done with bit widths of about 12 bits if you pay attention to your scaling. > > Obviously, it would be possible to implement a real multiplier, and > extended precision, in an FPGA - at the expense of extra complexity. I > have been told that such things are done, but I have never actually > seen it done: I confess that after many years of wide eyed innocence > in listening to marketing men's talk in DSP I can no longer stomach > six impossible things before breakfast - I tend now to believe things > when I see them with my own eyes., and often not even then. > I suppose I would be skeptical if I were just reading the FPGA manufacturer's marketing claims. The fact is, however, that I do this stuff day in and day out to pay the bills. I am not married to any of the FPGA vendors (although I do have my preferences as to part families for specific applications...some architectures are better than others). I have even had a hand in pushing the DSP envelope for FPGAs. My 27 Tap FIR filter presented at PLDCon in 1993 was the first publicly disclosed FIR filter implemented in an FPGA. That design is the one Atmel has in their 6K macro generator. I've also pioneered use of the CORDIC algorithm in FPGAs for a variety of uses including modulation and demodulation (sample rates to 50MHz and beyond). I'm presenting a talk at DesignCon next week on using FPGAs in digital communications as modulators and demodulators. DSP in FPGAs is in fact very real. I've personnally used them in phsyical modelling, radar signal processing, radar environment simulation, image processing, audio processing, digital communications and other applications. I'd like to invite you to one of my talks (This year I'll be presenting at DesignCon next week and FPGA'98 at the end of february). YOu are also welcome to visit my web page, which is regretfully very out of date for a taste of some of the work I've done making DSP real for FPGAs. -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 8749
AS OF 1/22/98, THERE ARE 528 COMPANIES ON THIS LISTING!! 64 new ones added since Christmas!!! -- IMPORTANT NEWS FOR USERS OF GRAY'S SEMICONDUCTOR URL PAGES the only URLs that now work for accessing my site are as follows: http://www.scruznet.com/~gcreager/welcome.htm http://www.scruznet.com/~gcreager/brief.htm (non-frame brief listing) http://www.scruznet.com/~gcreager/verbose.htm (non-frame verbose listing) any old links to my site that access other pages will lead to "page not found" errors -- Now, just a reminder to everyone... I have been compiling a semiconductor manufacturer website listing (and making it available to other engineers on the web) for almost 3 years now. I used to post it to sci.electronics every so often in the past, but it has gotten way too big for that. There are 528 companies on the list currently. These are chipmakers who market chips under their own names, so if you can't find the data sheet that you need because you don't know the manufacturer's website, try my listing. Bookmark it and tell your co-workers!! I try to keep it the most up-to-date and useful listing of chipmakers anywhere on the web (by constantly searching for new URLs before most others find them) and it is now widely used by a lot of people. The following categories exist among my "engineering" subpages. - Semiconductor URLs (Brief listing) - Semiconductor URLs (Verbose listing; includes product categories) - New Semiconductor URLs - Missing Semiconductor URLs - Motivations - Engineering Humor try it out, I think you'll find it to be quite useful... and let me know what you think. Again, the URL is: http://www.scruznet.com/~gcreager/welcome.htm The website is best viewed in a frames environment, but there are "back doors" for getting to these pages if your browser doesn't support frames. Thanks for all the support everyone has given me in this endeavor! :-) Gray Creager
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