Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
********************************
**** CALL FOR PARTICIPATION ****
********************************
1998 DAC University Booth
http://erebor.cudenver.edu/sigda
at the
35th Design Automation Conference
June 15-19, 1998
Moscone Center
San Francisco, CA
The DAC University Booth provides an opportunity for the
university community to demonstrate EDA tools, design
projects, and instructional materials at the ACM/IEEE
sponsored Design Automation Conference (http://www.dac.com).
You do not have to have a paper at DAC to demonstrate EDA
tools, design projects, and instructional materials at the
DAC University Booth, you simply need to attend DAC 1998 in
San Francisco.
The University Booth also provides space for the
presentation of EDA vendor literature and programs of
interest to the university community.
The 1000 square foot ACM SIGDA University Booth provides
booth space, poster areas, computers, printers, and a T1
connection to the Internet for participating universities.
(Please visit http://erebor.cudenver.edu/sigda for further
information.)
To sign up, simply send the following information to the
email address below, or better yet sign up at our web site
http://erebor.cudenver.edu/sigda.
--------------------------------------------------
1) Your Name (Primary Contact):
2) E-Mail: (user@etc.etc.etc)
3) University:
4) Department:
5) URL: (http://etc.etc.etc)
6) Computer Needed:
(Indicate if you will bring a machine.)
7) Operating System:
8) Brief Description of software, design project, or course
--------------------------------------------------
-Rich Auletta
1998 DAC University Booth Coordinator
University of Colorado at Denver
Electrical Engineering
Email: rauletta@erebor.cudenver.edu
URL: http://erebor.cudenver.edu/sigda
Voice: 303-556-2357
Fax: 303-556-2383
-------------------==== Posted via Deja News ====-----------------------
http://www.dejanews.com/ Search, Read, Post to Usenet
Article: 8826I'm just beginning to study Verilog or VHDL. Is there any difference between these two names? What will be the very suitable introductory book for this Verilog and/or VHDL? Thanks. Please email back: xiao@umr.eduArticle: 8827
Normally, you maybe right there is no difference between hdl and schematic. But there is a huge difference when it really matters. For example, you may need a very high performance 32 bit priority encoder.i A 32 bit priority encoder will likely be a huge bottle neck in your design if you this in vhdl. Synthesis will create this priority encoder using 4 input lookup tables and it will slow down your design to a ridiculoys speed. On the other hand, in schematic I can customize the carry logic using CY4 components in Xilinx and build a priority encoder that will perform at about 10ns in a 4000XL-09. Not bad ahh? Doing this implementation in VHDL will take at least 20 ns if the routes are decent and the synthesis tool is fairly good. If you want to get your job done and meet deadlines vhdl is the way to go. However, be prepared to replace some of your modules by designs done in schematic when vhdl doesn't do it. In article <6aqqra$3nl@borg.svpal.org>, George Noten <garyk@svpal.svpal.org> wrote: >Simon Ramirez (s_ramirez@email.msn.com) wrote: > I am not sure there is a big difference. You *can* do in VHDL absolutely > the same design that you do in schematic (i.e. write a netlist). The > only difference is that VHDL will be more portable and easier to > simulate. OTOH, you will need a schematic to understand what you wrote > in VHDL. > > > So-called "behavioral" VHDL description comes down to 2-3 sequential > statements that the synthesis tool is able to understand (and each > vendor interprets them in a different way). No big deal. Sometimes > I do use behavioral description, but usually I prefer netlist and para- > metrized libraries (XBLOX or LPM). Normally there is no difference in > performance between this type of design and schematic. > > George. >Article: 8828
In altera ftp suite(ftp.altera.com), you can find eau019.exe in /pub/utils directory. This files reads .tt2 file from Data I/O v4.0 or later and translate into .tdf(AHDL) file. Hope this helps. Thanks D.H. Ying C. ÀÌ(°¡) <6am21r$hn2$1@agate.berkeley.edu> ¸Þ½ÃÁö¿¡¼ ÀÛ¼ºÇÏ¿´½À´Ï´Ù... > >I believe you can compile an ABEL file in Synario and get out an AHDL >output file. > >Ying >ying@csua.berkeley.edu > > > >In article <34CD9B42.52C0@altatech.com>, >Douglas L Datwyler <datwyler@altatech.com> wrote: >>Does any one know of a RELIABLE ABEL to Altera-HDL conversion utility? >> >>Where is the FAQ for this news group? >> >>Thank you, >> >>Douglas L Datwyler >>Alta Technology >>datwyler@altatech.com > > >-- >----------------------------------- >http://www.csua.berkeley.edu/~yingArticle: 8829
Can anyone guide me with the design of a 3-staged pipelined multiplier in VHDL that is optimised for Xilinx 4000XL series ? -- Johannes Sølhusvik, PhD, Electronic Systems ABB Corporate Research Centre, Norway Tel: +47 66 84 34 28, Email: jso@nocrc.abb.noArticle: 8830
Marco Rivero wrote: > 3. I cannot lock a pin onto a complemented NET on a .ucf file. Tried a "-" as > I used to do with XACT: didn't work. Tried a "~" as done on Viewlogic netlists, > and .ncd files!: Didn't work. Called customer support and was told to remove In a previous life I was the Viewlogic tools manager. I insisted that the "~" NOT be used for inverted nets because different tools had different sets of acceptable characters. While one should probably expect trivial things like character sets to be common among tools by now, such is not the case. I would strongly reccomend using only alpha-numeric characters and the "_" character in all net and module names. From my experiance, these are the only characters that you can be sure will be accepted by other tools. While it is somewhat cumbersome, I always use "_l" as a suffix for active low nets and I would guess that other people have similar constructs. ToddArticle: 8831
Marco Rivero wrote: > 3. I cannot lock a pin onto a complemented NET on a .ucf file. Tried a "-" as > I used to do with XACT: didn't work. Tried a "~" as done on Viewlogic netlists, > and .ncd files!: Didn't work. Called customer support and was told to remove In a previous life I was the Viewlogic tools manager. I insisted that the "~" NOT be used for inverted nets because different tools had different sets of acceptable characters. While one should probably expect trivial things like character sets to be common among tools by now, such is not the case. I would strongly reccomend using only alpha-numeric characters and the "_" character in all net and module names. From my experiance, these are the only characters that you can be sure will be accepted by other tools. While it is somewhat cumbersome, I always use "_l" as a suffix for active low nets and I would guess that other people have similar constructs. ToddArticle: 8832
In article <34CF5524.255D@nortel.co.uk>,
Peter Rush <prush@nortel.co.uk> wrote:
>Maybe it's just the way that I'm using it, but does anybody else out
>there think that 8.2 is a giant leap backwards from 8.1!
>
>For my project (60% full 10K50, 2 clocks 25 and 50 MHz) compile times
>have gone from about 0.5 hrs to about 3 hrs, cliques seem to be ignored,
>and I get 10 - 15 timing constraints not met (previously 5 not met).
>
>I'm just glad I can still use 8.1.
Wow, I thought I was the only one!
Our design in a 10K130 compiles under 8.1. Under 8.2 it does'nt even
get past the syntax checking stage, it blows up in one of the LPMs.
We would really like 8.2 as it has the improved timing models for the
10K130.
Just for interests sake we are at 92% of a 10K130 running at 40 Mhz,
compile times are chaotic. Minor changes in design give compile times
ranging from 1.2 hours to 44.5 hours ( at least thats the longest we've
waited before giving up, and making some minor change ). If I add timing
constraints the compiler gives up. We started out at 150% utilization,
the design only started to route when we reached 92% LE utilization.
Even with complaints though, we DO have a functioning design.
Eric Pearson
--
Eric Pearson -- Focus Systems -- Waterloo, Ontario
ecp@focus-systems.on.ca (519) 746-4918
"We Engineer Innovative Imaging Solutions"
Article: 8833madarass@cats.ucsc.edu (Rita Madarassy) writes: > On the other hand, in schematic I can customize the carry logic using > CY4 components in Xilinx and build a priority encoder that will perform > at about 10ns in a 4000XL-09. Not bad ahh? So what you are saying is that a synthesis tool that does not know these CY4 components will perform poorly. That does not surprise me. What happens when you use a synthesis library that contains the CY4 component you mention? Will the synthesis tool still perform poorly, and if so: Why won't it use the component? GeirArticle: 8834
Geir, What really matters in this case is whether or not the synthesis tool is smart enough to take advantage of the element for your given design. Some are, some aren't, and there are a lot of factors that come into play. Typically, each tool has a variety of settings that result in the usage of different library elements. A typical example is a resource sharing option that would use an ADDSUB component when turned on and one each of ADD and SUB components when turned off. For situations like these, you need to examine your synthesis tool outputs and typically tweak the appropriate settings to try and get what you want. Even then, you may have to resort to schematics to implement EXACTLY what you want for optimal performance or area utilization. Adam Geir Harris Hedemark <geirhe@hridil.ifi.uio.no> wrote in article <xq3n2gdlnu7.fsf@hridil.ifi.uio.no>... > madarass@cats.ucsc.edu (Rita Madarassy) writes: > > On the other hand, in schematic I can customize the carry logic using > > CY4 components in Xilinx and build a priority encoder that will perform > > at about 10ns in a 4000XL-09. Not bad ahh? > > So what you are saying is that a synthesis tool that does not know > these CY4 components will perform poorly. That does not surprise me. > > What happens when you use a synthesis library that contains the CY4 > component you mention? Will the synthesis tool still perform poorly, > and if so: Why won't it use the component? > > Geir >Article: 8835
In article <xq3n2gdlnu7.fsf@hridil.ifi.uio.no>, Geir Harris Hedemark <geirhe@hridil.ifi.uio.no> wrote: >madarass@cats.ucsc.edu (Rita Madarassy) writes: >> On the other hand, in schematic I can customize the carry logic using >> CY4 components in Xilinx and build a priority encoder that will perform >> at about 10ns in a 4000XL-09. Not bad ahh? > >So what you are saying is that a synthesis tool that does not know >these CY4 components will perform poorly. That does not surprise me. > >What happens when you use a synthesis library that contains the CY4 >component you mention? Will the synthesis tool still perform poorly, >and if so: Why won't it use the component? There are a few tradeoffs when using CY4 components. First of all, you will inherently need to assign location constraints to the CY4s otherwise the xilinx tools will complain with errors. Second, customizing the CY4 components for specific implementations is EXTREMELY HARD to do. Only the latter generation synthesis tools like Synplicity will implement CY4 for other non-arithmetic code. Last but not least, when adding location constraints you may make life very hard for the router since the xilinx tools will have to deal with a large chunk of logic. > >GeirArticle: 8836
bootrecord wrote: > > persons wishing to modify the Volume Serial Number may use the following > process: > > re-boot in MS-DOS mode. (dos boxes can't write to the boot) > DEBUG > L 100 2 0 1 ; read a copy of the boot sector from #2 or C: > D 100 ; dump 128 bytes, look for words FAT16 or FAT32 > ( you can view the present serial number at the offsets listed below) > ( W 100 0 5 1 ; write a copy to sector 5 of #0 or A: scratch floppy > if you wish ) > ( Later you can L 100 0 5 1 and W 100 2 0 1 to restore if you must ) > E127 ; edit starting at byte CS:127 for FAT16 or FAT12 > E143 ; edit starting at byte CS:143 for FAT32 > ( enter desired serial number, in reverse byte order, follow each with > <SPACE>) > ( serial number 1234-5678 is entered as 78 56 34 12 ) > W 100 2 0 1 ; write it back out > > notes: in a previous post in this ng, S.E.E. indicated difficulty with > the FAT32 version, and had to format. S.E.E. placed his R/W buffer at > 0x0 instead 0x100. this may have been the source of the problem, it has > been customary to use 0x100, because the PSP and other things (stack) > are placed below 0x100. it's not clear to me that these areas would be > used by the L and W commands, though. my tests were successful with > FAT12, FAT16, and FAT32 volumes. also, ? gives help in debug. > > regards to all xilinx M1 users. > bill Great info Bill, what about NTFS? Regards, JackArticle: 8837
Absolutely agree. Whenver I have a question or issue with even the most esoteric parts of VHDL, Ashenden has an example and a understandable description. I began with VHDL in '88, and looked at many books; Ashenden's is the best single resource available. Deependra Talla wrote in message <6am4ub$p0l@ftp.ee.vill.edu>... >The Designer's Guide to VHDL by Peter Ashenden is the coolest book.. > >-- >~~~~~~~~~~~~~~~~~~~~ deepu@ece.vill.edu ~~~~~~~~~~~~~~~~~~~~~~~~~~~ >| Deepu Talla | If it is not necessary to change | >| | it is necessary not to change ... | >| Phone: (610)225-0243 (R) | | >| (610)519-7371 (O) | whatever, whoever, wherever, whenever| >~~~~~~~~~~~~~~~~ http://www.ece.vill.edu/~deepu ~~~~~~~~~~~~~~~~~~~Article: 8838
<snip snip> >get past the syntax checking stage, it blows up in one of the LPMs. >We would really like 8.2 as it has the improved timing models for the >10K130. > You can always change the timing models, they are not linked to the compiler. Just take the DMF file from 8.2 and put it in the MAXPLUS2 directory. I would back them up first of course. You can even tweak that file if you want to do more than one corner on your simulation. MattArticle: 8839
Rita Madarassy wrote: > > Normally, you maybe right there is no difference between hdl and > schematic. But there is a huge difference when it really matters. > For example, you may need a very high performance 32 bit priority encoder.i > > A 32 bit priority encoder will likely be a huge bottle neck in your > design if you this in vhdl. Synthesis will create this priority > encoder using 4 input lookup tables and it will slow down your > design to a ridiculoys speed. > On the other hand, in schematic I can customize the carry logic using > CY4 components in Xilinx and build a priority encoder that will perform > at about 10ns in a 4000XL-09. Not bad ahh? > Doing this implementation in VHDL will take at least 20 ns if the routes > are decent and the synthesis tool is fairly good. > > If you want to get your job done and meet deadlines vhdl is the > way to go. However, be prepared to replace some of your modules > by designs done in schematic when vhdl doesn't do it. > > In article <6aqqra$3nl@borg.svpal.org>, > George Noten <garyk@svpal.svpal.org> wrote: > >Simon Ramirez (s_ramirez@email.msn.com) wrote: > > I am not sure there is a big difference. You *can* do in VHDL absolutely > > the same design that you do in schematic (i.e. write a netlist). The > > only difference is that VHDL will be more portable and easier to > > simulate. OTOH, you will need a schematic to understand what you wrote > > in VHDL. > > > > > > So-called "behavioral" VHDL description comes down to 2-3 sequential > > statements that the synthesis tool is able to understand (and each > > vendor interprets them in a different way). No big deal. Sometimes > > I do use behavioral description, but usually I prefer netlist and para- > > metrized libraries (XBLOX or LPM). Normally there is no difference in > > performance between this type of design and schematic. > > > > George. > > You can get the structure you need to get the desired performance and density using an HDL, but you will likely have to resort to low level instantiation and a host of extra attributes to control placement. Effectively, this is writing a textual description of the schematic. The current HDL synthesis tools really don't provide enough control over the design implementation to quickly, reliably and successfully turn out high performance designs. Hopefully the CAE vendors will fix this soon, but I am not holding my breath. As I see it, the two real advantages an HDL has over well executed schematics are: 1) the design concept can be simulated behaviorly before the detail design is even started (increasingly important). THis allows a higher degree of HW/SW cosimulation, as well as early test bench development and the ability to find systemic snafus before the design has gone on for months. 2)Archiving the design. Schematics generally require the schematic tool to access electronic archives of the design, and definitely need the tool to make modifications. The CAE vendors can and do make changes to the database formats from rev to rev, which can make updating an old design very painful (BTDT). HDL's on the other hand only need a text editor to access and modify the design's source. You will still need a compiler to convert the source to a bit stream of course. All of the other claims to an HDL's superiority are suspect at best, and in most cases just pure marketing hogwash. Here are a few of the more common ones: Portability between devices/technologies: This is great as long as you keep the design at an abstract enough level to make it work. Doing this avoids using all the device's architectural features so you wind up with a hopelessly slow and large design. Instantiation of the device features can be easily done of course, but a well developed schematic library does the same thing. I've translated designs between technologies in schematics, and it is not very painful if the schematic is hierarchical and the partitioning between hierarchical blocks is logical. Design readability: proponents of thsi argument all seem to imply that schematics are flat and HDLs are hierarchical. A schematic can be easily made hierarchical so that no single schematic is more than a single page (this is the way I do mine). Proper partitioning makes a very readable design. On the otherhand, I have seen some absolutely terrible VHDL code that while not flat, might just as well been. I am still a believer in the age-old adage that a picture is worth a thousand words. For those who argue that state machines are easier to read in HDL, there are methods to make a schematic machine readable as well. For one-hot machines, the symbols for the components can be set up to resemble a flowchart. for encoded machines, the machine can be represented as a mux and register so that the next state is directly readable. Comments are easy to use in HDLs: and they should be or no one will ever follow the code. A well drawn schematic rarely needs comments. Refer to the picture=1000 words note above. HDL and synthesis makes for a push button solution: Using the push button solution removes the designer from the loop. The result is poor implementation of the design due to the synthesizer's not so hot abilities in partitioning the design and synthesizing the logic. Many of the synthesis engines have many controls over the style of synthesis. Unfortunately, these controls tend to have global influence over the design, and the effects are not necessarily intuitive. THe synthesis results also vary from tool to tool. As you can see, (and many of you already know this) I am not a big fan of HDLs at the current time, mostly because the control over the implementation in the current tools is not as complete or as intuitive as those controls applied in schematic entry. Give me that control, and I think the two real advantages stated above would tip the balance in favor of HDLs. For now, however, I can get to the desired performance and logic density faster using schematic entry, and since I get paid to get a working design, that means I either earn more money by doing more designs or have a little extra time to devote to my wife and kids or to flying (which is where the extra money part comes in). -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 8840
Johannes Sølhusvik wrote: > > Can anyone guide me with the design of a 3-staged pipelined multiplier > in VHDL that is optimised for Xilinx 4000XL series ? > > -- > Johannes Sølhusvik, PhD, Electronic Systems > ABB Corporate Research Centre, Norway > Tel: +47 66 84 34 28, Email: jso@nocrc.abb.no How many bits and what's the clock rate? Makes a big difference in the best implementation, and the level of instantiation required.Article: 8841
Hi, If you are using Synopsys, you can instantiate a 3stage multiplier from DesignWare. It is defined in Advance Math components in library DW02. You can check the use of this component for component instantiation or through "*" operator using --pragma map_to_operator in the DesignWare manual. Addie Tang Department of Electronic Engineering EDA Centre City University of Hong Kong Johannes Sølhusvik wrote: > Can anyone guide me with the design of a 3-staged pipelined multiplier > in VHDL that is optimised for Xilinx 4000XL series ? > > -- > Johannes Sølhusvik, PhD, Electronic Systems > ABB Corporate Research Centre, Norway > Tel: +47 66 84 34 28, Email: jso@nocrc.abb.noArticle: 8842
Hi, there. I'd like to buy a basic development system for FPGA, can anybody give me some suggestion which system I should buy? Thanks in advance. GuFeng engp7604@leonis.nus.sg -- ------------------------------------------------------------------------------- GuFeng Electrical Engineering Dept. National University of Singapore Tel:771-5252 email: engp7604@leonis.nus.sg gufeng@ee.nus.sg -------------------------------------------------------------------------------Article: 8843
Good summary, IMHO. I would have said that an HDL results in a more readable source when used for designs which are "random" in nature, e.g. decoder-heavy stuff, and encoded state machines are certainly in that category. One of the "problems" with schematics is that for some years now the trend has been to generate a huge number of small sheets. I have seen very few designs that really have such a huge number of functionally separate portions, so the sheet division tends to be unnecessary, and people spend lots of time inventing names for signals, just so they can connect them from one sheet to the next. The result is a unreadable schematic. I think one reason for this trend is the fact that many designers don't have access to a decent A3/A2 hard copy device, e.g. a plotter. I have seen ASIC design offices, with 10 people doing ASICs, and their sole hard copy device is an A4 laser. This is stupid. Also, not many people want to take care to draw a neat schematic these days. They rather throw a few gates on a piece of paper, and a few more gates on another piece of paper. Especially if they are full-time employed. Drawing a schematic so it is readable takes a bit of dedication, and most people can't do it well. A while ago I did a design which filled a XC3090. This went nicely on about five A3 sheets, each of which was entirely readable, although if I was passing it to a customer I would have plotted it on A2 sheets. Some time before that, I was on a project, of similar complexity, which was designed on about 50 A4 sheets, filling a ring binder, and most of it was incomprehensible. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiXYZserve.com but remove the XYZ.Article: 8844
Hi,
I'm just curious of how big a step there is from FPGA to ASIC? I
cnostatntly hear that ASIC is so much harder, but is that just to
protect the ASIC-designers postions?
I can accept that there is some added difficulty, but how hard can it
really be? After doing a few FPGA designs (1-3) and taking a week
course in ASIC design, would I be ready?
Homann
--
Magnus Homann Email: d0asta@dtek.chalmers.se
URL : http://www.dtek.chalmers.se/DCIG/d0asta.html
The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 8845Peter from x said: : Good summary, IMHO. : : I would have said that an HDL results in a more readable source when : used for designs which are "random" in nature, e.g. decoder-heavy : stuff, and encoded state machines are certainly in that category. rk: it's easy to see when a block is done in the "wrong" methodology: when you're drawing a schematic to understand some vhdl or when you're writing an equation or making a flow chart to understand a schematic. peter: : One of the "problems" with schematics is that for some years now the : trend has been to generate a huge number of small sheets. rk: fast, cheap laser "a-sized" laser printers on the desktop. while b-sized sheets fit relatively nicely onto this format and with some care are readable, d-sized sheets are an eye-chart with reference designators often unreadable. while moderately priced d-sized plotters are available with ink jet technology (i.e., designjet 200 series from hp) that are much faster then their mechanical arm pen plotter predecessors, it still takes a lot of time to plot out a drawing set. depending on the design, i find i do about half in all d-sized and half in all b-sized. peter: : I have seen very few designs that really have such a huge number of : functionally separate portions, so the sheet division tends to be : unnecessary, and people spend lots of time inventing names for : signals, just so they can connect them from one sheet to the next. The : result is a unreadable schematic. rk: seen too many designs done with small clusters of gates, 2 or 3 in a bunch, no logical flow at all. very unreadable. on the other hand, in my opinion, every macro instance and net should be visibly named. then, when using the drc, timing analysis, manual placement, and in-circuit debugging tools, it's much easier to proceed faster, without having to search for the invisible identifiers that the cae system does apply. a bit of work and a pain up front but for any significant design i find it worth the effort. now when designing with an hdl or macro generator, frequently i'll use the schematic generator to make a schematic out of it and depending on which tool is used, it can be either tolerable with a bit of work or a total mess. with no net names and reference designators specified, the timing path identified by the timing analyzer as too long is a pain to find quickly, especially if the schematic generation is done in levels. and if using in circuit probing, it's much easier to proceed quickly from a well-drawn, well-labelled schematic. peter: <snip> : Also, not many people want to take care to draw a neat schematic these : days. They rather throw a few gates on a piece of paper, and a few : more gates on another piece of paper. Especially if they are full-time : employed. Drawing a schematic so it is readable takes a bit of : dedication, and most people can't do it well. it takes a bunch of time to generate a schematic. and the engineers workload is increasing. it wasn't too long ago when we could sketch a schematic by hand on a d-sized piece of paper (much faster than *ANY* of the cae tools) and the draftsman would either draw it or enter into the system and maintain it when the engineer marked it up. and now we have secretaries that won't answer the phone, won't order supplies, won't type papers, won't do the mail, won't photocopy, won't fax ... ------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 8846
In article <34d8731a.71748198@news.netcomuk.co.uk>, Peter <z80@ds.com> writes [good stuff snipped from Peter and Ray] >I think one reason for this trend is the fact that many designers >don't have access to a decent A3/A2 hard copy device, e.g. a plotter. >I have seen ASIC design offices, with 10 people doing ASICs, and their >sole hard copy device is an A4 laser. This is stupid. Just as a aside, if you are using Windoze, look for the Cannon A3 inkjets. I have the BJ230 for exactly this reason, cheap and reasonably fast. There may be one around in colour by now. [and snipped again] Also, on the HDL/schematic stuff, I wouldn't let myself do a real (i.e. used by a customer) C++ program until I understood (at least reasonably well) what the compilers were doing in the background (non-trivial). Now I use it where its appropriate as I do with other languages. My use of HDL will go the same way. Understand its no magic bullet but will help in some cases and may be absolutely necessary in others. I can't see myself leaving schematics completely though. Maybe I'm just old <grin>. (No maybe about it really...). By the way, as for commenting HDL, unless its the gotcha's or general overview my belief is that the code should comment itself as much as possible. Otherwise who's to say that the comments and code agree :). In a way, schematics might benefit more from comments than HDL does. Just my .002p worth -- Steve Goodwin... De-spamming active, remove any _DSPM from addressArticle: 8847
Check at http://www.associatedpro.com/aps bart plackle wrote: > can anyone point out a very good advanced vhdl book > > Kind regards Bart Plackle -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 8848
There are a few try-before-you-buy packages available for free (or a low cost) via the web at http://www.optimagic.com/lowcost.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Gu Feng wrote in message <6b17pj$j52@nuscc.nus.sg>... >Hi, there. > >I'd like to buy a basic development system for FPGA, can anybody give me >some suggestion which system I should buy? > >Thanks in advance. > >GuFeng > >engp7604@leonis.nus.sg > > >-- >--------------------------------------------------------------------------- ---- >GuFeng >Electrical Engineering Dept. >National University of Singapore >Tel:771-5252 >email: engp7604@leonis.nus.sg gufeng@ee.nus.sg >--------------------------------------------------------------------------- ---- >Article: 8849
I like one called "HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog" by Douglas J. Smith. ISBN 0-9651934-3-8. Also see http://www.doone.com/hdl_chip_des.html and http://www.amazon.com/exec/obidos/ISBN=0965193438/9196-2112036-285223 to order it via Amazon.com. There are other books on VHDL, Verilog, and FPGA design listed at http://www.optimagic.com/books.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Xiao Wang wrote in message <34D18B9F.44B1@umr.edu>... >I'm just beginning to study Verilog or VHDL. > >Is there any difference between these two names? > >What will be the very suitable introductory book for this Verilog and/or >VHDL? Thanks. > >Please email back: xiao@umr.edu
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z