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Messages from 8875

Article: 8875
Subject: Re: combining Altera .sof files
From: Rune Baeverrud <r@acte.no>
Date: Wed, 04 Feb 1998 09:24:45 +0100
Links: << >>  << T >>  << A >>
Jim,

> Does anyone know of a way to combine Altera .sof files, pipe them
> into maxplus2 and generate an .rbf file.

Not quite - but I know of an alternative approach which might suit you:

Max+Plus II generates a sequential .ttf (Tabular Text File) file during
every project compile. (Go ahead, you will find it in your project
directory). This is an easy to read, comma-separated text file which
should be easy to convert to an .rbf (Raw Binary File) file.

If you do write such an utility - I would appreciate if you posted it to
the FreeCore Library at http://193.215.128.3/freecore.

Regards,
Rune Baeverrud
Article: 8876
Subject: Re: FPGA/ASIC - same difference?
From: z80@ds.com (Peter)
Date: Wed, 04 Feb 1998 11:03:16 GMT
Links: << >>  << T >>  << A >>
Peter,

True, but a few comments if I may:

>For the ASIC, you or somebody else must develop a custom test program
>specifically for your design. ASICs are custom circuits and cannot be
>tested before they are customized.
>You don't have that problem with an FPGA. You know that the manufacturer
>has tested that chip thoroughly, throwing a million ( or more ) test
>vectors at it.

You are mixing-up the need to test the FPGA *silicon* with the need to
test the FPGA *design*.

One can test an ASIC with the same unit-delay test vectors which were
used to simulate the FPGA design. I have done this, and it works very
well. It is also a highly safe way to do ASICs, because one can use
those same ex-FPGA test vectors to verify the design on the ASIC
vendor's machine before going to silicon.

The days of slaving over the manual generation of thousands of test
vectors are over. In fact this used to be the most time-consuming part
of many ASIC projects.

>And there is economics. You ( or your employer ) must pay for the
>non-recurring engineering charges that pay for creating the custom mask
>( set) and the specialized testing.
>FPGAs have none of that cost.

There are FPGA->ASIC conversion firms who will do the NRE for a few
thousand bucks.

>Then there are more subtle points: Who pays for your mistakes ? Who pays
>for a mid-life design change? Who pays when you ordered too many of too
>few parts?

Very true, except for the mid-life design change bit. If "mid-life" is
say 5 years later, it is possible that the FPGA originally used is no
longer available. Or, in the case of Xilinx, it may still be available
but in a superset version, which is OK, except that some designs,
relying on e.g. long lines for clock distribution (recommended by
Xilinx engineers as perfectly good practice not many years ago) may no
longer work.

>And there is a new wrinkle:
>IC processing is advancing very fast, and FPGAs are at the cutting edge
>of this progress. Does your ASIC supplier offer 0.25 micron technology? 
>I am just now designing a frequency counter, and the resolution is well
>above 300 MHz ( worst case ), using an XC4000XL FPGA.Just some
>thoughts...Peter Alfke, Xilinx Applications

Indeed, but the vast majority of FPGA/ASIC applications are nowhere
near the cutting edge. Lots of people are doing ASICs (or FPGAs) that
run at 5MHz.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8877
Subject: Re: FPGA/ASIC - same difference?
From: Ed McCauley <zzNOSPAMBottomLine@eclipse.net>
Date: Wed, 04 Feb 1998 09:27:18 -0500
Links: << >>  << T >>  << A >>
Magnus:

To add the icing to what Peter has said:

Along with today's advance process technologies offered by FPGAs, by using
an FPGA the designer is almost assured that they will ALWAYS be using chips
created with leading edge processes.  This means that the cost of an FPGA
will continue to drop over time while that of an ASIC remains constant due
to its unchanging fabrication process.  If challenged that true ASICs are
cheaper than FPGAs; remember, usually that's not the case long term
especially when all the costs are accounted for.

Regarding Tom Coonan's input:

Mega dittos!  Design as if you're targeting an ASIC and you'll LOVE
FPGAs.... CYA technology!  Keep it Synchronous, use simulation and static
timing analysis, and design hierarchically!

Best wishes


PS: Peter, It was nice to see you last week, Next time I'd like to spend
more time with you!

--
Ed McCauley
Lancair IV-P
President
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA
            (908) 996-0817
FAX:   (908) 996-0817



Article: 8878
Subject: info on VHDL simulators
From: deepu@wavelet.ee.vill.edu (Deependra Talla)
Date: 4 Feb 1998 16:28:49 GMT
Links: << >>  << T >>  << A >>

Hi,
        Please can anyone refer me to any websites/books that have information
on VHDL simulators. I am specifically looking for as to how they are
implemented. Particularly Mentor QuickHDL/VHDL simulator. I am interested in
finding out as to how much simulation time it takes for a model to be simulated.
For example we can say that a highly abstract model simulates faster than a
fully functional model because the simulator executes far less number of
instructions. I want to know how exactly we can come to know of the number of
simulation cycles..

        Any help in this matter would be greatly appreciated.
        
Thanks,
Deepu



~~~~~~~~~~~~~~~~~~~~ deepu@ece.vill.edu ~~~~~~~~~~~~~~~~~~~~~~~~~~~
| Deepu Talla              | If it is not necessary to change     | 
|                          |    it is necessary not to change ... |
| Phone: (610)225-0243 (R) |                                      |
|        (610)519-7371 (O) | whatever, whoever, wherever, whenever|
~~~~~~~~~~~~~~~~ http://www.ece.vill.edu/~deepu ~~~~~~~~~~~~~~~~~~~
Article: 8879
Subject: Re: can u give me some advice?
From: Steven Groom <arrownz@ihug.co.nz>
Date: Thu, 05 Feb 1998 08:05:08 +1300
Links: << >>  << T >>  << A >>
Gu Feng wrote:

> Hi, there.
>
> I'd like to buy a basic development system for FPGA, can anybody give me
> some suggestion which system I should buy?

Just to start off, you don't need to buy anything - check out Altera's website
www.altera.com and download PLS-WEB

Alternatively, contact your Altera distributor for a CD copy.

Regards,

Steve.


Article: 8880
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Links: << >>  << T >>  << A >>
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Article: 8881
Subject: Re: VHDL vs schematics
From: dark7room@ix.netcom.com (Austin Franklin)
Date: Wed, 4 Feb 1998 22:35:29 -0500
Links: << >>  << T >>  << A >>
>  I am not sure there is a big difference.  You *can* do in VHDL absolutely
>  the same design that you do in schematic (i.e. write a netlist).  The
>  only difference is that VHDL will be more portable and easier to
>  simulate.  OTOH, you will need a schematic to understand what you wrote
>  in VHDL.
> 
> 
>  So-called "behavioral" VHDL description comes down to 2-3 sequential
>  statements that the synthesis tool is able to understand (and each
>  vendor interprets them in a different way).  No big deal.  

That's simply not true and idealistic.  It is only true if you know 
exactly what the compiler will output for every construct you give it.  
You DO NOT have the control or consistency with HDLs as you do with 
schematics.

I have had one rev of a compiler generate one output, and a different rev 
generate a completely different output.  That is part and parcel for 
compilers, whether it be C or VHDL, as there is NO universal 
specification on how to do the generation.

You are at the mercy of what the compiler generates, and you 'may' have 
to play games with it in order to get it to generate the output YOU 
'think' it should.  If you become an 'expert' on ONE compiler, and one 
revision, you loose your 'expert-ship' when using another compiler, and 
possibly another revision of that same compiler!

Austin Franklin
darkroom@ix.netcom.com
Article: 8882
Subject: Re: VHDL vs schematics
From: dark7room@ix.netcom.com (Austin Franklin)
Date: Wed, 4 Feb 1998 22:39:01 -0500
Links: << >>  << T >>  << A >>
> 
> You can get the structure you need to get the desired performance and
> density using an HDL, but you will likely have to resort to low level
> instantiation and a host of extra attributes to control placement. 
> Effectively, this is writing a textual description of the schematic. 
> The current HDL synthesis tools really don't provide enough control over
> the design implementation to quickly, reliably and successfully turn out
> high performance designs.  Hopefully the CAE vendors will fix this soon,
> but I am not holding my breath.

I agree completely, and it will get better...as C compilers have...but 
there is still a need to to some assembly code in certain 
situations...but I don't believe it will get soooo good that it will 
override the need for schematics in cutting edge designs.

Also, as with C, faster processors have 'hidden' the poor performance, as 
faster FPGAs will do for HDLs...

Austin Franklin
darkroom@ix.netcom.com
Article: 8883
Subject: Re: VHDL vs schematics, I vote for VHDL and this is why...
From: dark7room@ix.netcom.com (Austin Franklin)
Date: Wed, 4 Feb 1998 22:45:24 -0500
Links: << >>  << T >>  << A >>
In article <886531024.3145738@dejanews.com>, husby@fnal.gov says...
> One can see the appeal of HDL, since I couldn't post the schematic
> here, 

Output to a postscript file and post the file as an attachment ;-)

Austin
Article: 8884
Subject: Xilinx and Altera CPLDs in JTAG chain
From: Kayvon Irani <kirani@cinenet.net>
Date: Thu, 05 Feb 1998 00:08:10 -0800
Links: << >>  << T >>  << A >>
    Hi:

    I have an application that uses ISP CPLDs from both Altera and
Xilinx,
    I'd like to program these parts through ONE JTAG port. Has any one
    tried JTAG programming with different vendors in the JTAG chain?

    Regards,
    Kayvon Irani
    Los Angeles, Ca

Article: 8885
Subject: VHDL vs schematics, I vote for VHDL and this is why...
From: Leon Heller <leon@lfheller.demon.co.uk>
Date: Thu, 5 Feb 1998 10:12:30 +0000
Links: << >>  << T >>  << A >>
In article <MPG.f42ffde7062a97f9896d2@nntp.ix.netcom.com>, Austin
Franklin <dark7room@ix.netcom.com> writes
>In article <886531024.3145738@dejanews.com>, husby@fnal.gov says...
>> One can see the appeal of HDL, since I couldn't post the schematic
>> here, 
>
>Output to a postscript file and post the file as an attachment ;-)
>
>Austin

Please *DO* *NOT* do this. Binaries and images should *NOT* be posted to
newsgroups.

Leon
-- 
Leon Heller: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk
Amateur Radio Callsign G1HSM    Tel: +44 (0) 118 947 1424
See http://www.lfheller.demon.co.uk/dds.htm for details of my AD9850
DDS system. See " "/diy_dsp.htm for a simple DIY DSP ADSP-2104 system.
Article: 8886
Subject: Can XACT6 run in a NT4 DOS box?
From: z80@ds.com (Peter)
Date: Thu, 05 Feb 1998 11:26:27 GMT
Links: << >>  << T >>  << A >>
Just wondered. There is the dongle which is the main problem.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8887
Subject: Re: Can XACT6 run in a NT4 DOS box?
From: Ed McCauley <zzNOSPAMBottomLine@eclipse.net>
Date: Thu, 05 Feb 1998 08:06:53 -0500
Links: << >>  << T >>  << A >>


Peter wrote:

> Just wondered. There is the dongle which is the main problem.
>
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to z80@digiXYZserve.com but
> remove the XYZ.

 Peter:

Yes, it can.  You just need to install the rainport driver.  We've been
doing it (running XACT:XDM,PPR,and XDE (full screen)) for a year now.

One BIG note however, we find it faster to reboot in DOS mode, run what
we have to and then re-boot back to NT4.  For some reason several of the
Xilinx programs, makebits for example, take 10 times the amount of run
time under NT.  We have tweaked the DOS idle time and increased the
task's priorety with little or no impact on this problem.

--
Ed McCauley
President
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA
            (908) 996-0817
FAX:   (908) 996-0817


Article: 8888
Subject: Re: Xilinx and Altera CPLDs in JTAG chain
From: landowsk@eda.mke.ab.com (Roger Landowski)
Date: 5 Feb 1998 13:32:31 GMT
Links: << >>  << T >>  << A >>
Yes, I have programmed Altera EPM7128's and Vantis MACH211's in the same chain along 
with other JTAG parts, (Xilinx FPGA's and buffers). The programming utility from
the CPLD vendor will put the other parts in the Bypass state, you will have to 
provide a minimal amount of information about the other parts to the programming
utility so it knows how long the chain is.

Roger Landowski
Sr. Project Engineer
Allen-Bradley Milwaukee


Article: 8889
Subject: Re: VHDL vs schematics, I vote for VHDL and this is why...
From: husby@fnal.gov
Date: Thu, 05 Feb 1998 08:51:41 -0600
Links: << >>  << T >>  << A >>
husby@fnal.gov says...
> One can see the appeal of HDL, since I couldn't post the schematic
> here,

dark7room@ix.netcom.com (Austin Franklin) wrote:
> Output to a postscript file and post the file as an attachment ;-)

You're assuming that I have access to a sensible news server.
That seems like a reasonable assumption, since I work at a major
U.S. National Lab that has over 1000 scientists and engineers.
Unfortunately, the folks here don't seem to be able to maintain
a decent news server.  I have to use Deja-News to post articles,
and it won't take attachments.

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 8890
Subject: Job Posting: FPGA Video Processing
From: Steve Nordhauser <nords@intersci.com>
Date: 5 Feb 1998 08:58:01 -0700
Links: << >>  << T >>  << A >>
InterScience, Inc., a contract research and development company
in Upstate New York is seeking a digital hardware engineer with 
experience in FPGA design using VHDL and/or schematic.  Applications
include real time video processing and control systems.  Enjoy
a small company atmosphere while participating in state-of-the-art
research.

Experience in any of the following is a plus:
Microprocessor hardware and software
C or C++ programming
Analog design
Data acquisition
Printed circuit board layout

For further information, contact:
Steve Nordhauser
Embedded Systems Manager
InterScience, Inc.
105 Jordan Road
Troy, NY 12180

Phone: (518) 283-7500
Fax:   (518) 283-7502
Email: nords@intersci.com
Web:   http://www.intersci.com
Article: 8891
Subject: Q: Workview Office and M1
From: Erik Lins <Erik.Lins@exp2.physik.uni-giessen.de>
Date: Thu, 05 Feb 1998 17:07:27 +0100
Links: << >>  << T >>  << A >>
Hello,

I'm trying to use Workview Office together with Xilinx M1 and I have
some problems.
I entered a very small design with ViewDraw: Two IPADs followed by two
IBUFs followed by and AND2.1 followed by an OBUF, followed by an OPAD.
When I do a design rule check with ViewDraw, some error messages occur:
PinType: Error: - spn IBUF.I: Invalid pin type: CHIPIN
PinType: Error: - spn OBUF.O: Invalid pin type: CHIPTRI
InvalidGlobal: Error: XC4000E: OBUF net GTS: Global net name not listed
                                             in legal_blobals
PinMatch: Error: XC4000E: OBUF net GTS: PINTYPE mismatch -- symbol=IN,
                                        schematic=OUT

Nevertheless I can produce a netlist without errors as well as an EDIF
netlist, which I can read with M1 Design Manager. When I start the
implementation process I get the following error messages in the Map
Report File:

ERROR:basnu - logical block "$1I3/$1I3" of type "DELAY" is unexpanded.
ERROR:basnu - logical block "$1I6/$1I3" of type "DELAY" is unexpanded.
ERROR:basnu - logical block "$1I6/$1I13" of type "AND2" is unexpanded.
ERROR:basnu - logical block "$1I6/$1I1" of type "DELAY" is unexpanded.
ERROR:basnu - logical block "$1I1/$1I3" of type "DELAY" is unexpanded.
ERROR:basnu - logical block "$1I2/$1I3" of type "DELAY" is unexpanded.

I didn't find any comments on this in the documentation, has anybody an
idea ? Has anybody had the same problem ?
The M1 libraries seem to be correct installed, the license files are ok,
the libs.lst file is ok and the environment variables seem to be ok,
too. We installed the software on another PC, but it's exactly the same.
When I open one of the Workview Office example files (like COUNT4S), I
get almost the error messages with ViewDraw and with M1.
BTW: I'm running Windows NT4

Erik
Article: 8892
Subject: Re: Can XACT6 run in a NT4 DOS box?
From: Jeff <me@home.sleeping>
Date: Thu, 05 Feb 1998 11:51:46 -0600
Links: << >>  << T >>  << A >>
Peter wrote:
> 
> Just wondered. There is the dongle which is the main problem.
> 
> Peter.
> 
> Return address is invalid to help stop junk mail.
> E-mail replies to z80@digiXYZserve.com but
> remove the XYZ.

Currently XACT will not run on NT.  Xilinx says it won't, but
we tried anyway ... surprise! It didn't work!

Anyway, With the release of M1 software (which does run on NT),
Xilinx no longer supports XACT.  The problem I have with this
is that we have many, many application specific boards installed
that use old XC3090's.  Once in a while we have to make a
tweak to an FPGA config file.  Unfortunately, M1 does not
support the old 3090's.  And, since all of our engineering
computers now have NT loaded on them ... I'm hosed!

This means I must keep an old machine with for XACT and do
all new development on an NT using M1.  The problem with
this is that this really isn't legal!  One license, two 
machines.

WHAT CAN I DO?   Awwwww, come on Xilinx -- add the capability
to compile old 3000's on M1!!!

Oh well, enuf whining
-- Jeff
Article: 8893
Subject: Re: Can XACT6 run in a NT4 DOS box?
From: Ed McCauley <zzNOSPAMBottomLine@eclipse.net>
Date: Thu, 05 Feb 1998 13:12:35 -0500
Links: << >>  << T >>  << A >>
Jeff:

Refer to XCELL Q496 page 20.  The XACT (sorry!) directions are there....
it does work under NT4, we've been "doing it" for over a year.

All of our systems at Bottom Line are dual boot, that is: on re-boot we
tell the machine to boot NT4 or Win311.

FYI: We keep the C: drive a FAT partition and install our Win16, DOS and
Xilinx SW there.  Thus we stay within the"law" and have optimal
invironments for both tool sets.

Best wishes.  If you can't find the copy of XCELL, give us a call and
I'll fax you the needed info.


--
Ed McCauley
Lancair IV-P
President
Bottom Line Technologies Inc.
Specializing Exclusively in Xilinx Design, Development and Training
Voice: (500) 447-FPGA
       (908) 996-0817
FAX:   (908) 996-0817


Article: 8894
Subject: Re: Can XACT6 run in a NT4 DOS box?
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 5 Feb 1998 18:39:14 GMT
Links: << >>  << T >>  << A >>
In article <34D9FC32.32F0@home.sleeping> Jeff <me@home.sleeping> writes:
>
>Currently XACT will not run on NT.  Xilinx says it won't, but
>we tried anyway ... surprise! It didn't work!

Well, actually it does. Although two programs (WIR2XNF and MAKEBITS) run 
much slower than in real DOS, the rest of the programs you need run
fine in a DOS box under NT. (XNFMERGE, XNFPREP, PPR, XDELAY).

I have had this running with both NT 4.0, and NT4.0+SP3

To be able to run the software, you need a driver that allows the
software to see the stupid dongle, under NT. It is called the RAINPORT
driver, and you can get it at:

http://www.rnbo.com/tech/drivers/drivers.htm

or something similar. (old address that I havent checked recently)

Once you have installed it you can check that it is working by
opening a DOS box, and typing the command:

	xkey -r

And it should give you some info like:

xkey [5.2.1] --  Xilinx Automatic CAE Tools
Copyright (c) 1996 Xilinx Inc.  All Rights Reserved.

Key Serial #: C98761234

Feature Name         Authorization Status
-------------------  --------------------
XDE                  Authorized for XACT
APR                  Authorized for XACT
PPR                  Authorized for XACT
XBLOX                Authorized for XACT
XABEL                Authorized for XACT
VLS-STD              Authorized for XACT
XACT8000             37050 evaluation runs left
XABLCPLD             274350 evaluation runs, but why would you be using a CPLD
FOUNDATION           49 evaluation runs, tried it once, didn't like it
X-VHDL               50 evaluation runs, or use schematic 
Done.


>
>Anyway, With the release of M1 software (which does run on NT),
>Xilinx no longer supports XACT.  The problem I have with this
>is that we have many, many application specific boards installed
>that use old XC3090's.  Once in a while we have to make a
>tweak to an FPGA config file.  Unfortunately, M1 does not
>support the old 3090's.  And, since all of our engineering
>computers now have NT loaded on them ... I'm hosed!

Not so. Either run the Xact step software as described above,
or if you check the recently released M1.4 release, you will find
that XC3000A, XC3100, and XC3100A are now all supported. Since the
'A' series parts have extra pips in them that you existing chips on
boards dont have, you should probably select XC3190 as your target
chip, and hopefully, there is a matching speed grade.

>
>This means I must keep an old machine with for XACT and do
>all new development on an NT using M1.  The problem with
>this is that this really isn't legal!  One license, two 
>machines.

If anyone asks, just tell them you deinstalled M1 from your NT machine
while you were running on you DOS machine,

or

run it in a DOS box , as above

or

use M1 to do XC3190 designs

or

Check out a really neat program called System Commander, that allows
booting multiple operating systems on the one machine. A utility I
could not live without, and only $69.95 at Fry's.

>WHAT CAN I DO?   Awwwww, come on Xilinx -- add the capability
>to compile old 3000's on M1!!!

Hope fully one of my sugestions will help you.

>
>Oh well, enuf whining
>-- Jeff

Nah, keep whining, it makes for interesting articles.


Philip Freidin



Article: 8895
Subject: Re: Q: Workview Office and M1
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 5 Feb 1998 18:46:56 GMT
Links: << >>  << T >>  << A >>

This one is easy. When you run the EDIF netlister, you need to type the
text "xilinx" in the box labeled "level". Given how often I have seen this
missteake happen, is seems crazy that Xilinx doesnt do a better job of
identifying it and giving you help. When you leave out the level parameter,
the netlister traverses all the way to the bottom of the hierarchy, and 
writes out a net list of simulation primatives, which is one level too far.

Philip Freidin


In article <34D9E3BF.4E0C@exp2.physik.uni-giessen.de> Erik.Lins@exp2.physik.uni-giessen.de writes:
>Hello,
>
>I'm trying to use Workview Office together with Xilinx M1 and I have
>some problems.
>I entered a very small design with ViewDraw: Two IPADs followed by two
>IBUFs followed by and AND2.1 followed by an OBUF, followed by an OPAD.
>When I do a design rule check with ViewDraw, some error messages occur:
>PinType: Error: - spn IBUF.I: Invalid pin type: CHIPIN
>PinType: Error: - spn OBUF.O: Invalid pin type: CHIPTRI
>InvalidGlobal: Error: XC4000E: OBUF net GTS: Global net name not listed
>                                             in legal_blobals
>PinMatch: Error: XC4000E: OBUF net GTS: PINTYPE mismatch -- symbol=IN,
>                                        schematic=OUT
>
>Nevertheless I can produce a netlist without errors as well as an EDIF
>netlist, which I can read with M1 Design Manager. When I start the
>implementation process I get the following error messages in the Map
>Report File:
>
>ERROR:basnu - logical block "$1I3/$1I3" of type "DELAY" is unexpanded.
>ERROR:basnu - logical block "$1I6/$1I3" of type "DELAY" is unexpanded.
>ERROR:basnu - logical block "$1I6/$1I13" of type "AND2" is unexpanded.
>ERROR:basnu - logical block "$1I6/$1I1" of type "DELAY" is unexpanded.
>ERROR:basnu - logical block "$1I1/$1I3" of type "DELAY" is unexpanded.
>ERROR:basnu - logical block "$1I2/$1I3" of type "DELAY" is unexpanded.
>
>I didn't find any comments on this in the documentation, has anybody an
>idea ? Has anybody had the same problem ?
>The M1 libraries seem to be correct installed, the license files are ok,
>the libs.lst file is ok and the environment variables seem to be ok,
>too. We installed the software on another PC, but it's exactly the same.
>When I open one of the Workview Office example files (like COUNT4S), I
>get almost the error messages with ViewDraw and with M1.
>BTW: I'm running Windows NT4
>
>Erik


Article: 8896
Subject: Off topic...Netiquite and Emoticons WAS Re: VHDL vs schematics, I vote for VHDL and this is why...
From: dark7room@ix.netcom.com (Austin Franklin)
Date: Thu, 5 Feb 1998 14:07:44 -0500
Links: << >>  << T >>  << A >>
In article <EMklVUBOCZ20EwJm@lfheller.demon.co.uk>, 
leon@lfheller.demon.co.uk says...
> In article <MPG.f42ffde7062a97f9896d2@nntp.ix.netcom.com>, Austin
> Franklin <dark7room@ix.netcom.com> writes
> >In article <886531024.3145738@dejanews.com>, husby@fnal.gov says...
> >> One can see the appeal of HDL, since I couldn't post the schematic
> >> here, 
> >
> >Output to a postscript file and post the file as an attachment ;-)
> >
> >Austin
> 
> Please *DO* *NOT* do this. Binaries and images should *NOT* be posted to
> newsgroups.

Didn't you notice the little smiley face at the end of my comment?  Well 
for those of you who are humor impared, IT WAS MEANT AS A JOKE!  The 
smiley face is called an 'emoticon' and means the preceding was meant to 
be funny.

Geeze...

anyways...there are newsgroups that are nothing but binaries, so your 
little netiquite 'rule' isn't quite correct...  Personally, I don't have 
any problem with simeone posting a small attachment in ANY newsgroup if 
it is part of the discussion...

Funny though, I've noticed a few people from the UK complain about this 
exact subject....you guys must have bad ISPs or software there because it 
really makes no difference to my and my news reader, I only download the 
headers...and I can see how big a post is, and can choose NOT to download 
it if I don't want to...and I don't pay by the byte....or by the time, 
just flat fee for unlimited net access...

Austin

Article: 8897
Subject: Re: Off topic...Netiquite and Emoticons WAS Re: VHDL vs schematics, I vote for VHDL and this is why...
From: "Richard Iachetta" <iachetta@us.ibm.com>
Date: 5 Feb 1998 20:36:52 GMT
Links: << >>  << T >>  << A >>
Austin Franklin <dark7room@ix.netcom.com> wrote in article
<MPG.f43d7e6b94209aa9896d6@nntp.ix.netcom.com>...
> In article <EMklVUBOCZ20EwJm@lfheller.demon.co.uk>, 
> leon@lfheller.demon.co.uk says...
> > In article <MPG.f42ffde7062a97f9896d2@nntp.ix.netcom.com>, Austin
> > Franklin <dark7room@ix.netcom.com> writes
> > >In article <886531024.3145738@dejanews.com>, husby@fnal.gov says...
> > >> One can see the appeal of HDL, since I couldn't post the schematic
> > >> here, 
> > >
> > >Output to a postscript file and post the file as an attachment ;-)
> > >
> > >Austin
> > 
> > Please *DO* *NOT* do this. Binaries and images should *NOT* be posted to
> > newsgroups.
> 
> Personally, I don't have 
> any problem with simeone posting a small attachment in ANY newsgroup if 
> it is part of the discussion...

I agree.  Postscript is just ASCII anyway.

Article: 8898
Subject: Re: Off topic...Netiquite and Emoticons WAS Re: VHDL vs schematics, I vote for VHDL and this is why...
From: "rk" <stellare@erols.com.NOSPAM>
Date: 5 Feb 1998 20:50:54 GMT
Links: << >>  << T >>  << A >>
austin:
: > >Output to a postscript file and post the file as an attachment ;-)

leon:
: > Please *DO* *NOT* do this. Binaries and images should *NOT* be posted
to
: > newsgroups.


austin: 
: Didn't you notice the little smiley face at the end of my comment?  Well 
: for those of you who are humor impared, IT WAS MEANT AS A JOKE!  The 
: smiley face is called an 'emoticon' and means the preceding was meant to 
: be funny.
: 
: Geeze...
: 
: anyways...there are newsgroups that are nothing but binaries, so your 
: little netiquite 'rule' isn't quite correct...  Personally, I don't have 
: any problem with simeone posting a small attachment in ANY newsgroup if 
: it is part of the discussion...

rk:
i don't think there's anything wrong w/ posting attachments as the purpose
of this thing is supposed to be communication, and drawing schematics w/
ascii art is kind of a pain.  i know other newsgroups like to limit
attachments to 10k or less for most posts, <20k as a general rule.  if you
download at 2 kbytes per second, which isn't very challenging for the
dial-up user (like me), that's 5 to 10 seconds, quite an acceptable amount
of time.  and as long as the attachments are in a standard format (i.e.,
gif, .pdf, etc.) that we can all read, i see nothing wrong with it.

i think it would be good policy to say in the header the format and size of
an attachment, so people can choose whether or not they wish to download
when they open up a message.

--------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------
Article: 8899
Subject: Power consumption
From: Richard Schwarz <aaps@erols.com>
Date: Thu, 05 Feb 1998 16:07:56 -0500
Links: << >>  << T >>  << A >>
I am looking to do a low power design which I would like to implement
on and FPGA. I have to do some syncing, framing, interleaving (requiring
about
10K byrtes SRAM), and 2 uarts. My clock freqs will be less than 5 Mhz. I
have to keep my power well below 90 mW. Is this unrealistic for FPGA and
10K SRAM? Also, any hints or tips or past experiences on low power
designs at all would be greatly appretiated.

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: aaps@erols.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




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