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Messages from 8900

Article: 8900
Subject: Re: can u give me some advice?
From: Richard Schwarz <aaps@erols.com>
Date: Thu, 05 Feb 1998 16:11:01 -0500
Links: << >>  << T >>  << A >>
Check out http://www.associatedpro.com/aps  You can get a XILINX starter
kit with software and hardware for as low as 350.00!! This is the
best/most complete/lowest cost  starter kit available.

Gu Feng wrote:

> Hi, there.
>
> I'd like to buy a basic development system for FPGA, can anybody give
> me
> some suggestion which system I should buy?
>
> Thanks in advance.
>
> GuFeng
>
> engp7604@leonis.nus.sg
>
> --
> --
> ----------------------------------------------------------------------------
>
> GuFeng
> Electrical Engineering Dept.
> National University of Singapore
> Tel:771-5252
> email: engp7604@leonis.nus.sg   gufeng@ee.nus.sg
> ------------------------------------------------
> ------------------------------



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

    Richard Schwarz, President
    Associated Professional Systems Inc. (APS)
    email: aaps@erols.com
    web site: http://www.associatedpro.com
    Phone: 410-569-5897
    Fax:   410-661-2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 8901
Subject: Re: Xilinx and Altera CPLDs in JTAG chain
From: daveb@iinet.net.au (David R Brooks)
Date: Thu, 05 Feb 1998 22:35:36 GMT
Links: << >>  << T >>  << A >>
Kayvon Irani <kirani@cinenet.net> wrote:

:    Hi:
:
:    I have an application that uses ISP CPLDs from both Altera and
:Xilinx,
:    I'd like to program these parts through ONE JTAG port. Has any one
:    tried JTAG programming with different vendors in the JTAG chain?
:
 There is a thread running on the Xilinx Users (XUMA) mailing list,
discussing this & related issues.

 The list-source is xuma@ecla.com


--  Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34
 What's all this? see http://www.iinet.net.au/~daveb/crypto.html
Article: 8902
Subject: Re: Power consumption
From: James Horn <jimhorn@svn.net>
Date: 6 Feb 1998 00:58:02 GMT
Links: << >>  << T >>  << A >>
Hi, Richard -

For *really* low power you might want to try the Philips CoolRunner ICs
(PZ5128 or PZ3128) with an external (inexpensive) CMOS SRAM.  I'd suspect
that with careful implimentation you may be able to the the 128 macrocells
to do the job and both parts would be fairly inexpensive in small
quantities and *very* low power, relatively speaking.

No, I'm not associated with Philips - I've just enjoyed using 'em (and
lots of Altera 7000 series parts, too).

Jim Horn  (jimh@drop-this-part.ncicom.com)
Nusantara Communications, Inc.   707-792-3025


Article: 8903
Subject: Asic to FPGA
From: Lars <larsher@online.no>
Date: Fri, 06 Feb 1998 07:31:47 +0100
Links: << >>  << T >>  << A >>
Hello,
I have an Asic that is going out of production because the vendor is no
longer supporting this process. The design is about 12500 gates (where a
nand gate is 2 gates, a set/reset/scan FF is 12 gates), 160 pins and
runs at 50MHz, made in a 1u process. It is not possible to the chip run
at a higher speed because of all the logic between clocks (Pipelining).
There are many clocks, and a lot of different clears on the FFs. Also
delaylines internally is used. The timing is extremly important, and
must be known. So to my questions:

1) Does an FPGA give you the same control over the design as an Asic
does?
2) Is this a recommended way of going? The alternative is to do another
Asic. We can not afford to use too long time on this. The volum is
pretty low.
Article: 8904
Subject: Re: Can XACT6 run in a NT4 DOS box?
From: Alasdair MacLean <alasdair.maclean@gecm.com>
Date: Fri, 06 Feb 1998 09:03:28 +0000
Links: << >>  << T >>  << A >>
Jeff wrote:
> 
Snip ...
> 
> Anyway, With the release of M1 software (which does run on NT),
> Xilinx no longer supports XACT.  The problem I have with this
> is that we have many, many application specific boards installed
> that use old XC3090's.  Once in a while we have to make a
> tweak to an FPGA config file.  Unfortunately, M1 does not
> support the old 3090's.  And, since all of our engineering
> computers now have NT loaded on them ... I'm hosed!
> 

I've got a similar problem, except in my case I've got some old designs
kicking around with XC4010 (as opposed to XC4010A/E/XL etc.) chips in
them, which need modified. As with the XC3090, there is no support for
the old parts in the new software. The solution is either to replace the
chip with a newer device or keep a machine running the old XACT
software. Neither option is particularly satisfactory.

> This means I must keep an old machine with for XACT and do
> all new development on an NT using M1.  The problem with
> this is that this really isn't legal!  One license, two
> machines.
> 
> WHAT CAN I DO?   Awwwww, come on Xilinx -- add the capability
> to compile old 3000's on M1!!!
>

Ditto for XC4000.
 
> Oh well, enuf whining
> -- Jeff

With a little additional whining from me.
-- 
Alasdair Maclean, Development Engineer,
GEC Marconi Electro-Optics Ltd.,
GNET: 709-5711; Tel: +44 (0)131 343 5711
Fax: +44 (0)131 343 5050
Email: <mailto:alasdair.maclean@gecm.com>
Article: 8905
Subject: Re: VHDL vs schematics, I vote for VHDL and this is why...
From: z80@ds.com (Peter)
Date: Fri, 06 Feb 1998 11:38:45 GMT
Links: << >>  << T >>  << A >>

>Please *DO* *NOT* do this. Binaries and images should *NOT* be posted to
>newsgroups.

Small ones are fine, IMO. Zipped-up, a few-k file is perfectly OK. A
lot of rather ignorant people post their Netscape address cards with
their posts, and there aren't small.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8906
Subject: Re: Q: Workview Office and M1
From: "reno" <falkenberg@stagetec.com>
Date: Fri, 6 Feb 1998 12:48:04 +0100
Links: << >>  << T >>  << A >>
you can customize your ViewDraw 'Tools' menu - so you nether have to bother
about this 'level' definition
- click 'Customize' in your 'Tools' menu, a box appears
- select 'User Menu'
- fill 'Menu Text:' with "create edif xilinx netlist" (e.g.)
- fill 'Command:' with "edifneto.exe"
- fill 'Arguments:' with "-l xilinx $BLOCKNAME"
- push 'Add' and 'OK'
now an extra command should appear in your 'Tools' menu where you can
generate an EDIF netlist from within ViewDraw

good luck
reno:)
falkenberg@stagetec.com


Philip Freidin schrieb in Nachricht ...
>
>This one is easy. When you run the EDIF netlister, you need to type the
>text "xilinx" in the box labeled "level". Given how often I have seen this
>missteake happen, is seems crazy that Xilinx doesnt do a better job of
>identifying it and giving you help. When you leave out the level parameter,
>the netlister traverses all the way to the bottom of the hierarchy, and
>writes out a net list of simulation primatives, which is one level too far.
>
>Philip Freidin
>
>
>In article <34D9E3BF.4E0C@exp2.physik.uni-giessen.de>
Erik.Lins@exp2.physik.uni-giessen.de writes:
>>Hello,
>>
>>I'm trying to use Workview Office together with Xilinx M1 and I have
>>some problems.
>>I entered a very small design with ViewDraw: Two IPADs followed by two
>>IBUFs followed by and AND2.1 followed by an OBUF, followed by an OPAD.
>>When I do a design rule check with ViewDraw, some error messages occur:
>>PinType: Error: - spn IBUF.I: Invalid pin type: CHIPIN
>>PinType: Error: - spn OBUF.O: Invalid pin type: CHIPTRI
>>InvalidGlobal: Error: XC4000E: OBUF net GTS: Global net name not listed
>>                                             in legal_blobals
>>PinMatch: Error: XC4000E: OBUF net GTS: PINTYPE mismatch -- symbol=IN,
>>                                        schematic=OUT
>>
>>Nevertheless I can produce a netlist without errors as well as an EDIF
>>netlist, which I can read with M1 Design Manager. When I start the
>>implementation process I get the following error messages in the Map
>>Report File:
>>
>>ERROR:basnu - logical block "$1I3/$1I3" of type "DELAY" is unexpanded.
>>ERROR:basnu - logical block "$1I6/$1I3" of type "DELAY" is unexpanded.
>>ERROR:basnu - logical block "$1I6/$1I13" of type "AND2" is unexpanded.
>>ERROR:basnu - logical block "$1I6/$1I1" of type "DELAY" is unexpanded.
>>ERROR:basnu - logical block "$1I1/$1I3" of type "DELAY" is unexpanded.
>>ERROR:basnu - logical block "$1I2/$1I3" of type "DELAY" is unexpanded.
>>
>>I didn't find any comments on this in the documentation, has anybody an
>>idea ? Has anybody had the same problem ?
>>The M1 libraries seem to be correct installed, the license files are ok,
>>the libs.lst file is ok and the environment variables seem to be ok,
>>too. We installed the software on another PC, but it's exactly the same.
>>When I open one of the Workview Office example files (like COUNT4S), I
>>get almost the error messages with ViewDraw and with M1.
>>BTW: I'm running Windows NT4
>>
>>Erik
>
>


Article: 8907
Subject: Looking for XC6200 Sw
From: merino@die.upm.es (Pedro Merino Gonzalez)
Date: 6 Feb 1998 15:44:20 GMT
Links: << >>  << T >>  << A >>
Hi there,

We are trying to obtain Xilinx XC6200 software through the Xilinx
University Program, but we haven't any news from them. Has anybody 
got the Synopsys libraries for this FPGA?

Regards.

Pedro.

--
            ///                   \\\
           ( ..)                 (.. )
--------o00-(_)-00o-----------o00-(_)-00o------------------------------
Pedro Merino Gonzalez (PhD. Student of Electrical Engineering)

mail: E.T.S.I. de Telecomunicacion     phone:  (+34 1) 549-5700 x 420
      Dpto. de Ingenieria Electronica  fax:    (+34 1) 336-7323
      Ciudad Universitaria s/n         email:  merino@die.upm.es
      28040 Madrid (Spain)     WWW: -> http://betis.die.upm.es/~merino
-----------------------------------------------------------------------
Article: 8908
Subject: Re: Asic to FPGA
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 6 Feb 1998 18:51:34 GMT
Links: << >>  << T >>  << A >>


FPGAs offer you a lot of benefits, however timing is not one of them.
An altera 10K30 or a xilinx 4013XL should be able to accomodate your design.
If the volume is pretty low and the cost of ASICs is prohibitve I suggest
you relayout your design to make it "FPGA friendly"



In article <34DAAE53.5AB8@online.no>, Lars  <larsher@online.no> wrote:
>Hello,
>I have an Asic that is going out of production because the vendor is no
>longer supporting this process. The design is about 12500 gates (where a
>nand gate is 2 gates, a set/reset/scan FF is 12 gates), 160 pins and
>runs at 50MHz, made in a 1u process. It is not possible to the chip run
>at a higher speed because of all the logic between clocks (Pipelining).
>There are many clocks, and a lot of different clears on the FFs. Also
>delaylines internally is used. The timing is extremly important, and
>must be known. So to my questions:
>
>1) Does an FPGA give you the same control over the design as an Asic
>does?
>2) Is this a recommended way of going? The alternative is to do another
>Asic. We can not afford to use too long time on this. The volum is
>pretty low.


Article: 8909
Subject: Re: Asic to FPGA
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 06 Feb 1998 11:05:03 -0800
Links: << >>  << T >>  << A >>
Lars wrote:

> Hello,
> I have an Asic that is going out of production because the vendor is
> no
> longer supporting this process. The design is about 12500 gates (where
> a
> nand gate is 2 gates, a set/reset/scan FF is 12 gates), 160 pins and
> runs at 50MHz, made in a 1u process. It is not possible to the chip
> run
> at a higher speed because of all the logic between clocks
> (Pipelining).
> There are many clocks, and a lot of different clears on the FFs. Also
> delaylines internally is used. The timing is extremly important, and
> must be known. So to my questions:
>
> 1) Does an FPGA give you the same control over the design as an Asic
> does?

If you are willing to spend the same time and effort as you would do on
an ASIC, the answer is yes.

> 2) Is this a recommended way of going? The alternative is to do
> another
> Asic. We can not afford to use too long time on this. The volum is
> pretty low.

I think you have to investigate this design and try to reduce the number
of independent clocks and definitely get rid of internal delay lines.
Run at a faster clock rate and pipeline more. Take a fresh look at how
you design. Designing with carefully tuned delays inside the chip is not
the way to go.

Just my $0.02 worth
Peter Alfke, Xilinx
  

Article: 8910
Subject: The PARALLEL Processing Connection-February 9 meeting notice
From: m-node@ix.netcom.com (mitchell)
Date: Fri, 06 Feb 1998 11:56:39 -0800
Links: << >>  << T >>  << A >>
The PARALLEL Processing Connection recognizes Run Time Reconfigurable
Hardware to be an important enabling technology.  The proposition is that
a software package would be mapped to hardware by software people and a
bit stream file would then be easily produced to implement that hardware
implementation.  However, C programmers generally don't have the necessary
hardware knowledge to create the software to hardware mapping.  Compilogic
Corporation's new C2Verilog compiler overcomes this problem and yields
high performance hardware implementations!

On February 9th Don Soderman, CEO of Compilogic will discuss how their
compiler automatically creates on-chip registers, arithmetic macros,
external memory interfaces, and multiple state machines for loops ...
starting from C!  PPC will be interested in what limitations presently
exist in the C2Verilog compiler and what kind of collaborative
arrangements might be possible between PPC and Compilogic.  On the surface
C2Verilog looks very impressive.



The main meeting starts promptly at 7:30PM at Sun Microsystems at 901 San
Antonio Road in Palo Alto.  This is just off the southbound San Antonio
exit of 101.  Northbound travelers also exit at San Antonio and take the
overpass to the other side of 101.  A discussion of member projects
currently underway and other issues of interest to entrepreneurs follows
immediately thereafter at 9:15PM.


Please be prompt; as usual, we expect a large attendance; don't be left
out or left standing.  There is a $12 fee for non-members and members will
be admitted free.  Yearly membership fee is $65.

-- 
B. Mitchell Loebel
Executive Director
The PARALLEL Processing Connection
408 732-9869
Article: 8911
Subject: ASIC position in Sacramento
From: "Todd Walbert" <walbert@softcom.net>
Date: Fri, 6 Feb 1998 12:38:41 -0800
Links: << >>  << T >>  << A >>
Title: ASIC Design Engineer
 Job Description: You will be part of a world-class team developing a
leading-edge multimedia ASIC. You will be involved in all phases of the
development of this 200K+ gate ASIC, including architecture, logic design,
logic verification, test logic insertion, timing analysis, physical design,
and lab bring-up.
 Qualifications: BS (MS preferred) and at least two years relevant
experience.
A very strong background in ASIC development.
Prior experience with one or more of the following ASIC development efforts
is highly desirable: large/complex ASICs, video or graphics ASICs, deeply
embedded microprocessor ASICs.
Prior experience with Synopsys and either VHDL or Verilog.
Prior experience with Model Technology's Vsystem simulator is a plus.

Perm position 90k

Contact Kevin or Karen
 Karenh@new-boston.com


Article: 8912
Subject: Simple questions; please answer
From: "Frits Wester" <fritsw@worldonline.nl>
Date: Fri, 6 Feb 1998 22:38:42 +0100
Links: << >>  << T >>  << A >>
FPGA is totally new for me, but I need some answers:

1.    When and where did FPGA came up?
2.    What are the major advantages?
3.    What products can you use for FPGA?
4.    Are there any books for learning FPGA?
5.    Is FPGA to be considered difficult?
6.    Can you name any sites wich explains all this?
7.    Is FPGA worldwide known/available?

If you have any answers or documentation please mail me.
Thanks for your time.

Frits (fritsw@worldonline.nl)


Article: 8913
Subject: Re: Power consumption
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Fri, 06 Feb 1998 14:22:03 -0800
Links: << >>  << T >>  << A >>
Richard Schwarz wrote:

> I am looking to do a low power design which I would like to implement
> on and FPGA. I have to do some syncing, framing, interleaving
> (requiring
> about
> 10K byrtes SRAM), and 2 uarts. My clock freqs will be less than 5 Mhz.
> I
> have to keep my power well below 90 mW.

I would go for a 2-chip design, using an SRAM and an FPGA.At 5 MHz, your
90 mW power budget is reasonable.
Assuming an XC4005XL and 100 flip-flops connected to your 5 MHz clock,
you will dissipate about 5 mW clock power.
Assuming that on average 25 flip-flops toggle each clock period, that's
another 10 mW. Assuming that 20 outputs, each loaded with 50 pF,  change
every clock period, that  adds another  30 mW.
You see that the wiggling outputs are your biggest power consumer, and
reducing load capacitance would help.
3.3-V devices are a must for low-power design.
The detailed XC4000XL power figures come from page 29 in the Xilinx
newsletter XCELL, 1Q98, which just came from the printer, and is being
mailed next week.

Peter Alfke, Xilinx Applications

Article: 8914
Subject: Altera Timing Requirements
From: Jorge Ivonnet <jivonnet@paging.mot.com>
Date: Fri, 06 Feb 1998 17:44:02 -0500
Links: << >>  << T >>  << A >>
Does anyone know how to make an Altera FPGA meet its timing requirements
by executing some type of command in the MaxPlus2 software?  I'm trying
to run a 30 bit ripple adder on a FPGA.  Maxplus2 says it fails timing
but it's not trying to correct the problem.
Article: 8915
Subject: The PARALLEL Processing Connection - What Is It?
From: m-node@ix.netcom.com (mitchell)
Date: Fri, 06 Feb 1998 14:47:27 -0800
Links: << >>  << T >>  << A >>
The PARALLEL Processing Connection is an entrepreneurial association; we
mean to assist our members in spawning very successful new businesses
involving parallel processing.

Our meetings take place on the second Monday of each month at 7:30 PM at
Sun Microsystems at 901 South San Antonio Road in Palo Alto, California.
Southbound travelers exit 101 at San Antonio ; northbound attendees also
exit at San Antonio and take the overpass to the other side of 101. There
is a $12  visitor fee for non-members and members ($65 per year) are
admitted free. Our phone number is (408) 732-9869 for a recorded message
about upcoming meetings; recordings are available for those who can't
attend - please inquire.

Since the PPC was formed in late 1989 many people have sampled it, found
it to be very valuable, and even understand what we're up to. Nonetheless,
certain questions persist. Now, in our ninth year of operation, perhaps we
can and should clarify some of the issues. For example:


Q.  What is PPC's raison d'etre?

A.  The PARALLEL Processing Connection is an entrepreneurial organization
intent on facilitating the emergence of new businesses. PPC does not
become an active member of any such new entities, ie: is not itself a
profit center.



Q.  The issue of 'why' is perhaps the most perplexing. After all, a $65
annual membership fee is essentially free and how can anything be free in
1998? What's the payoff? For whom?

A.  That's actually the easiest question of all. Those of us who are
active members hope to be a part of new companies that get spun off; the
payoff is for all of us -- this is an easy win-win! Since nothing else
exists to facilitate hands-on entrepreneurship, we decided to put it
together ourselves.



Q.  How can PPC assist its members?

A.  PPC is a large technically credible organization. We have close to 100
paid members and a large group of less regular visitors; we mail to
approximately 400 engineers and scientists (primarily in Silicon Valley).
Major companies need to maintain visibility in the community and
connection with it; that makes us an important conduit. PPC's strategy is
to trade on that value by collaborating with important companies for the
benefit of its members. Thus, as an organization, we have been able to
obtain donated hardware, software, and training and we've put together a
small development lab for hands-on use of members at our Sunnyvale office.
Further, we've been able to negotiate discounts on seminars and
hardware/software purchases by members. Most important, alliances such as
we described give us an inside opportunity to JOINT VENTURE SITUATIONS.



Q.  As an attendee, what should I do to enhance my opportunities?

A.  Participate, participate, participate. Many important industry
principals and capital people are in our audience looking for the
'movers'!

For further information contact:

-- 
B. Mitchell Loebel
CEO, Chief Technical Officer
MultiNode Microsystems Corporation              408 732-9869

Executive Director
The PARALLEL Processing Connection              408 732-9869
Article: 8916
Subject: Atmel 6k Speedup procedure
From: "Brad Smallridge" <manbike@smallridge.xo.com>
Date: Fri, 6 Feb 1998 16:08:39 -0800
Links: << >>  << T >>  << A >>
Does anyone know how to speed up the manual placement of registered
instances in the Atmel 6k Figaro software.  Does removing the global clock
and reset buffers help? Is there a way to turn off the Delay Calculator?
Brad Smallridge
Sightech Vision Systems, Inc.



Article: 8917
Subject: Re: FPGA/ASIC - same difference?
From: Rick Carmichael <rcarmich@intellistor.com>
Date: Fri, 06 Feb 1998 19:51:51 -0700
Links: << >>  << T >>  << A >>
Hi Magnus,

I believe, you already understand the differences
between ASICs and FPGAs,and wonder (being a pretty 
good FPGA designer), "how will I do in a larger more 
complex, higher perfomance ASIC environment"? 

Both methodologies are complex processes requiring
a certain talent level to execute. ASICs require the
knowledge of a larger tool set and require additional
"grunt work" to acheive adequate test quality levels,
and to insure working silicon.

My experience is that good FPGA designers make good ASIC
designers if they work well in a team environment. ASIC
methodologies for large designs require a "software-like
approach" since more folks participate in the design. 
Instead of calling your own shots sometimes you have to
reach group concensus. Remember that register interface
you used in your previous design? Consider that there is
overhead in a group of say 10 folks in determining how best
to approach that aspect of your design. Synchronization of 
progress and revision control also add additional overhead
to that which would be experienced by a lone wolf doing a 
single FPGA design.

ASIC design teams must worry that their baby,
created over a 7 - 12 month time frame might become 30
or so "$300000 tie tacks" when prototypes are obtained.
ASIC designers are sometimes "neurotic" - I attribute this
to the long lead times for large standard cell arrays.
At tape out, I realize that in 8-12 weeks, ASIC prototypes 
will be rushed from the assembly house to the lab where one 
of three events occur:

The ASIC Works great - ASIC designers are heros :)

SW workarounds exist - ASIC designers are "OK guys" :|

The ASIC is not useable by SW - designers are scum - company 
may experience problems due to late product introduction :( 

During the 8-12 week wait, I am powerless to change a 
single gate.

If you think you might enjoy the above, go for the ASIC 
design experience. Few experiences compare with 
participation in a hot team of ASIC designers turning 
out high-quality silicon! 

rickc



Magnus Homann wrote:
> 
> Hi,
> 
> I'm just curious of how big a step there is from FPGA to ASIC? I
> cnostatntly hear that ASIC is so much harder, but is that just to
> protect the ASIC-designers postions?
> 
> I can accept that there is some added difficulty, but how hard can it
> really be? After doing a few FPGA designs (1-3) and taking a week
> course in ASIC design, would I be ready?
> 
> Homann
> --
>    Magnus Homann  Email: d0asta@dtek.chalmers.se
>                   URL  : http://www.dtek.chalmers.se/DCIG/d0asta.html
>   The Climbing Archive!: http://www.dtek.chalmers.se/Climbing/index.html
Article: 8918
Subject: Re: Simple questions; please answer
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 6 Feb 1998 19:32:06 -0800
Links: << >>  << T >>  << A >>

Frits Wester wrote in message <6bfvrd$4ce$1@news.worldonline.nl>...
>FPGA is totally new for me, but I need some answers:
>
>1.    When and where did FPGA came up?

Xilinx introduced the first FPGA back in 1986, then called a Logic Cell
Array (or LCA).  Since then, various companies such as Actel, Altera, Atmel,
Lucent Technologies, Motorola, QuickLogic, and Vantis (AMD's programmable
logic division) have introduced their own version of FPGAs.

>2.    What are the major advantages?

Compared to PALs and TTL, FPGAs offer:

* higher integration
* reduced board space
* reduced power consumption
* easier design modifications
* faster time to market
* many more flip-flops and I/O than found in a typical PAL or PLD

Compared to ASICs, FPGAs offer:

* reduced risk (no need to create a custom, unchangeable device)
* no non-recurring engineering (NRE) charges
* no need to write device test vectors (though you still need to verify your
design)
* usually faster time to market
* very easy design changes
* more cost effective in small to moderate production volumes

>3.    What products can you use for FPGA?

FPGAs are found in practically any digital design, though there are
limitations.  Generally, FPGAs are on boards costing $100 or more (not much
in consumer products).  FPGAs cost somewhere from US$5 on up to $1,000 per
device.  Also, they generally don't run faster than 100 MHz.

>4.    Are there any books for learning FPGA?

There are many.  You should look at the list at
http://www.optimagic.com/books.html .

>5.    Is FPGA to be considered difficult?

Their difficulty is all relative.  If you know TLL and PALs, yes, FPGAs
might seem more difficult at first.  They have their own idiosyncrasies,
much like any other technology.  I have a few tips available at
http://www.optimagic.com/faq.html#General_Advice

>6.    Can you name any sites which explains all this?

The Programmable Logic Jump Station at http://www.optimagic.com may be
helpful.  I would recommend looking at the Frequently-Asked Questions
section at http://www.optimagic.com/faq.html.  It's a good place to start.


A good overview article on the various FPGA and CPLD architectures is
available in Adobe Acrobat format at http://www.vcc.com/papers/brown.pdf .


>7.    Is FPGA worldwide known/available?
>

FPGAs are generally widely available in most industrialized countries.


-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------





Article: 8919
Subject: Re: Asic to FPGA
From: sam@palmnet.net (Steve Mitchell)
Date: 7 Feb 1998 04:57:36 GMT
Links: << >>  << T >>  << A >>
The NRE to do another ASIC would kill you, considering that you have low
volumes.  A Xilinx 4K series device would probably suit your application.
I would consider redesign (delay lines - yuck!), but I don't know your
design.  Another option is to consult with a company such as Chip Express
or QuickLogic to see if they can translate your ASIC into their technology.

Steve Mitchell

In article <34DAAE53.5AB8@online.no>, larsher@online.no says...
>
>Hello,
>I have an Asic that is going out of production because the vendor is no
>longer supporting this process. The design is about 12500 gates (where a
>nand gate is 2 gates, a set/reset/scan FF is 12 gates), 160 pins and
>runs at 50MHz, made in a 1u process. It is not possible to the chip run
>at a higher speed because of all the logic between clocks (Pipelining).
>There are many clocks, and a lot of different clears on the FFs. Also
>delaylines internally is used. The timing is extremly important, and
>must be known. So to my questions:
>
>1) Does an FPGA give you the same control over the design as an Asic
>does?
>2) Is this a recommended way of going? The alternative is to do another
>Asic. We can not afford to use too long time on this. The volum is
>pretty low.

Article: 8920
Subject: altera max7000s and JTAG ISP
From: eteam.nospam@aracnet.com (bob elkind)
Date: Fri, 6 Feb 1998 21:13:32 -0800
Links: << >>  << T >>  << A >>
Recent experience for a client brought some useful applications
information to our attention:

The Altera Max7000s series of (cplds|fpgas) are in-system
re/programmable, via the standard JTAG port facilities.

One serious hazard to avoid is the presence of a clock signal
on either of the two "global" clock inputs.  Be sure to disable
all such clocks to the device before programming the device via
the JTAG port.

underlying results:

1.  attempted programming with free-running clock.  Programming
(using ByteBlaster and ASAP2 on a PC) stopped without completing.
Cycle power to the target board.  Device won't program, won't
accept any JTAG commands.  Part must be replaced, as its wounds
are fatal.

2.  2nd attempt on a second board yielded the same results.

3.  On Altera's recommendation, free-running clock is disabled
while programming.  Third attempt successful.  Many successive
attempts are successful.  Try one last programming run, with the
clock running (a very curious jr engineer at the helm!), and
the device breathes its last.

4.  Removing all the various and sundry "fixes" suggested by
Altera, but *still* disabling the clock during programming runs,
there are no further failures reported.

This hazard is, to my knowledge, not mentioned in any application
notes that I've seen, which is a shame.  The results of violating
this requirement are quite severe, and the remedy for a dead
208-pin device is painful.  Boards don't suffer replacing the
same fine-pitch SMD device for very long, without eventually
surrendering some pads.

After subsequent conversation with Altera, they are thinking about
disabling all clock inputs internally (in future product designs)
while programming.

Also, they are thinking about CRC checking
programming data before "burning" the programming into the
non-volatile "switches".  To my understanding, the failure
mechanism is that the programming data is corrupted by on-chip
interference from the clock; and it is the bogus program that
convinces the device to actively *drive* the JTAG pins, making
attempts to correct the bogus programming futile.

-- Bob Elkind

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 8921
Subject: Re: Looking for XC6200 Sw
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: Sat, 7 Feb 1998 12:27:19 -0000
Links: << >>  << T >>  << A >>

You should try to get a copy of the XACTStep 6000 software for Workstations-
the libraries are included on there.

Craig


Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>...
>Hi there,
>
>We are trying to obtain Xilinx XC6200 software through the Xilinx
>University Program, but we haven't any news from them. Has anybody
>got the Synopsys libraries for this FPGA?





Article: 8922
Subject: Re: Looking for XC6200 Sw
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: Sat, 7 Feb 1998 12:27:19 -0000
Links: << >>  << T >>  << A >>

You should try to get a copy of the XACTStep 6000 software for Workstations-
the libraries are included on there.

Craig


Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>...
>Hi there,
>
>We are trying to obtain Xilinx XC6200 software through the Xilinx
>University Program, but we haven't any news from them. Has anybody
>got the Synopsys libraries for this FPGA?





Article: 8923
Subject: Re: Looking for XC6200 Sw
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: Sat, 7 Feb 1998 12:27:19 -0000
Links: << >>  << T >>  << A >>

You should try to get a copy of the XACTStep 6000 software for Workstations-
the libraries are included on there.

Craig


Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>...
>Hi there,
>
>We are trying to obtain Xilinx XC6200 software through the Xilinx
>University Program, but we haven't any news from them. Has anybody
>got the Synopsys libraries for this FPGA?





Article: 8924
Subject: Re: Looking for XC6200 Sw
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: Sat, 7 Feb 1998 12:27:19 -0000
Links: << >>  << T >>  << A >>

You should try to get a copy of the XACTStep 6000 software for Workstations-
the libraries are included on there.

Craig


Pedro Merino Gonzalez wrote in message <6bfb4k$ppd$1@sanson.dit.upm.es>...
>Hi there,
>
>We are trying to obtain Xilinx XC6200 software through the Xilinx
>University Program, but we haven't any news from them. Has anybody
>got the Synopsys libraries for this FPGA?







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