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Messages from 8950

Article: 8950
Subject: Re: Free FPGA tools???
From: ying@soda.CSUA.Berkeley.EDU (Ying C.)
Date: 8 Feb 1998 23:01:35 GMT
Links: << >>  << T >>  << A >>
In article <34dde6bd.2747293@news.megsinet.net>,  <msimon@tefbbs.com> wrote:
>I am interested but in the Chicago area. I am interested in FPGA tools
>good enough to design 4K to 10K gate microprocessors, with possibly
>128 bytes of internal RAM (not counting registers). I want to design a
>generic board so that different designs could be tried out against
>different classes of problems.
>
>I have no problem with board design but lack the $$$ required for the
>FPGA tools.
>
>Simon
>


One of the device supported by Altera's free trial version, PLS-WEB, is
10k10. It has 6K bits of RAM and sufficient # of gates for your use. Your
computer has to be on a TCP/IP network to get PLS-WEB to work though.
Check out http://www.altera.com/html/products/pls-web.html.

Ying
ying@csua.berkeley.edu
-- 
-----------------------------------
http://www.csua.berkeley.edu/~ying
Article: 8951
Subject: Re: Free FPGA tools???
From: &miker <&miker@ethergate.com>
Date: Sun, 08 Feb 1998 16:39:59 -0800
Links: << >>  << T >>  << A >>
Richard Schwarz wrote:

> Miker,
>
> For $350.00 you can get the ...snip

Thanks for the input.  I guess I should have explained the concept "free"
:-).What I meant was, no cost, without payment, provided gratis by the vendor,

or anyone else,  to stimulate use of their product.  Then there's the
educational
freebie, and the good-will freebie, the demo freebie...
miker


&miker wrote:

I've been using PALASM and GAL20V8 for hobby projects.  Don't need much
 more capability, just more
 of the same.  Like a GAL32V128.

 The problem with FPGAs is that I can't find any affordable tools to
 program them.  Does anyone support their
 programmable devices with free base development software?  I don't need
 anything more capable than PALASM.

 I have a second item on my wish list.  I'd like to be able to reprogram
 an FPGA on the fly.
 Back when I had access to Xilinx tools, there still was no information
 available to know which bits
 did which functions.  Best I could do was route it and load the
 resultant secret patterns.

 What I really want is to define a few "architecture files" that define
 the base FPGA configurations that could
 be loaded into the FPGA configuration RAM.  Then I need the capability
 to reprogram polarities of nodes on the fly.  I'll probably buy two
 FPGAs, total,  so there's not much use
 in asking a vendor for something that's not already published.

 That's the problem with being retired.  You lose access to all those
 neat expensive hi-tech tools.

 Any ideas?
 miker
 --


--
Return Address is Bogus.
TO REPLY CLICK BELOW.
http://www.ethergate.com/users/miker/index.html
Usually have stuff WANTED and FOR SALE.
If you get a URL error, try again later.


Article: 8952
Subject: Re: Free FPGA tools???
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Sun, 8 Feb 1998 16:56:33 -0800
Links: << >>  << T >>  << A >>
The Programmable Logic Jump Station has links to various vendors that
provide free or low-cost, downloadable development programs.  All the major
vendors are represented.  Please point your browser to
http://www.optimagic.com/lowcost.html.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


&miker <&miker@ethergate.com> wrote in message
<34DD1F0E.74AAA61B@ethergate.com>...
>I've been using PALASM and GAL20V8 for hobby projects.  Don't need much
>more capability, just more
>of the same.  Like a GAL32V128.
>
>The problem with FPGAs is that I can't find any affordable tools to
>program them.  Does anyone support their
>programmable devices with free base development software?  I don't need
>anything more capable than PALASM.
>



Article: 8953
Subject: Re: Free FPGA tools???
From: Sam Falaki <falaki@nospam.videotron.ca>
Date: Mon, 09 Feb 1998 01:11:56 GMT
Links: << >>  << T >>  << A >>
I downloaded this software but am a little afraid of using it due to
privacy issues.  What's the deal with the TCP/IP stuff?  Anyone know
why this is necessary and what it is used for?  Would my designs be
protected?

Hopefuly someone from Altera will read this and respond with an explanation.

rgds,

Sam Falaki

Steven Groom wrote:

> Also check out Altera's free PLS-WEB software - it allows design up to 10K
> gates.
>
> www.altera.com
>
> Regards,
>
> Steve.



Article: 8954
Subject: Re: VHDL vs schematics
From: "rk" <stellare@erols.com.NOSPAM>
Date: 9 Feb 1998 03:41:07 GMT
Links: << >>  << T >>  << A >>
david d.:
: It's not only whether it can use special elements of a particular
: FPGA, but also whether it's smart enough to minimize logic. When I
: checked out Alta Group's SPW and Synopsis's Behavioral, Altera's DSP
: Tools, and Exemplar, a couple of years ago, None of them correctly
: recognized that a constant multiply by 9 of an 8 bit number, should
: use a 9 bit adder to get the 12 bit result.

rk:
i just tried actmap, the vhdl compiler (amongst other things), to see how
it did, since i just updated to 3.1.1 update 1.  when i multiplied by 8, it
correctly implemented it with no logic.  however, when i had it multiply by
9, it insisted on using a multiplier.  i did two runs, one optimized for
area, the other for speed, and it insisted on doing things the hard way.


david d:
: Sure, they could be forced, kicking and screaming, to implement it
: this way, but schematics seemed far simpler. 
<snip>

rk:
it's easy enough to break out the terms and simply tell the compiler to add
them up; i.e., x + 8x.  i just finished an fir filter done that way and the

coefficients were selected, in part, so that i could use that construction 
efficiently.  the first version i did used macro generator output hooked up

in a top-level schematic, by the way, not "pure" schematics, as i didn't
want 
to spend a lot of time drafting adders.  since the system equations
changed, 
i wanted to get the redesign done as quickly as possible, and vhdl was much

quicker to design with than the schematics.

<snip>
 
dave d:
: I'd rather spend 4 hours doing manual placement one time, than 40
: hours of dubious automatic placement for every design change.

rk:
this may be a question of tools and s/w, which we just went through in
great detail, a few weeks ago.  but one additional benefit of the hdl is
the ability to do trade-offs.  while an optimal design would be done in
either schematics or modifed macros + schematics, it is simple enough to do
the design in vhdl, do a p&r, and then back down from top speed to save
some area and power.  and these iterations are done in tens of minutes, not

tens of hours. generally i have found that the predictability of the tools
is
fairly good and for most designs there is little tweaking or hand placement
necessary.  for some environments, as we saw during the previous series of
posts, there may be a factor of 2 in timing performance from automagic to
hand optimized and some ppl have reported p&r times exceeding 24 hours. 
another factor is changing systems equations.  if i felt that the system
design (handed to me) would not change, i might have done the redesign in
schematic + macro generator and got something close to optimal.  since the
probability of things changing again seem to approach 100%, i chose the
better is the enemy of good enough approach to save humanoid time.

one trade-off i did last night was in chip technology vs. speed and area. 
in a few minutes i was able to do timing analyses in two different
technologies and speed grades.  and the difference in performance from the 
hardware for an identical p&r was great enough that in the more recent
technology
device i was able to use slower, small adders.  doing this via schematics
would have been relatively painful.

dave d:
: I wonder if any of these tools have improved enough, in the last two
: years, that they would now instantiate a 9 bit adder, and permit me
: to graphically, hierarchally, edit the placement of this adder with
: respect to the registers on its input and/or output.

rk:
not the one that i'm using.  perhaps others could post their results.  i'd
be real interested in seeing how the current synopsis, synplicity, and
examplar tools do.


--------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------

Article: 8955
Subject: x86 soft cores?
From: Joachim Strombergson <emwchim@emw.ericsson.se>
Date: Mon, 09 Feb 1998 09:07:54 +0100
Links: << >>  << T >>  << A >>
Tja!

I'm looking for soft cores for x86 processors. Does anybody develop and
sell such beasts? Any help greatly appreciated.

-- 
Med vänlig hälsning

Joachim Strömbergson
---------------------------------------
Joachim Strömbergson UN/X

ASIC Technology and System on Silicon
Ericsson Microwave Systems AB
SE-431 84 Mölndal
Joachim.Strombergson@emw.ericsson.se
---------------------------------------
Article: 8956
Subject: Re: Free FPGA tools???
From: THIEBOLT Francois <thiebolt@irit.fr>
Date: Mon, 09 Feb 1998 10:53:55 +0100
Links: << >>  << T >>  << A >>
Hi,

Like us working with a few $$$, we'd like to use FPGA WITHOUT any
programmer
so that's the reason why we're now using Lattice tools and chips because
you
don't need anything more than a download cable (# $65 and they even give
schématics !!).

Hope this helps.

-- 
-------------------------------------------------------------
THIEBOLT Francois \ You think your computer run too slow ?
UPS Toulouse III  \ - Check nobody's asked for tea !
thiebolt@irit.fr  \ "The Hitchikers Guide to the Galaxy" D.Adams
-------------------------------------------------------------
Article: 8957
Subject: CfP: 3rd International Workshop on Boolean Problems
From: "Prof. Dr. B. Steinbach" <steinb@informatik.tu-freiberg.de>
Date: Mon, 9 Feb 1998 11:00:17 +0100
Links: << >>  << T >>  << A >>
Please note: SUBMISSION DEADLINE IS 15 April

Please redistribute to your colleagues as appropriate.

With thanks from the entire Organizing Committee,

Prof. Dr.-Ing. habil. Bernd Steinbach, Chair
---------------------------------------------------------------------

Call for Papers

3rd International Workshop on Boolean Problems
September 17-18, 1998, Freiberg (Sachsen)

Synopsis

The workshop on Boolean problems has an emphasis on the problems
related to the solution of all kinds of high-dimension Boolean and
discrete problems, and provides a forum for researchers and
engineers from different disciplines to exchange ideas.  The
workshop is devoted to theoretical discoveries as well as practical
applications.  An aim of the workshop is to initiate possible
collaborative research and to find new areas of application. It is
intended to publish the papers in proceedings.

Topics of Interest

  Theory
  - Properties and applications of Boolean Algebras

  Data Structures and Algorithms
  - Modeling
  - Specification of data structures/Algorithms
  - Complexity

  Program Systems/Software
  - Fundamental software for the solution of Boolean Problems
  - Comparison of efficiency

  Practical Applications
  - Modeling
  - Solution of real-world problems

Submissions

To submit a paper, please send an extended abstract, no longer than
6 pages, as a postscript file to <langc@informatik.tu-freiberg.de>
OR send two hard copies of your paper to the general chair (below)
by April 15, 1998.  Acceptance notices will be sent by May 15, 1998.
The final version of the paper should be submitted by July 1, 1998.

Program Committee

Prof. U. G. Baitinger, Universität Stuttgart
Prof. T. Sasao, Kyushu Institute, Iizuka
Prof. B. Becker, Universität Freiburg
Prof. B. Steinbach, TU BA Freiberg
Prof. Ch. Meinel, Universität Trier
Prof. A. Zakrevskij, Academy of Science, Minsk
Prof. M. A. Perkowski, Portland State University

Conference Language: English

Contacts
- Conference Location
    Freiberg University of Mining and Technology,
    Freiberg (Sachs.), Germany
- General Chair
    Prof. Dr.-Ing. habil. B. Steinbach, TU Bergakademie Freiberg,
    Institut für Informatik, Akademiestr. 6, D-09596 Freiberg, Germany,
    Phone +49(03731) 39-2568, Fax. +49(03731) 39-2645,
    E-mail: steinb@informatik.tu-freiberg.de
- Conference Coordinator
    Ch. Lang, TU Bergakademie Freiberg, Institut für Informatik,
    Akademiestr. 6, D-09596 Freiberg, Germany,
    Phone +49(03731) 39-3197, Fax. +49(03731) 39-2645,
    E-mail: langc@informatik.tu-freiberg.de
- More Information
    http://www.informatik.tu-freiberg.de/prof2/ws_bp3/



Article: 8958
Subject: Re: Free FPGA tools???
From: madarass@cats.ucsc.edu (Rita Madarassy)
Date: 9 Feb 1998 15:35:36 GMT
Links: << >>  << T >>  << A >>

Well, you are probably referring to the ISP Lattice parts.
If you are using these lattice parts you are probably spending
way too much money on these parts.
Xilinx offers the same type of technology with a sw package of around
70$. And just like the lattice parts, you only need a download cable.




In article <34DED233.673F@irit.fr>,
THIEBOLT Francois  <thiebolt@irit.fr> wrote:
>Hi,
>
>Like us working with a few $$$, we'd like to use FPGA WITHOUT any
>programmer
>so that's the reason why we're now using Lattice tools and chips because
>you
>don't need anything more than a download cable (# $65 and they even give
>schématics !!).
>
>Hope this helps.
>
>-- 
>-------------------------------------------------------------
>THIEBOLT Francois \ You think your computer run too slow ?
>UPS Toulouse III  \ - Check nobody's asked for tea !
>thiebolt@irit.fr  \ "The Hitchikers Guide to the Galaxy" D.Adams
>-------------------------------------------------------------


Article: 8959
Subject: Re: x86 soft cores?
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Mon, 9 Feb 1998 08:00:25 -0800
Links: << >>  << T >>  << A >>
I believe that VAutomation has 8086 and 80186 cores available, including
test silicon for verification.  You can find out more at
http://www.vautomation.com/html/products.htm.

From their description, though, it sounds like an 8086 requires multiple
mid-range FPGA devices but may fit in a single large device.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Joachim Strombergson wrote in message <34DEB95A.2BED@emw.ericsson.se>...
>Tja!
>
>I'm looking for soft cores for x86 processors. Does anybody develop and
>sell such beasts? Any help greatly appreciated.
>
>--
>Med vänlig hälsning
>
>Joachim Strömbergson
>---------------------------------------
>Joachim Strömbergson UN/X
>
>ASIC Technology and System on Silicon
>Ericsson Microwave Systems AB
>SE-431 84 Mölndal
>Joachim.Strombergson@emw.ericsson.se
>---------------------------------------


Article: 8960
Subject: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
From: z80@ds.com (Peter)
Date: Mon, 09 Feb 1998 18:30:38 GMT
Links: << >>  << T >>  << A >>
Hello,

I have been using Viewlogic 4 (DOS) and XACT6 PPR for XC3000 designs.

It has occurred to me that XACT6 might be ignoring these net
attributes, as attached to certain wires in Viewdraw.

I don't want to clutter a simple question, but the reason this came up
is that years ago, Xilinx app engineers were recommending that (if one
cannot use the global clock nets) it is OK to use a long line for it,
by using the L attribute. One could also put in a very tight skew
spec, like SC=1. This worked fine with the old APR (and with the
slower devices of the day), but with XACT6 PPR it often fails. I
recently heard that XACT6 now ignores these net attributes.

I know that the Xilinx preferred method today is timespecs.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 8961
Subject: Semiconductor Times semiconductor startups web site
From: Cliff Hirsch <cjh@mediaone.net>
Date: Mon, 09 Feb 1998 15:28:18 -0500
Links: << >>  << T >>  << A >>
Semiconductor Times debuts its new web site,
http://www.semiconductortimes.com , featuring:

        o a downloadable PDF sample issue,
        o semiconductor company earnings (check out the gross margins!),
        o on-line order entry form.

Semiconductor Times, a monthly newsletter, is the definitive source for
the hottest semiconductor related startups: fabless chip companies,
chipless chip companies, EDA, micro displays, MEMS. Tomorrow's hottest
technologies brought to you today.

Check it out and spread the word.

Regards,
Cliff Hirsch
Publisher
cjh@semiconductortimes.com
Article: 8962
Subject: Re: Free FPGA tools???
From: ying@soda.CSUA.Berkeley.EDU (Ying C.)
Date: 9 Feb 1998 21:17:38 GMT
Links: << >>  << T >>  << A >>
In article <34DE58E4.98631BA@nospam.videotron.ca>,
Sam Falaki  <falaki@nospam.videotron.ca> wrote:
>I downloaded this software but am a little afraid of using it due to
>privacy issues.  What's the deal with the TCP/IP stuff?  Anyone know
>why this is necessary and what it is used for?  Would my designs be
>protected?
>
>Hopefuly someone from Altera will read this and respond with an explanation.
>
>rgds,
>
>Sam Falaki
>

The TCP/IP requirement for PLS-WEB is needed for the license server.
PLS-WEB uses Window based flexlm server to obtain license information.
For more information about the flexlm license server, you can check out
www.globetrotter.com. I don't think PLS-WEB or the flexlm license server
creates any secutity loop hole.

Ying
ying@csua.berkeley.edu

-- 
-----------------------------------
http://www.csua.berkeley.edu/~ying
Article: 8963
Subject: FPGA resource available
From: anthony staiti jr <tony.staiti@sun.com>
Date: Mon, 09 Feb 1998 17:07:02 -0500
Links: << >>  << T >>  << A >>
SunLabs has built a series of FPGA based reconfigurable SBus and PCI bus
interface cards designed to allow rapid prototyping of custom
co-processors,
"soft" peripherals and/or I/O logic with little or no physical hardware
development. In particular these cards are designed to make it
relatively easy
for customers to interface their custom hardware to a Sun workstation or
a PCI system running Solaris.

For information on the architecture of these boards please visit:

    http://www.sunlabs.com/research/sbx/

For information on availability please contact:

    anthony.staiti@east.sun.com

    or:

    stuart.adams@east.sun.com
Article: 8964
Subject: FPGA resource available
From: anthony staiti jr <tony.staiti@sun.com>
Date: Mon, 09 Feb 1998 17:14:02 -0500
Links: << >>  << T >>  << A >>
SunLabs has built a series of FPGA based reconfigurable SBus and PCI bus
interface cards designed to allow rapid prototyping of custom
co-processors,
"soft" peripherals and/or I/O logic with little or no physical hardware
development. In particular these cards are designed to make it
relatively easy
for customers to interface their custom hardware to a Sun workstation or
a PCI system running Solaris.

For information on the architecture of these boards please visit:

    http://www.sunlabs.com/research/sbx/

For information on availability please contact:

    anthony.staiti@east.sun.com

    or:

    stuart.adams@east.sun.com
Article: 8965
Subject: IEEE memory workshop
From: fmeyer@cs.tamu.edu (Jackie Meyer)
Date: 10 Feb 1998 06:10:03 GMT
Links: << >>  << T >>  << A >>
1998 IEEE International Workshop on
MEMORY Technology, Design, and Testing

August 24--25, 1998

CALL FOR PAPERS

San Jose, California

Deadline:  February 25

Sponsored by: IEEE Computer Society, Technical Committee on Test
Technology and Technical Committee on VLSI. In cooperation with: IEEE
Solid-State Circuit Society.

The workshop will include all aspects of memory design, process
technologies, and testability related topics. Memory circuit designs,
cell structures, fabrication processes, design architectures and
related testing and verification methods for SRAM, DRAM, Flash and
non-volatile memories, EPROM, EEPROM, embedded memories,
logic-enhanced and FIFO memories, 3-D memories, and content
addressable memories. Representative topics are:

Memory fault modeling and test generation
Built-in test and testable designs for memories
Concurrent checking and memory fault diagnosis
Quality and reliability issues
Space applications and radiation hardening issues
Memory failure and yield analysis
High-speed, innovative designs
Fault isolation, reconfiguration and repair
Multiported, multibuffered memories
Logic-enhanced and programmable memories
Application-specific and embedded memories
Multimegabit SRAMs and DRAMs
CMOS, BiCMOS and bipolar designs for high yield and reliability

If you are interested in giving a tutorial please contact the Tutorial
Chair as early as possible.

For consideration for the regular technical program, please submit
five (5) copies of an extended abstract of about one thousand words of
original work on any aspect of memory technology, design, and testing
to either Program Chair. Submissions should include full names and
affiliations of authors and contact information, and should indicate
the intended presenter.

Submissions are due February 25, 1998. Acceptance notification will be
on March 31, 1998. Final papers will be due May 15, 1998 and must be
in postscript format. Presentation time slots will average 30 minutes.

GENERAL CHAIR
Fabrizio Lombardi
Computer Science MS 3112
Texas A&M University
College Station TX  77843, USA
409/845-5464; fax 847-8578
lombardi@cs.tamu.edu

LOCAL ARRANGEMENTS
Craig Soldat, Hewlett-Packard
351 E Evelyn Ave
San Jose CA  95035, USA
415/694--3499; craig_soldat@hp.com

TUTORIALS CHAIR
Bruce Cockburn
Elec. and Comp. Engg. MS 238 CEB
University of Alberta
Edmonton AB  T6G 2G7, Canada
403/492-3827; fax 492-1811
cockburn@ee.ualberta.ca

FINANCE CHAIR
Duncan "Hank" Walker
Computer Science MS 3112
Texas A&M University
College Station TX  77843, USA
409/862-4387; walker@cs.tamu.edu
walker@cs.tamu.edu

PUBLICITY CHAIR
Fred "Jackie" Meyer
Computer Science MS 3112
Texas A&M University
College Station TX  77843, USA
409/845-1014; fmeyer@cs.tamu.edu

STEERING COMMITTEE

Rochit Rajsuman, Chair
Equator Technologies
408/260-0599 X337
rajsuman@equator.com

Bernard Courtois, INPG/TIMA
Grenoble, France

Ad van de Goor, Delft Univ. of
Technology, The Netherlands

Yervant Zorian, LogicVision
San Jose CA, USA

PROGRAM COMMITTEE

Thomas Wik, PROGRAM co-CHAIR
LSI Logic, MS E--194
1551 McCarthy Blvd, Milpitas CA  95035, USA
408/954-4471; fax 433-4561; trw@lsil.com

David Lepejian, PROGRAM co-CHAIR
Heuristic Physics Laboratories
1649 S Main Street, Milpitas CA  95035, USA
408/263-1466; fax 263-1584; dyl@hpl.com


Glenn Chapman, Simon Fraser Univ.
Bernard Courtois, INPG/TIMA
Bob Evans, MosAid
Paul Franzon, NCSU
Ad van de Goor, Delft Univ. of Tech.
Susumu Horiguchi, JAIST
Omar Kebichi, Mentor Graphics
Jim Lewandowski, Bell Labs
Sankaran Menon, TI
Sharon Murray, Medtronic Micro-Rel
Ceredig Roberts, Micron
Konrad Schoenemann, Siemens AG
Ying Shiau, Cypress Semiconductor
Stu Tewksbury, WV Univ.
Seiken Yano, NEC
Yervant Zorian, LogicVision
Article: 8966
Subject: Re: Free FPGA tools???
From: gregh@wx.rose.hp.com (Greg Holdren)
Date: 10 Feb 1998 06:23:14 GMT
Links: << >>  << T >>  << A >>
Ying C. (ying@soda.CSUA.Berkeley.EDU) wrote:
: In article <34DE58E4.98631BA@nospam.videotron.ca>,
: Sam Falaki  <falaki@nospam.videotron.ca> wrote:
: >I downloaded this software but am a little afraid of using it due to
: >privacy issues.  What's the deal with the TCP/IP stuff?  Anyone know
: >why this is necessary and what it is used for?  Would my designs be
: >protected?
: >
: >Hopefuly someone from Altera will read this and respond with an explanation.
: >
: >rgds,
: >
: >Sam Falaki
: >
: 
: The TCP/IP requirement for PLS-WEB is needed for the license server.
: PLS-WEB uses Window based flexlm server to obtain license information.
: For more information about the flexlm license server, you can check out
: www.globetrotter.com. I don't think PLS-WEB or the flexlm license server
: creates any secutity loop hole.
: 
Flexlm is a pain in the ASS!  I assume the problem for me is that
I'm behind a firewall. I dont know as I dont HAVE the time to mess
with it. Gee, what happened to good ole working demos.

-- 
Greg Holdren
gregh@wx.rose.hp.com

Article: 8967
Subject: Re: Free FPGA tools???
From: Bernt.Hullen@ruhr-uni-bochum.de (Bernt_Hullen)
Date: 10 Feb 1998 07:21:18 GMT
Links: << >>  << T >>  << A >>
On Mon, 09 Feb 1998 10:53:55 +0100, THIEBOLT Francois <thiebolt@irit.fr> wrote:
>Hi,
>
>Like us working with a few $$$, we'd like to use FPGA WITHOUT any
>programmer
>so that's the reason why we're now using Lattice tools and chips because
>you
>don't need anything more than a download cable (# $65 and they even give
>schématics !!).

The same is with AMD. I use the Mach445 in my Diplomarbeit.

-- 
--

Tschau,
       Bernt

+-------------------------------------------------------------------+
|Bernt Hullen              Email: Bernt.Hullen@rz.ruhr-uni-bochum.de|
+-------------------------------------------------------------------+

Article: 8968
Subject: TPC1020AFN-068C DEVICES REQUIRED
From: "Ptmsa1" <tmsa1@iafrica.com>
Date: 10 Feb 1998 08:43:25 GMT
Links: << >>  << T >>  << A >>
We require information of anyone who might have stock of the TEXAS
INSTRUMENTS TPC1020AFN-068C FPGA devices for purchase.

We are looking of a quantity of 50. Could you please provide us with any
information urgently!!!!

Thank-you.
Bossie
Article: 8969
Subject: Synario schematic to Xilinx Foundation conversion?
From: "Pontus Andersson" <pontus.andersson@obducat.com>
Date: 10 Feb 98 10:48:33 GMT
Links: << >>  << T >>  << A >>
I´m currently converting a design which consist of ABEL source code and
schematic. These are done in a Synnario - Lattice package. And I want to
convert them so I can use it with Xilinx Foundation. Does anybody know a
way to do this. I'd very much appreciate not to redraw all my schematics. 

Pontus Andersson
Article: 8970
Subject: reading crcs from an fpga
From: david.surphlis@gecm.com
Date: 10 Feb 1998 12:23:00 GMT
Links: << >>  << T >>  << A >>
hi there,
	Dose any-one know if it is possible to read back the checksum 
from an fpga, if so could you point me in the right direction.
the device i am using is xilinx 4000e

Thanks 
Davey
-- 
--
                             ...phil

Article: 8971
Subject: Re: Synario schematic to Xilinx Foundation conversion?
From: "Robert E. Engle Jr." <rengle@ix.netcom.com>
Date: Tue, 10 Feb 1998 10:07:40 -0500
Links: << >>  << T >>  << A >>
Pontus Andersson wrote:
> 
> I´m currently converting a design which consist of ABEL source code and
> schematic. These are done in a Synnario - Lattice package. And I want to
> convert them so I can use it with Xilinx Foundation. Does anybody know a
> way to do this. I'd very much appreciate not to redraw all my schematics.

you need the synario xilinx fitter which produces a xilinx xnf format
file. then from within the design manager you use translate to import
the design.

the xilinx fitter is $2000 though, and i am not sure if it will
interface to the stripped down version that lattice provides

if you know anyone with the full blown synario system they could easily
do this for you, as well as going to actel, atmel, and others.

do you think that such a service offered over the web would be a usefull
thing?

_______________________________________________________________________

Bob Engle			rengle@ix.netcom.com
Embedded Solutions	
Orlando, Florida		FPGA and MPU contract engineering
_______________________________________________________________________

"I will not be pushed, filed, stamped, indexed, briefed, de-briefed
or numbered. My life is my own...."    The Prisoner
_______________________________________________________________________

Article: 8972
Subject: Re: TPC1020AFN-068C DEVICES REQUIRED
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 10 Feb 1998 08:21:11 -0800
Links: << >>  << T >>  << A >>
I believe that Texas Instruments has discontinued these devices.  However,
Actel (http://www.actel.com) was the original developer of these devices and
continues to sell them as their ACT 1 Series.  I would recommend contacting
Actel for their recommendations on an alternative.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------

Ptmsa1 wrote in message <01bd3600$3fb3f4a0$50131fc4@rb>...
>We require information of anyone who might have stock of the TEXAS
>INSTRUMENTS TPC1020AFN-068C FPGA devices for purchase.
>
>We are looking of a quantity of 50. Could you please provide us with any
>information urgently!!!!
>
>Thank-you.
>Bossie


Article: 8973
Subject: Re: Free FPGA tools???
From: Edward Lee <epl@rocketmail.com>
Date: Tue, 10 Feb 1998 13:38:38 -0800
Links: << >>  << T >>  << A >>
&miker wrote:
> 
> Richard Schwarz wrote:
> 
> > Miker,
> >
> > For $350.00 you can get the ...snip
> 
> Thanks for the input.  I guess I should have explained the concept "free"
> :-).What I meant was, no cost, without payment, provided gratis by the vendor,
> 
...
>  The problem with FPGAs is that I can't find any affordable tools to
>  program them.  Does anyone support their
>  programmable devices with free base development software?  I don't need
>  anything more capable than PALASM.
> 
>  I have a second item on my wish list.  I'd like to be able to reprogram
>  an FPGA on the fly.
...
How about the AMD/Vantis Machxl 2.0?  You can download it free from
AMD/Vantis.
It's DOS based, but good enough for simple design.  It comes with lots
of
design reports and simulations.  You can program it ISP with a parallel
port
cable.  I tried out the software, but i have not actually programmed it
yet.
-- 
Embedded Programming Lab
http://www.glasscloth.com/epl
epl@rocket_dot_com (_dot_ -> .)
Article: 8974
Subject: PCI Prototyping Board(s)
From: "Yves Boudreault" <spamless_yboudreault@nospam_hyperchip.com>
Date: Tue, 10 Feb 1998 22:23:22 GMT
Links: << >>  << T >>  << A >>
Hi,

We are looking for FPGA prototyping boards with small to medium size FPGA
(10K gates with some RAM), that
would happily reside on the PCI bus - We would like to use it as a simple
communication interface between
a PeeCee and some other hardware we are developing...

Anyone knows of such cards ?

for email responses, please remove the "spamless_" at the beginning of my
address.

Thanks for you attention.

--
Yves Boudreault
Hyperchip Inc.
Disclaimer: Stated opinions are mine.





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