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Messages from 9600

Article: 9600
Subject: New infomation resource on embedded microprcessors
From: Chris Stephens <sales@FORTHINC.demon.co.uk>
Date: Wed, 25 Mar 1998 17:48:42 +0000
Links: << >>  << T >>  << A >>


    Looking for development tools for that embedded project ?
    ---------------------------------------------------------

COMSOL has just published a new database on its web site.  It covers 77 
different microprocessor families - use it to see which tools (compiler, 
simulator, RTOS, ICE or programmers) are available to work with which 
specific chip in the family.

                http://www.Computer-Solutions.co.uk

COMSOLs embedded microprocessor developers web site has the UK's widest 
range of products for engineers including:

        In-circuit emulators
        Assemblers
        C & C++ compilers
        Real-time executives
        Software simulators
        186-486 linkers
        Remote debuggers
        EPROM emulators
        EPROM-PAL-GAL-micro programmers
        GANG programmers
        CASE tools
        Forth systems from chips to Windows
        RS232 Debuggers
        PC instruments (Logic Analysers & DSOs)

-----------------------------------------------------------------------
If you would like information on any of our current products, or to be
emailed with info on new embedded products please email to the address 
below

-----------------------------
Chris Stephens                         E-mail: sales@computer-solutions.co.uk
Computer Solutions Ltd.                Phone & Fax: +44  (0)1 932 829 460
1a New Haw Road, Addlestone,
Surrey, KT15 2BZ  England              http://www.Computer-Solutions.co.uk   

For the largest range of embedded microprocessor development tools in the UK
Article: 9601
Subject: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
From: Caspar Steineke <Steineke@ihs.ee.tu-berlin.de>
Date: Wed, 25 Mar 1998 19:01:07 +0100
Links: << >>  << T >>  << A >>
Hi Peter,

you might want to check out Thesys' full-speed USB chip, the TH6501, at
this URL: http://www.thesys.de/index_n.htm
The datasheet has lots of examples explaining interfacing that chip to
various uC's. Beware of the limited serial clock speed between uC and
TH6501 though.

Caspar


Peter wrote:

> Hello,
>
> There are two speeds in USB: 1.5mbit/sec and 12 mbit/sec.
>
> There are lots of quite cheap chips for the slow speed - these are (or
> will be) used in mice, keyboards, and such.
>
> There are a lot fewer solutions for the high speed version, and I
> wonder just how hard this is to do in an FPGA. Xilinx XC4000 devices
> are finally, after all these years, getting cheap enough in 100+
> quantities to be used for this sort of thing in production.
>
> I want to make a USB peripheral device, not a hub. The FPGA would be
> talking to a fast and cheap 8/16-bit CPU with DMA, e.g. a Z180.
>
> I have seen some "IP" (trendiest word right now) cores for USB, in a
> recent Xilinx publication, but having seen some of the pricing in this
> market, this is likely to be expensive. And I have mislaid the book.
>
> Has anyone who can talk about it done this?
>
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to zX80@digiYserve.com but
> remove the X and the Y.



Article: 9602
Subject: Re: Partially reconfigurable FPGA
From: Caspar Steineke <Steineke@ihs.ee.tu-berlin.de>
Date: Wed, 25 Mar 1998 19:19:06 +0100
Links: << >>  << T >>  << A >>
Hi Scott,

Xilinx' XC6216 is probably what you are looking for. Besides supporting
rapid partial reconfiguration it is the only (correct me if I'm wrong) FPGA
with a documented bitstream format. The evaluation board from VCC looks very
promising. We tried to order one last year but after a dozen E-mails and
prospective lead times of several months we turned back to the 4000 series.
If you are more successful, please let me know.
I'm still very excited about the 6200 series and with an improved
uP-interface, more CLB's and a lower price tag those chips could be
excellent reconfigurable co-processors for the mainstream.

Caspar


Scott Bronson wrote:

> I'd like to make an ISA add-in card based on an FPGA.  It will include a
> small state machine to watch for data patterns on some lines (i.e., when
> 0x5F is immediately followed by 0x4C, then process the next five
> characters, etc.)  However, from time to time I'd like to be able to
> dynamically upload a new, completely different state machine from the
> computer.
>
> Does anybody make a device that will support this partial
> reprogramming?  I've heard that Altera has some rudimentary support in a
> few of their FPGAs, but that it's seriously difficult to work with.
> Thanks to their symmetry, I'd think that CPLDs with good interconnect
> would make this easy (as long as I leave a few CLBs unused, to be filled
> in later).  With all the reconfigurable computing research lately,
> there's got to be something...?
>
> Thanks for any leads,
>
>         - Scott                 NOsSPAMbronson@opentv.com
>
> (either follow up to this newsgroup or repair my E-mail address
> (sbronson) to reply.  Spammers are a real nuisance).



Article: 9603
Subject: Re: New radix-4 CORDIC for computing sine and cosine
From: peb@transcontech.co.uk ("Paul E. Bennett")
Date: Wed, 25 Mar 98 18:59:17 GMT
Links: << >>  << T >>  << A >>
In article <6f7e66$m5d$1@baygull.rtd.com> dgy@rtd.com "Don Yuniskis" writes:

> In article <35172689.1B5086C@computer.org>,
> Vitit Kantabutra  <vkantabu@computer.org> wrote:
> >I believe I have a new radix-4 CORDIC algorithm for computing sine and
> >cosine.  Unlike previously known algorithms, mine doesn't need extra
> >iterations and doesn't involve non-constant multiplicative factors.
> 
> From my foggy memory  :>  CORDIC only needed "double iterations"
> for some of the hyperbolic and *inverse* circular functions.
> sin() and cos() converge without the need for extra iterations.
> 
> >However, it does require a slow iteration on rare occasions.  I also
> >designed a Xilinx-based prototype of the new part of the circuit. Please
> >contact me if interested.
> 
> If you have this written as a software algorithm or in VHDL, I'd
> be interested in taking a peek...

Likewise, I'd like to see the paper and VHDL or software algorithm you
may have developed so far.

-- 
Paul E. Bennett ................... <peb@transcontech.co.uk>
Transport Control Technology Ltd.   <http://www.tcontec.demon.co.uk/>
+44 (0)117-9499861                  <enquiry@transcontech.co.uk>
Going Forth Safely

Article: 9604
Subject: Re: Lowest POWER FPGAs???
From: IJ.McCrum@ulst.ac.uk (I McCrum)
Date: Wed, 25 Mar 1998 21:12:45 GMT
Links: << >>  << T >>  << A >>
On Tue, 24 Mar 1998 23:07:15 -0500, Richard Schwarz
<aps@associatedpro.com> wrote:
>power consumption of FPGAs. I know these are design dependent, but there
I have just been looking into this, but for a very small design, (CPLD
really). Xilinx XC3000A are pretty low power. I opted for Phillips
CPLDs in the end because they look like they will give the best ratio
of microamps/cost. I'd have preferred the Xilinx route but the extra
cost of holding the bitstream plus the higher component cost weighed
against it.
Ian McCrum <IJ.McCrum@ulst.ac.uk>
Article: 9605
Subject: Re: Looking for space qualified FPGAs/ASICs
From: Gareth Baron <gareth.baron@eng.efi.com>
Date: Wed, 25 Mar 1998 13:12:48 -0800
Links: << >>  << T >>  << A >>
I think that ORBIT Semiconductor might do RAD-Hardened devices.  They will turn
your FPGA into a mask part for you.

----------------
Gareth Baron



Ray Andraka wrote:

> Stephen King wrote:
> >
> > We are looking to encode a complicated algorithm onto either an FPGA or
> > ASIC for space applications.
> >
> > We are interested to know of any space qualified:
> >
> > 1.) FPGAs,
> >
> > 2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc),
> >
> > 3.) Conventional ASIC processes.
> >
> > Thanks for you help in this matter.
> >
> > --
> > Stephen King
> > CRL
> > sking@crl.co.uk
>
> For FPGAs, Actel has a hardened line, I think they are in the 1280
> family.  A few years ago harris was working on a rad hard device too,
> but I don't know if it ever came to market.



Article: 9606
Subject: Verilog 2 VHDL
From: Gareth Baron <gareth.baron@eng.efi.com>
Date: Wed, 25 Mar 1998 13:15:47 -0800
Links: << >>  << T >>  << A >>
I'm looking for a shareware/freeware Verilog to VHDL translation tool.
It must run under DOS/WINTEL Machines.

I'm specifically after RTL translation and not behavioural.  If a
behavioural one is available please let me know where to get it.


TIA.

---------------
Gareth Baron
gareth.baron@eng.efi.com

Article: 9607
Subject: xilinx M1.4 / XC3000 problem
From: Christophe BARNICHON <c.barnich@wanadoo.fr>
Date: Wed, 25 Mar 1998 22:50:49 +0100
Links: << >>  << T >>  << A >>
We are updrading a XC3100A design but the PAR cannot place and route the
design any more. 
I have noticed some strange behavior of the xilinx Mapper: 
a common symbol such as a counter "CB8CLED" is mapped into  up to 12 or
14 CLB because the Clock Enabled logic generation is replicated into 
8  (half) CLBs. (The same logic function) 
This a huge lost of space !!!
Does anyone knows how to reduce that? (I know the xilinx mapper has a -l
option but this only works with XC4000)  

Thanks.
-- 
Christophe BARNICHON  
Please Email to Christophe.Barnichon@insalien.org
Article: 9608
Subject: Re: Partially reconfigurable FPGA
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Wed, 25 Mar 1998 21:20:32 -0500
Links: << >>  << T >>  << A >>
Scott Bronson wrote:
> 
> I'd like to make an ISA add-in card based on an FPGA.  It will include a
> small state machine to watch for data patterns on some lines (i.e., when
> 0x5F is immediately followed by 0x4C, then process the next five
> characters, etc.)  However, from time to time I'd like to be able to
> dynamically upload a new, completely different state machine from the
> computer.
> 
> Does anybody make a device that will support this partial
> reprogramming?  I've heard that Altera has some rudimentary support in a
> few of their FPGAs, but that it's seriously difficult to work with.
> Thanks to their symmetry, I'd think that CPLDs with good interconnect
> would make this easy (as long as I leave a few CLBs unused, to be filled
> in later).  With all the reconfigurable computing research lately,
> there's got to be something...?
> 
> Thanks for any leads,
> 
>         - Scott                 NOsSPAMbronson@opentv.com
> 

There are several partially reconfigurable devices on the market.  They
tend to be fine grained.  In alphabetical order: Atmel 6K, which is
descended from the concurrent logic design; Atmel 40K, a newer
generation with some improvements in routing and cell architecture;
Motorola, based on the pilkington architecture (I've not actually used
these); National Semiconductor Clay10 & CLay31, which are also
descendants of the CLI architecture and are almost identical to the
Atmel 6K; and Xilinx 6200, which is a hierarchical setup with some nice
features but not well suited to arithmetic applications.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 9609
Subject: Re: Dual port
From: Rick Collins <redsp@writeme.com>
Date: Wed, 25 Mar 1998 22:08:42 -0500
Links: << >>  << T >>  << A >>
Philip Freidin wrote:

> In article <35188CBE.2DD97143@writeme.com> redsp@writeme.com writes:
> >This is how it appears to the user, but obviously both ports are written at the
> >same time.
>
> Think of it this way: there is a LUT RAM (16 x 1), and it has a write
> address decoder, and a read address decoder. The address input lines of
> ...snip...
> LUT, the read address is independent. It can be watching the same
> address, or some other address.

I understand how the sync Rams work. I am questioning the why of it. I don't see any
reason for limiting the capability of the RAM in this way. The CLB could be used with
one 4 bit input as a write address, and the other a read address. Then you could
access two bits in a dual port manner. In another post you spoke of not being able to
READ two locations at the same time with this arrangement. But I would be willing to
bet that this memory is most often used to implement FIFOs rather than register
files. If you had a 2 bit dual port CLB, you would still have the option of using two
dual port, 2 bit CLBs for the redundant two read port register file while reserving
the option of using a single CLB for a 2 bit dual port FIFO. So this would have
provided more capablity to the users.

> >The only way to allow reads and writes without contention is to design
> >the RAM with dual access to each location. This requires a lot more real
> >estate than a simple RAM.
>
> But is inherently what was already there in the XC4000 (in terms of read
> and write decoders), before dual port was added.

I don't follow this. In the XC4000A, you only had a single 4 bit address input to the
RAM. So by definition they weren't dual port. The XC4000E is the first Xilinx 4000
part to have dual port RAM. My point is that within the CLB of the XC4000E, only one
RAM bit is truly dual port. The other RAM bit is either being read, or being written
and not both at the same time. So the two bits function differently while duplicating
the same data. If they had been made to work the same, you would have a 2 bit dual
port memory for use in FIFOs, etc..., without sacrificing any other capability.

> >If I can read write one port simultaneously, why can't I read write
> >different ports simultaneously?
>
> Because one port is a read/write port (the address input is used for both)
> and the other port is read only, because the writing is done from the
> first port.

But can't I simultaneously read at address A from the port with separate read and
write addresses and write to address B in the port with the read and write addresses
tied together?

> >My point about the memory cell is that the function generator that has
> >different read and write address ports MUST already be a fully dual port
> >memory. Why not make them both fully dual port and have it be two bits
> >wide?
>
> As described above, while the read and write structures are separate,
> they share the 4 address signals. To make them independent would require
> 4 more inputs to the CLB.

I disagree. The two RAM bits can share the read and write addresses. The addresses
only need to separate read from write. So the existing inputs can be used, one for
read, one for write.

I am not sure that we are communicating well. Is what I am saying not clear?

Rick Collins

redsp@writeme.com




Article: 9610
Subject: Re: xilinx M1.4 / XC3000 problem
From: Rick Collins <redsp@writeme.com>
Date: Wed, 25 Mar 1998 22:22:26 -0500
Links: << >>  << T >>  << A >>
Christophe BARNICHON wrote:

> We are updrading a XC3100A design but the PAR cannot place and route the
> design any more.
> I have noticed some strange behavior of the xilinx Mapper:
> a common symbol such as a counter "CB8CLED" is mapped into  up to 12 or
> 14 CLB because the Clock Enabled logic generation is replicated into
> 8  (half) CLBs. (The same logic function)
> This a huge lost of space !!!
> Does anyone knows how to reduce that? (I know the xilinx mapper has a -l
> option but this only works with XC4000)
>
> Thanks.
> --
> Christophe BARNICHON
> Please Email to Christophe.Barnichon@insalien.org

I am just starting to use these tools, but I believe one of the options on
the build is to prohibit the replication of logic. I think this is done to
improve the speed of some circuits.

Rick Collins

redsp@writeme.com



Article: 9611
Subject: Re: XactStep6 - The cure for a dongle
From: Rick Collins <redsp@writeme.com>
Date: Wed, 25 Mar 1998 22:39:51 -0500
Links: << >>  << T >>  << A >>
Don Husby wrote:

> nobody@REPLAY.COM (Anonymous) wrote:
> > P.S.
> > What do you think about similar patches for M1.4? Foundation?
> > Anyone interested?
>
> Viewlogic please!!
> As someone mentioned earlier, the Viewlogic licensing scheme is a pain in the
> ass, and often makes it impossible to use their software even with a valid
> license.
>
> --
> Don Husby <husby@fnal.gov>                        Phone: 630-840-3668
> Fermi National Accelerator Lab                      Fax: 630-840-5406
> Batavia, IL 60510

I'll second the pain in the rear opinion. In my last job, we bought two seats of
viewlogic. One was a full board seat, and to save money, the other was an FPGA
only seat. The problem was that if we tried to use the full board seat to do FPGA
design, we then couldn't read those schematics on the FPGA seat!!!

At that time we found that the magic number on the second line (if I remember
correctly) of the file only depends on the key and the file name. So if you make
the same file on the FPGA station and then copy the magic number to the file from
the board station, you can work with the file on the FPGA station.

This was still a pain in the but we found that it would allow us to use the two
stations the way we intended.

BTW, Xilinx had a program to restamp a file to the currently installed key. This
makes sense since they would be facing this problem in many of the files that
customers sent to them. But they wouldn't share it with us.

As for the dongle, I cracked the old Xilinx key as well as the Viewlogic key.
They were rather simple devices. The OLD Xilinx key was an 8 bit loadable
counter. One bit on the parallel port would load the hardcoded number into the
counter. A second bit would be toggled to decrement the counter. A parallel port
input was used to watch a zero detect output. When the zero detect tripped, the
number of clocks sent was the counter value. This value was odd for one type of
key and even for another type of key. The two types of key allowed you access to
different packages of software.

The viewlogic key is a serial EEPROM with some 128 bits or bytes of data. Each
software package was enabled by a magic number in a file, if I remember
correctly. This EEPROM could be read and written via the parallel port. I wrote
some software to do this and tested it. But I never built a blank duplicate key.

Does Viewlogic still use the same key? I know that Xilinx went to a more
encrypted key for awhile and now keys off of your C drive serial number if you
are not running off of a network.


Rick Collins

redsp@writeme.com



Article: 9612
Subject: Re: VHDL shareware editor?
From: Rick Collins <redsp@writeme.com>
Date: Wed, 25 Mar 1998 22:50:03 -0500
Links: << >>  << T >>  << A >>
Greg Prior wrote:

> Hi all-
>
> Due to a lack of an 'undo' function in the Xilinx Alliance tools, I am
> looking for a better editor.  I would like to try out a share one with
> the capability of multiple levels of 'undo'.  Also it should be VHDL
> aware, and highlite keywords, etc.  Can anyone point me to something?
>
> Thanks, Greg

Try posting your message in the comp.arch.vhdl newsgroup. I belive there
was a discussion on VHDL editors there just a week or two ago.

Someone mentioned Codewright as a VHDL editor. I have used it for C
programming and it does the usual auto indenting, keyword highlighting...
I does have multi level undo. I haven't tried it for VHDL, but I am sure
it would work reasonably well. It's not shareware, but they might have a
demo they could send you. It is from Premia at 503-641-6000. If you speak
with Dottie, tell her that Rick Collins sent you. She is very nice.


Rick Collins

redsp@writeme.com



Article: 9613
Subject: XactStep6 - The cure for a dongle
From: nobody@REPLAY.COM (Anonymous)
Date: 26 Mar 1998 06:54:51 +0100
Links: << >>  << T >>  << A >>
It is rude to cancel somebody's posts :-<
Perhaps someone would find it useful ;-)
You should've implemented smarter protection.

Here we go again...

begin 644 xpatch12.zip
M4$L#!!0````(`"=H;"0?(NL)K"(``*4C```,````6%!!5$-(,3(N15A%75IG
M6!-;M]XSR223228)(?06>JA2I0A*E0ZAB8`B4@0!E=Y$2.B$9@$;>L1>^50\
MQW8L5,6N8F\4Z4CO32[GW.<^S[UW_7C?M=>S]_S8:_U8^UWC%O`:$@$0(($>
M:'E9'@8P```:7?9:(9H(S\75R<>>8[LK-EZ7HV]FIJ=C9L#AN?A9>]ESG':&
MZG*L8V(X7MLC(A,3.%[A">'QR>%A9/"_[?8HX:X$C`"PA@2#!&D=#I@O>[V@
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M0L^@.I&2SEL/XM:OK.MK@;7KK;J_%5;JYZ^-N%(>^Q8V\FO^'H`]N=AL-`4_
MA;Y2@/W8P"'7JB*+;C2W-IT:9PZ0HR\UQW/=IM;0,K-_0GQXA/C(Y0%UJ44K
MEGP=L*L7\/L'6CZ/E+Z@?P(<9ODB?GGR6>$2/>6KG8;5FHP6&3__5X\\"X>/
M`F]O[Y+FIE_4PC=6;D>;RGY-M$L%^`)NU8QCP2.S@K-HZ8&++8"]@3QF2P1/
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M\S6B"J?9WTH"([P,;ZBN,ZJC:;SQ=:'7\__>^OO[>&?_[Z00F[!;@B@+#9/]
M-NX9%G(_MM<R-X4==3C:E)&MX/8J3#_=KX"P:9O_+=%S[B$7'H3KGKO3?OW)
MB5/W6GSDJ/N.#.,Y`V%!#+W/^YW>\H63>A.R=R337L+^9(MJ%:P331Z?_^EP
M^4D8=TGPVN;)EXL%?>'%X9$:^R-&+K?NOTMQ_GR]Z>KRNWCJEEN;5K_-N':W
MT[D)EJX0#O8\5LV?.R%WZ92U7!^TR<'\>.CK!UJVKZ?8.W94#+DUG!Y?5;V'
MQ+O9[)YMVY6O?>"+0%.E-&9FH()U_4:#/4U:)H"3!C7M]3[V75%95T7WTM6S
M0+-FX>!FO4#E&?/=+$AN/_%AQX#D^DL7[_`$=UP.G:_M-_Z^Y93I5T*)U9.'
MAA<50B>MGIU\CY7?BAW_:LH@E^_]ZO+7@X])[;Y#W3G#2+-;NEE61_G@.7K#
M$X_D\QUWL.\'&C:-/1Y:.)O[_4%1XYJX@*G%(D_I?+<ZVR/9GVP%P3WKIKP.
MU:2X-"3G*X"VKN&LVY^KGEF]4-WO6E_"T%FG;W9<ON;^)=;F7>\?BOV.7/5^
M_B5ZW"61_%]02P,$%`````@`CHMM)(G=V23H`0``D0,```P```!84$%40T@Q
M,BY.1D]]D\V.FS`41M=%XAUN=JV$`&,,F%TZR2C3)FV4I%(J9>,8$]`@.^)'
M"6\_-AEU2CI3RSO./?Y\N=X590-Z,\B4/%4">,WX,^2JAGU9E?(*^^G##B+7
M1]"HO+VP6KCPU,*9M;P0#;2%L*U<596ZE/($XBIXU[)CI3]]OA0E+Z!7'32%
MZJH,CMK=G2$OZZ;]DMJ6;4T7LV6P=^?[^2<P*R*A$]$`(,">CSQ*`!!*?:+)
M]<9@,%HD00Y-_`%'_@T/4TQMZ]M\%FCW?E2#2>S$-'K'OEY.MT^K,0T8^P["
M[X59_QLFT+FQ@Y/01/#\R#/G(#\-L6VYA]5TMWA8'][J_H_/5[^6?\$&CPEU
M<!S?X5B'V?[^L5O<18<(47T"U96!YX<W/$DQLBWS0^]@Y)`X<!*"]9V1YY,;
MCE.4:/SK\N>=7(=!L1,2TTCRQXX&_(/.A`[%YJJZD8E'X\&NZS4-Q`U<Q`&Z
M\ZEFF?@PH%;$9*0(TR"YS>?@*-\4MK7I)%R'(46!*ZX"2FDFL8;#E?$6LK(6
MO%5U[QIXIJ2`YBQXR:JJAV,/WX4$E<-F^SB\!3/#KP^DZ?)<U*)N)I.);:V8
M[*$MF'QNH%6P7@QX(:KSQ(AAM#:"][P2&6Q?7Q(\JDYFK"V5=`!1JOOW`E!+
M`0(4`!0````(`"=H;"0?(NL)K"(``*4C```,````````````(`````````!8
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`
end

P.S.
What do you think about similar patches for M1.4? Foundation?
Anyone interested?





Article: 9614
Subject: Re: Dual port
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 26 Mar 1998 06:41:21 GMT
Links: << >>  << T >>  << A >>
In article <WQFzZfAS5rF1EwXj@walker.demon.co.uk> Paul Walker <paul@walker.demon.co.uk> writes:
>
>But can anyone explain why some of Xilinx competitors provide genuine
>dual-port RAM and then insist that both ports are clocked by the same
>clock?

There are several levels of "dual ported-ness" out there. Here are a few,
and I'll leave the issue of "genuine" to the readership.

1) There are vendors that think that a single clock for both read and write
ports is good enough.

2) There are vendors that think that dual port RAMs with arbitration logic
(including NOT specifying the metastability failure rate for the arbiter)
is good enough. 

3) There are vendors that think that a busy line passed to the second 
domain, but clocked from the first domain is good enough.

4) There are vendors that think that a single port RAM with some sort of 
wrapper around it that shares the port to two domains is good enough.

5) There are vendors that think that the interface should support two
independent clocks, not have arbitration, and the only special case
you have to deal with is when one port is writing and the other
port is reading the same location, in which the system designer must
deal with the basically asynchronous fall through time. Note that in any 
well designed system, this case should never occur because of usually 
semaphore based locking schemes.

Personally, I like 5. This is what the XC4000E does. Version 1
may be usefull in systems where the domains are on the same clocks.
Version 2 and 3 are potentially disastrous, especially in the hands of 
less experienced designers.

I have designed devices that supported two write ports (AM29C334), 
in which case, if you tried to write to the same address from both ports, 
you got what you deserved. 

Philip.

Article: 9615
Subject: Re: Looking for space qualified FPGAs/ASICs
From: ees1ht@ee.surrey.ac.uk (Hans)
Date: 26 Mar 1998 09:04:53 GMT
Links: << >>  << T >>  << A >>
Stephen,

I found the following article on the "news channel",

SUNNYVALE, Calif.--(BUSINESS WIRE)--March 24, 1998--Actel Corporation (NASDAQ: 
ACTL) today announced the availability of a new radiation-hardened, 
non-volatile, field programmable gate array (FPGA), the 2,000 gate RH1020, 
specially designed for use in the growing telecommunications satellite market. 
The new device is the latest addition to Actel's industry-leading RadHard 
product line.

I am not sure if anybody mentioned Chip Express LPGA's. Have a look at Rickard 
Katz (http://flick.gsfc.nasa.gov/radhome/) QYH500 test report, looks pretty 
good. Also you might find the price of these devices (1 or 2 off) 
very interesting.

Good luck,

Hans.



In article <01bd5324$d36ff5e0$1d3872c1@sk_ii.crl.co.uk>, sking@crl.co.uk 
says...
>
>We are looking to encode a complicated algorithm onto either an FPGA or
>ASIC for space applications.
>
>We are interested to know of any space qualified:
>
>1.) FPGAs,
>
>2.) Low volume ASIC processes (e.g. laser programmable, shared wafer etc),
>
>3.) Conventional ASIC processes.
>
>Thanks for you help in this matter.
>
>-- 
>Stephen King
>CRL
>sking@crl.co.uk

Article: 9616
Subject: Re: CMOS or TTL?
From: "Yau Man Wai , Roger" <rogeryau@net.polyu.edu.hk>
Date: Thu, 26 Mar 1998 20:40:57 +0800
Links: << >>  << T >>  << A >>
Hello David,
For old type SPP or new EPP, you can choose TTL. In my opinion, you may
better insert a buffer (74LS245) or Schmitt Trigger (74LS14) and do some
termination at the end of the transmition line.
Regards,
Roger Yau
__________________________________________________________
Roger Yau
Electronic Engineer ( ASIC and DSP Dept. )
CASIL R & D Co., Ltd.
(A Subsidiary of China Aerospace International Holdings Ltd.)


Article: 9617
Subject: Re: CMOS or TTL?
From: "Yau Man Wai , Roger" <rogeryau@net.polyu.edu.hk>
Date: Thu, 26 Mar 1998 20:41:23 +0800
Links: << >>  << T >>  << A >>
Hello David,
For old type SPP or new EPP, you can choose TTL. In my opinion, you may
better insert a buffer (74LS245) or Schmitt Trigger (74LS14) and do some
termination at the end of the transmition line.
Regards,
Roger Yau
__________________________________________________________
Roger Yau
Electronic Engineer ( ASIC and DSP Dept. )
CASIL R & D Co., Ltd.
(A Subsidiary of China Aerospace International Holdings Ltd.)


Article: 9618
Subject: Command line input for Maxplus2?
From: yt <furnitec@singnet.com.sg>
Date: Thu, 26 Mar 1998 21:35:29 +0800
Links: << >>  << T >>  << A >>
Can Maxplus2 supports command line input to combine .sof files to .sbf ?
or any other method without using Maxplus2.

Regards
Verasco

Article: 9619
Subject: Re: XactStep6 - The cure for a dongle
From: husby@fnal.gov (Don Husby)
Date: Thu, 26 Mar 1998 14:21:58 GMT
Links: << >>  << T >>  << A >>
nobody@REPLAY.COM (Anonymous) wrote:
> P.S.
> What do you think about similar patches for M1.4? Foundation?
> Anyone interested?

Viewlogic please!!
As someone mentioned earlier, the Viewlogic licensing scheme is a pain in the 
ass, and often makes it impossible to use their software even with a valid 
license.



--
Don Husby <husby@fnal.gov>                        Phone: 630-840-3668
Fermi National Accelerator Lab                      Fax: 630-840-5406
Batavia, IL 60510
Article: 9620
Subject: Re: Looking for space qualified FPGAs/ASICs
From: "rk" <stellare@erols.com.NOSPAM>
Date: 26 Mar 1998 20:52:45 GMT
Links: << >>  << T >>  << A >>
Dave Hawkins <dwh@ovro.caltech.edu> wrote in article
<6fbfuo$62v@gap.cco.caltech.edu>...
: Try www.spec.com they are a company working under an
: SBIR (small business innovation and research (?)) grant.
: They supply radiation hardened FPGAs ... but I would
: imagine that it is at a price.


rk:
interesting ... didn't know that they are actually supplying them.
have then been tested and qualified yet?

--------------------------------------------------------------
rk

"there's nothing like real data to screw up a great theory" 
- me (modified from original, slightly more colorful version)
--------------------------------------------------------------
Article: 9621
Subject: Newbie question - FAQ for this group?
From: "Ian Stevenson" <ianstevenson@no-junk.saqnet.co.uk>
Date: 27 Mar 98 00:01:04 GMT
Links: << >>  << T >>  << A >>
Is there a FAQ for this group? I would be grateful if anyone can point me
in the right direction.
Cheers,
Ian

-- 
--------------------------------------------------------------------------
Spam block: Reply to 
ianstevenson@no-junk.saqnet.co.uk
only remove the text 'no-junk'
=====================================
Article: 9622
Subject: VHDL shareware editor?
From: Greg Prior <eng@digital-reflection.com>
Date: Thu, 26 Mar 1998 16:15:25 -0800
Links: << >>  << T >>  << A >>
Hi all-

Due to a lack of an 'undo' function in the Xilinx Alliance tools, I am
looking for a better editor.  I would like to try out a share one with
the capability of multiple levels of 'undo'.  Also it should be VHDL
aware, and highlite keywords, etc.  Can anyone point me to something?

Thanks, Greg

Article: 9623
Subject: FPGA design services
From: "Michelle Tran" <icommtek@fpga-design.com>
Date: Thu, 26 Mar 1998 22:06:58 -0500
Links: << >>  << T >>  << A >>
Hi Professionals,

We offer digital design services for all your FPGA/CPLD solutions.   Please
come to visit our Web site for more information.

http://www.fpga-design.com/


Michell Tran



Article: 9624
Subject: Re: Dual port
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Thu, 26 Mar 1998 23:49:17 -0500
Links: << >>  << T >>  << A >>
Rick Collins wrote:
> 

> I don't follow this. In the XC4000A, you only had a single 4 bit address input to the
> RAM. So by definition they weren't dual port. The XC4000E is the first Xilinx 4000
> part to have dual port RAM. My point is that within the CLB of the XC4000E, only one
> RAM bit is truly dual port. The other RAM bit is either being read, or being written
> and not both at the same time. So the two bits function differently while duplicating
> the same data. If they had been made to work the same, you would have a 2 bit dual
> port memory for use in FIFOs, etc..., without sacrificing any other capability.

Not true.  both rams can be simultaneously read and written.  One has
the constraint that the read address is the same as the write address. 
This is the same as the sync single ram mode.  I use the simultaneous
read/write from the same address extensively in my DSP work.

-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


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