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"Symon" <symon_brewer@hotmail.com> wrote in message news:445f4e03$0$15789$14726298@news.sunsite.dk... > > "John_H" <johnhandwork@mail.com> wrote in message > news:JpH7g.4786$k%2.1985@trnddc03... >> Symon wrote: >>> I think I'm skeptical because of the >>> 'room-temperature-glass-flows-myth'. (No, it doesn't!) >> >> Shame. Glass flows. You just don't "see" it flow so that makes it a >> myth for you? The plate glass in the Notre Dame cathedral has measurable >> differences in thickness from the top to the bottom as just one simple >> example. > Nope, in olden days making glass windows was tricky. The thickness across > the sheet wasn't constant. When they originally fitted the panes into the > frames, they fitted the thick bit at the bottom. > Cheers, Syms. > p.s. Interestingly enough, given what we're talking about, modern window > glass is made on top of a pool of molten tin! Google for "Pillington > Process". > Here's a link:- "Antique windowpanes and the flow of supercooled liquids" http://dwb.unl.edu/Teacher/NSF/C01/C01Links/www.ualberta.ca/~bderksen/windowpane.htmlArticle: 101901
Hypertransport offer 41GB/s speed. Maybe it is the best way to move data between PC and FPGA. WayneArticle: 101902
Hi Aurelian, my answers : 1. we start from the same bitfile where startup-clock is set to = CCLK. This is no problem because for JTAG configuration we use Impact or Chipscope and these tools replace the startupclock=CCLK in our bitfile automatically by startupclk=JTAGCLK. So apart from that different startup-option it really is the same configuration bitstream. 2. It is slave serial configuration : we use an external controller to program the devices. Just to make clear : the FPGA-done pin goes high at end of config as it should. Everything *seems* to behave normally and we have worked with this board + fpga-config stream for several months now. No real issues with functionality. But now I measure my output-clock and I notice we don't have any headroom left on our timing budget due to a supposedly slow output driver. I hope this clears up the situation. Best regards, BartArticle: 101903
the startup behaviour for slave serial and jtag is a little different, the way the actual 'startup' sequence is sent, etc.. done=1 doesnt meant that FPGA is configured or started it is possible that done goes high by jtag config while 1) FPGA is completly empty, no config at all 2) FPGA is loaded is corrupted bitstream 3) FPGA is loaded but not started GHIGH=0 but none of those seem to apply in your case, still check out the bitgen options and what is maybe even better, if you have suitable clock then use a USER clock as startup clock! of course sending a few more CCLKs after bitstream can also fix a problem sometimes it is safe to stream in plain .BIT file with extra leading bulls*** and shift in any ff's after the actual bitstream is completed (sure not to send sync again!) Antti PS I did not know that ChipScope is now fixing the startup clock, a few revisions ago it did not do thatArticle: 101904
We have a Xilinx Flash (XCF series I believe) that we would like to program in circuit from a microcontroller in order to support field reconfigurability. This flash has a JTAG backend. We were thinking about using the GPIO ports on a microcontroller to wiggle the JTAG lines and load the new files that way. Problem is we don't know much about the upper protocol involved in JTAG and the documentation seems hazy. Has anyone done something similar? Does software exist that will do this for us? Thanks, WPArticle: 101905
We've done something similar. Xilinx has a utility called "playxsvf" that can be probably modified to fit your environment. I changed it to work with a dedicated h/w shifter used to send the JTAGS data stream without requiring our host processor to do the low level bit banging. Look through the Xilinx app notes and you should be able to find the zip archive that has the source code you'll need. Good luck! John ProvidenzaArticle: 101906
"Derek Simmons" <dereks314@gmail.com> writes: |> Is there a recommended source control system? Subversion is one of the most popular ones today. It has become the de-facto successor of CVS, because it is very easy to understand for people used to CVS and fixes most of CVS's problems. In particular, in contrast to CVS, Subversion understands about renaming and copying files and subdirectories, and using this, it provides a far more elegant and flexible alternative to the branching and tagging mess of CVS. Subversion also has much better support for remote access than CVS. Definitely worth a try! The manual is at http://svnbook.red-bean.com/ A very good and mature tool for converting an existing CVS repository into Subversion is cvs2svn at http://cvs2svn.tigris.org/ Subversion, like CVS, is a set of command-line tools. If you want a Microsoft Windows GUI client for Subversion that integrates fully with Windows Explorer, try TortoiseSVN at http://tortoisesvn.tigris.org/. A comparison of source control systems is at http://better-scm.berlios.de/comparison/comparison.html MarkusArticle: 101907
Antti, I am not sure on the fixing of the startup clock by Chipscope. I just assumed Chipscope does this, but never mentions it. I have additional info on that and to me it makes this situation even stranger : When we config with Impact => Impact says it replaces CCLK by JTAGclk => "programming succesful", but GHIGH=0 When we config with Chipscope => chipscope does not replace CClk (?) => "programming succesful", and GHIGH=1. Could this strange behaviour of the tools be related to our problem ? BartArticle: 101908
I am looking for some assistance writing a driver and FPGA code to handle DMA on a PCI Express system. The FPGA is a Xilinx V2P with a Xilinx x4 PCIe LogiCORE (v3.0). I've scoured through the entire PCI Express Base Specification v2.0 (the Solari/Intel book) and DMA isn't mentioned once, as far as I can tell. I suppose it is at a higher level than the base spec covers. The Xilinx manuals don't mention it, either. I've also googled everywhere (websites, groups, etc.) for mention of PCI Express and DMA, to no avail. Where should I go to find out how PCI Express handles DMA? What should the TLP messages look like? Are there any reference designs / sample code available? I look forward to hearing from the community about this issue. Thank you, --Alex GrossArticle: 101909
well GHIGH is the signal that actually releases the IO enables! but if it is not asserted properly then it usually looks like all IO are input only, you seem to have partially/wrong enabled IOs any if there is some mess with GHIGH then it sounds like the right place to keep digging AnttiArticle: 101910
In article
<VbOdnQfqqqqJwsLZnZ2dneKdnZydnZ2d@comcast.com>,
songdrgn@g.m.a.i.l.n0.spam.com says...
[ ... ]
> I've scoured through the entire PCI Express Base Specification v2.0 (the
> Solari/Intel book) and DMA isn't mentioned once, as far as I can tell. I
> suppose it is at a higher level than the base spec covers. The Xilinx
> manuals don't mention it, either. I've also googled everywhere (websites,
> groups, etc.) for mention of PCI Express and DMA, to no avail.
PCI (express or otherwise) doesn't really support DMA as
such. Looking for bus mastering is much more likely to
get you useful information.
--
Later,
Jerry.
The universe is a figment of its own imagination.
Article: 101911"SongDragon" <songdrgn@g.m.a.i.l.n0.spam.com> wrote in message news:VbOdnQfqqqqJwsLZnZ2dneKdnZydnZ2d@comcast.com... >I am looking for some assistance writing a driver and FPGA code to handle >DMA on a PCI Express system. The FPGA is a Xilinx V2P with a Xilinx x4 PCIe >LogiCORE (v3.0). > > I've scoured through the entire PCI Express Base Specification v2.0 (the > Solari/Intel book) and DMA isn't mentioned once, as far as I can tell. I > suppose it is at a higher level than the base spec covers. The Xilinx > manuals don't mention it, either. I've also googled everywhere (websites, > groups, etc.) for mention of PCI Express and DMA, to no avail. > > Where should I go to find out how PCI Express handles DMA? What should the > TLP messages look like? Are there any reference designs / sample code > available? > > I look forward to hearing from the community about this issue. > > Thank you, > > --Alex Gross The DMA isn't done by the PCI express - it's done by the surrounding layers. The PCI, PCI-X, PCIe all have the ability to be a Master in a Burst transaction. For your FPGA to DMA to another system, the FPGA needs a request to master a transaction issued to the core. Once granted, the transaction will specify the location for the data transfer which has to be coordinated in your system, not in the PCIe core. The transaction can provide a complete payload or may be interrupted (at least in PCI/X land) to allow other higher-priority transactions to occur. Look at mastering transactions and post again with further questions.Article: 101912
As Antti sugested, just send more clocks (cclk) from your micro to make sure you move the configuration state machine, into a proper state. Aurash Antti wrote: > the startup behaviour for slave serial and jtag is a little different, > the way the actual 'startup' sequence is sent, etc.. > > done=1 doesnt meant that FPGA is configured or started > it is possible that done goes high by jtag config while > 1) FPGA is completly empty, no config at all > 2) FPGA is loaded is corrupted bitstream > 3) FPGA is loaded but not started GHIGH=0 > > but none of those seem to apply in your case, still check out the > bitgen options and what is maybe even better, if you have suitable > clock then use a USER clock as startup clock! > > of course sending a few more CCLKs after bitstream can also fix a > problem sometimes > it is safe to stream in plain .BIT file with extra leading bulls*** and > shift in any ff's after > the actual bitstream is completed (sure not to send sync again!) > > Antti > PS I did not know that ChipScope is now fixing the startup clock, a few > revisions ago it did not do that >Article: 101913
Can you successfully boot Linux from the MicroDrive shipping with the ML300 and then mount the NFS filesystem as root from the command prompt? - Peter chakra wrote: > Hi all, > > I am loading linux onto the ML300. I have created a zImage.elf file for > ppc with the drivers and bsps for the project created using the EDK.I > am booting from NFS, the board is the client and my system is the > server. while booting up i get the following error. > > .................................. > ................. > eth0: using fifo mode. > eth0: No PHY detected. Assuming a PHY at address 0. > eth0: Xilinx EMAC #0 at 0x40C00000 mapped to 0xC9070000, irq=31 > eth0: id 2.0h; block id 7, type 1 > NET4: Linux TCP/IP 1.0 for NET4.0 > IP Protocols: ICMP, UDP, TCP, IGMP > IP: routing cache hash table of 1024 buckets, 8Kbytes > TCP: Hash tables configured (established 8192 bind 16384) > eth0: Could not read PHY control register; error 19 > IP-Config: Complete: > device=eth0, addr=192.168.1.10, mask=255.255.255.0, > gw=192.168.1.1, > host=192.168.1.10, domain=, nis-domain=(none), > bootserver=192.168.1.5, rootserver=192.168.1.5, rootpath= > NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. > Looking up port of RPC 100003/2 on 192.168.1.5 > Root-NFS: Unable to get nfsd port number from server, using default > Looking up port of RPC 100005/1 on 192.168.1.5 > Root-NFS: Unable to get mountd port number from server, using default > eth0: Could not read PHY control register; err > > Coould anyone please guide me, as to what i am doing wrong, and > possible solution for this error. > > with warm regards, > chakra. >Article: 101914
Problem is fixed ! And yes, it was the (lack of) extra CCLK cycles that was causing the problem. To be more precise : actually we provided about 200 CCLK-cycles of clock activity after done goes high, but the small CPLD in between our controller and our fpga masked this. CPLD programming is changed, and fpga configures ok and starts up ok with a clean fast output clock. Thanks to all for suggestions. best regards, BartArticle: 101915
"Symon" <symon_brewer@hotmail.com> wrote in message news:445f5136$0$15789$14726298@news.sunsite.dk... > > "Symon" <symon_brewer@hotmail.com> wrote in message > news:445f4e03$0$15789$14726298@news.sunsite.dk... >> >> Nope, in olden days making glass windows was tricky. The thickness across >> the sheet wasn't constant. When they originally fitted the panes into the >> frames, they fitted the thick bit at the bottom. >> Cheers, Syms. >> p.s. Interestingly enough, given what we're talking about, modern window >> glass is made on top of a pool of molten tin! Google for "Pillington >> Process". >> > Here's a link:- > "Antique windowpanes and the flow of supercooled liquids" > http://dwb.unl.edu/Teacher/NSF/C01/C01Links/www.ualberta.ca/~bderksen/windowpane.html Thanks for the link. The information presents some concepts with glass deformation that I wasn't familiar with but the comment "This author believes that the correct explanation lies in the process by which window panes were manufactured at that time" without support for why the thicker end would always be installed on the bottom leaves me with the issue still open. I'll nudge it more toward "maybe." Apologies to those disturbed by how off topic this got.Article: 101916
Symon wrote: > I don't think Tin is viscoelastic. My point is that tin (and other > materials) only have this plastic deformation above the yield stress limit. So ... the real discussion is how the materials behave at 400G and more. When solder yields at very low presures and room temp, doesn't that raise a flag when subject to continuous long term 400G radials? The discussion about Si-O-Si bonds was interesting, and the effects of extra ions in the glass that greatly alter the strength of the glass to stress ... so what about Si doping in the substrate ... will it be stable at 400G for the long term? 400G is a pretty substantial force even on low masses.Article: 101917
Yes, 41GB/s would a nice rate for moving data around. Am I correct in assuming this would require a motherboard board with two or more 939 AMD sockets? Any idea how much effort would be involved in programming the host to move data between. I expect there are some open libraries for this sort of thing. Also, how much work to have the FPGA handshake the hypertransport protocol? Hopefully the FPGA board vendor would have this covered. Found this product, which looks interesting. Anyone know of other HT products of interest? http://www.drccomputer.com/pages/modules.html Seems the HT route could get expensive (more costly FPGA board + new motherboard & processor). Thanks all for the great discussion! --- PDTi [ http://www.productive-eda.com ] SpectaReg -- Spec-down code and doc generation for register mapsArticle: 101918
Part of the traditional military qualification of ceramic wire-bonded parts (bonding wires essentially unsupported in the cavity) was a centrifuge test at 20,000g (10 000 g for the larger parts.) Plastic encapsulated parts are not tested this way, since the test is considered meaningless (no chance to fail). Peter AlfkeArticle: 101919
JJ wrote:
> I have fantastic disbelief about that 6 ops /clock except in very
> specific circumstances perhaps in a video codec using MMX/SSE etc where
> those units really do the equiv of many tiny integer codes per cycle on
> 4 or more parallel 8 bit DSP values.
John, of course it is about peak performance, reachable with great effort.
But the existence of every accelerator is explained only when even that
peak performance is not enough. Otherwise you simply could write better
code at no additional hardware cost. I know that in most cases the CPU
sleeps because of lack of load or stalls because of a cache miss, but it
is completely different song...
> Now thats looking pretty much like what FPGA DSP can do pretty trivially
> except for the clock ratio 2GHz v 150MHz.
Yes, in my case a Cyclone @ 65MHz (130MHz internally + SDR interface,
260 MHz at the critical path with timesharing) is enough. But it is a
specialized
waveforming device, not a generic-purpose computer. As a processor, it could
reach 180MHz and then stabilize -- not an impressive value today, not to
mention
that it contsins no cache, as BRAMs are too precious resources to be wasted
that
way.
> A while back, Toms Hardware did a comparison of 3GHz P4s v the P100 1st
> pentium and all the in betweens and the plot was basically linear
Interesting. In fact I don't care about P4, as its architecture is one
big mistake, but linear speedup would be a shame for a Pentium 3...
> benchmark performance, it also used perhaps 100x the transistor count
Northwood has 55 million, the old Pentium had 4.5 million.
> as well and that is all due to the Memory Wall and the necessiity to
> avoid at all costs accessing DRAM.
Yes, that is true. 144 MiB of caches of a POWER5 does help.
A 1.5GHz POWER5 is as fast as a 3.2GHz Pentium 4 (measured
on a large memory-hungry application). But you can buy many P4s
at the price of a single POWER5 MQM.
> Try running a random number generator say R250 which can generate a new
> rand number every 3ns on a XP2400 (9 ops IIRC). Now use that no to
> address a table >> 4MB. All of a sudden my 12Gops Athlon is running at
> 3MHz ie every memory access takes 300ns
Man, what 4MiB... ;-) Our application's working set is 200--600MiB. That's
the PITA! :-/
> So on an FPGA cpu, without OoO, no Branch prediction, and with tiny
> caches, I would expect to see only abouit .6 to .8 ops/cycle and
> without caches
In a soft DSP processor it would be much less, as there is much vector
processing, which omits (or at least should) the funny caches built of
BRAMs.
> I have no experience with the Opterons yet, I have heard they might be
> 10x faster than my old 1GHx TB but I remain skeptical based on past
> experience.
I like the Cell approach -- no chache => no cache misses => tremendous
preformance.
But there are only 256KiB of local memory, so it is restricted to
specialized tasks.
Best regards
Piotr Wyderski
Article: 101920
Andreas Ehliar wrote:
> One interesting application for most of the people on this
> newsgroup would be synthesis, place & route and HDL simulation.
> My guess would be that these applications could be heavily
> accelerated by FPGA:s.
A car is not the best tool to make another cars.
It's not a bees & butterflies story. :-) Same with FPGAs.
> My second guess that it is far from trivial to actually do this :)
And who actually would need that?
Best regards
Piotr Wyderski
Article: 101921<fpga_toys@yahoo.com> wrote in message news:1147106043.216198.313570@j33g2000cwa.googlegroups.com... > > Symon wrote: >> I don't think Tin is viscoelastic. My point is that tin (and other >> materials) only have this plastic deformation above the yield stress >> limit. > > So ... the real discussion is how the materials behave at 400G and > more. > > When solder yields at very low presures and room temp, doesn't that > raise a flag when subject to continuous long term 400G radials? > Hi John, I agree it does raise a flag, but unless the engineer does the physics, they're unable to work out whether they'll be ok or not. It seems it's not to do with the acceleration, it's to do with the pressure in the tin. The total force divided by the total cross sectional area of all the BGA balls is what we're interested in. What I'm suggesting is doing the calculation. So, here's the sum. Solder ball diameter 3mm. Solder ball area = 7.1E-8 m^2 Let say we're using a 256 ball FPGA. Total xsectional area = 256 * 7.1E-8 m^2 = 1.8E-5 m^2 Ok acceleration = 400g = 4000 m/s^2 If the yield stress limit of tin is 10MPa ref. http://en.wikipedia.org/wiki/Tensile_strength to remain under the yield stress limit (YSL) Sn YSL > accel * mass-of-FPGA / X-sectional area 10E6 > mass * 4000 / 1.8E-5 Therefore the FPGA mass must be less than 10E6*1.8E-5/4000 i.e. less than 45 grams. > > The discussion about Si-O-Si bonds was interesting, and the effects of > extra ions in the glass that greatly alter the strength of the glass to > stress ... so what about Si doping in the substrate ... will it be > stable at 400G for the long term? 400G is a pretty substantial force > even on low masses. > To be pedantic, 400g is a pretty substantial _acceleration_ on a mass! The upshot is, if you want to put an unclamped FPGA in a tyre, I suggest your FPGA has big balls. (With apologies to AC/DC!) HTH, Syms. :-)Article: 101922
Hi Peter, could you please further elaborate this ? How is the checkerboard shift register different than the switching of every bit from high to low in terms of Icc and Vcc ? I would think that Icc behaviour is the same in both cases but what about Vcc ? If Vcc behaves different in both cases, what is the reason ? Thank you.Article: 101923
Let's remember that the g-forces have a direction (outward), and it is up to the pc-board designer to take advantage of this. Peter AlfkeArticle: 101924
"Peter Alfke" <peter@xilinx.com> wrote in message news:1147110712.154203.47590@i39g2000cwa.googlegroups.com... > Let's remember that the g-forces have a direction (outward), and it is > up to the pc-board designer to take advantage of this. > Peter Alfke > Peter, You raise an interesting point. I wonder if the yield stress limit is the same for compression as for expansion? Sod it, just epoxy the damn thing to the board! :-) Cheers, Syms.
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