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Messages from 10200

Article: 10200
Subject: Re: Xilinx Foundation and Linux
From: janovetz@ews.uiuc.edu (Jacob W Janovetz)
Date: 3 May 1998 14:58:04 GMT
Links: << >>  << T >>  << A >>
madarass@cats.ucsc.edu (Rita   Madarassy) writes:


>With all due respect, I do not understant why anybody likes Linux.
>It is obvious any UNIX like platform is fading away. Check out the guys
>from SUN: their system looks more and more like an NT. 
>The finally realized UNIX sucks.

>UNIX was never designed for interfacing with humans. It was rather designed
>to interface with phones!

>The PCs were blessed with an operating system designed for human beings
>(WIN 95 and even WIN NT). So why do you want to make your machine stupid
>by adding LINUX?
>Tell me about a serious EDA tool in the market that is rational enough
>to code for LINUX!!


LINUX machine:> uptime
 10:03am  up 33 days, 23:33,  4 users,  load average: 0.00, 0.01, 0.00
             ^^
             ^^

That's one reason.

   Cheers,
   Jake

--
   janovetz@uiuc.edu    | Once you have flown, you will walk the earth with
 University of Illinois | your eyes turned skyward, for there you have been,
                        | there you long to return.     -- da Vinci
        PP-ASEL         | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 10201
Subject: Re: Xilinx Foundation and Linux
From: cyliax@cs.indiana.edu (Ingo Cyliax)
Date: 3 May 1998 11:57:53 -0500
Links: << >>  << T >>  << A >>
Yes, I would love to have my FPGA place&route and Cad tools under Linux. I
use Win95/NT4.0 for FPGA P&R and Word. Win95 typically crashes 2-3 times
per work session, NT4.0 is better but needs to be rebooted for config. 
changes, it's also expensive. I do everything else under Linux on my 
notebook.  It never crashes and I can change PCCards and network configs.
without rebooting. Sometimes my Linux sessions run for 1-2 weeks before
I reboot usually just to run Win95. 

I don't just read my Email under Linux. I lay out PCBs, have a VHDL simulator
and much of my FPGA toolchain runs under Linux as well as the cross-compilers
(gcc) that I use for micros.  Finally, I prefer to write all my articles
documentation under Linux, and then convert them to Word as a final step.
Granted, Linux needs some care and feeding just as Win95/NT4.0 does in a
networked enrionment, but over all it crashes less for the workload I have
and I wish I had access to more tools on that platform.

Overall, I would say that I'm 10-20% more productive under Linux than Win95,
just because it crashes and hangs less. With NT4.0 my productivity more on
par with Linux, except that it's more expensive to run (memory, software, disk
space requirments). The user interface argument is irrelevent, since it
doesn't effect my productivity.

Anyway, your mileage may vary. I just want to see more EDA tools for Linux.

See ya, -ingo

In article <m3zpgzdhcl.fsf@ztransform.velsoft.com>,
Andrew Veliath  <andrewtv@usa.net> wrote:
>Hi,
>
>I'm using Xilinx Foundation M1.3 for a class, and am wondering if
>Xilinx will release a Linux version.  Under 95 things start to become
>unstable after a day or two for me (sometimes after a few hours even),
>and I have to reboot (I don't want NT either).
>
>I know they do make some software for various Unices, but a Linux
>version would be excellent.
>
>--
>Andrew Veliath
>andrewtv@usa.net, veliaa@rpi.edu


-- 
/* Ingo Cyliax, cyliax@derivation.com, Tel/Fax: 760-431-1400/1484 */
Article: 10202
Subject: Re: Xilinx Foundation and Linux
From: timolmst@cyberramp.net
Date: Sun, 03 May 1998 19:00:01 GMT
Links: << >>  << T >>  << A >>
z80@ds2.com (Peter) wrote:

>Have you tried NT4? Far better than win95. I would never use win95 for
>serious work.

I try hard not to use Win95 for anything.



Tim Olmstead
email : timolmst@cyberramp.net
Visit the unofficial CP/M web site.
MAIN SITE AT : http://cdl.uta.edu/cpm
MIRROR AT    : http://www.mathcs.emory.edu/~cfs/cpm

Article: 10203
Subject: Re: Xilinx Foundation and Linux
From: dfura@seanet.com (David Fura)
Date: Sun, 3 May 1998 12:35:21 MST
Links: << >>  << T >>  << A >>
In article <6ihd7o$i1q@darkstar.ucsc.edu> madarass@cats.ucsc.edu (Rita   Madarassy) writes:
>From: madarass@cats.ucsc.edu (Rita   Madarassy)
>Subject: Re: Xilinx Foundation and Linux
>Date: 3 May 1998 09:26:16 GMT


>With all due respect, I do not understant why anybody likes Linux.
For people who care about getting more work done faster Linux is the way to 
go.   If, on the other hand, your goal is to build up shoulder strength 
from muscleing your mouse all over the place, then windows is the way to 
go.

>It is obvious any UNIX like platform is fading away. Check out the 
guys>from SUN: their system looks more and more like an NT. >The finally 
realized UNIX sucks.
It is *not* obvious that UNIX is fading away.  Who told you this?

>UNIX was never designed for interfacing with humans. It was rather designed
>to interface with phones!
I haven't actually spoken to the designers, but UNIX seems to work 
pretty well for me.  You do need to have a keyboard installed.

>The PCs were blessed with an operating system designed for human beings
>(WIN 95 and even WIN NT). So why do you want to make your machine stupid
>by adding LINUX?
>Tell me about a serious EDA tool in the market that is rational enough
>to code for LINUX!!
Windows works well for people who use their machines once a week and can't be 
expected to remember commands.  Fine.  However, if you're using your machine 
every day in your work, then it is no problem to remember UNIX commands.  If 
you can't remember, well, that's what they make those yellow sticky papers 
for.  I don't know any UNIX-proficient engineers who are more proficient 
at their work using windows rather than UNIX, but I do know many cases where 
just the opposite is true.

David Fura
Levetate Design Systems, Inc.
Article: 10204
Subject: Re: Xilinx Foundation and Linux
From: Andrew Veliath <andrewtv@usa.net>
Date: 3 May 1998 21:22:01 GMT
Links: << >>  << T >>  << A >>

    > The PCs were blessed with an operating system designed for
    > human beings (WIN 95 and even WIN NT). So why do you want to
    > make your machine stupid by adding LINUX?  Tell me about a
    > serious EDA tool in the market that is rational enough to
    > code for LINUX!!

Maybe not too many for Linux (yet!), but Unix in general?  I think
quite a few (doh! :-).

I don't really want to respond to your message which had no purpose
other than to ask me _why_ I'm using Linux (I honestly have no
interest in making people want to use Linux, but find it highly
insulting when people think I'm an idiot for doing so--after all, I'm
not calling _you_ an idiot for using Windows), but I will this once
just to try to help you to understand why I use Linux (or for that
matter, FreeBSD, NetBSD, etc.).

Not everyone likes memory-hogging desktops.  I'd much rather type pppd
than 'rundll32 rnaui,RnaDial MyIsp', considering that I often disable
the explorer interface since I never use it to save memory.  I'd much
rather use bash than command.com or cmd.exe.  I prefer operating
systems which I don't have to reboot every time I load or unload a
system driver, can modify the source to my needs (i.e. write my own
drivers), can it stay up for months, and first and foremost, can
automate easily (how does one automate an entirely GUI driven machine
easily)?  GUIs are essential for some things, like entering schematics
and viewing timing simulations--not _everything_ like Microsoft would
like you to believe.  The NT command line is reminiscent of VMS like
the VAX in the hardware lab here.

Why not use NT?  Well, I have Linux and 95 on right now.  I use 95 for
hardware and software which is currently unsupported under Linux, such
as DVD Video and my TB Pinnacle soundcard.  However, in my spare time
I'm working on writing drivers to use these under Linux.  Having NT
on, which doesn't support much of my hardware, would be a waste of
space, and it doesn't read fat32 which I'm using for my 6.4GB whereas
Linux reads and writes it, which is good until I can get rid of 95.

I have free compiler tools which I just used to write a number of
useful filters for my assembler output for my FPGA CPU.  Speaking of
which, I also made nice use of flex and bison in addition to GNU gcc
and GNU make, not to mention extensive use of GNU Emacs.

I own Windows 95, Windows NT 3.51, Visual C++ 4.2, MASM 6.13 and
Visual Studio 97, but the latter two are academic versions, and GNU
Win32 gives me some of the Unix tools for free under Windows, albiet
it is much less stable.  Also I cannot write drivers under Windows
since I don't want to subscribe to MSDN for like $500 or whatever, in
addition to the what I've paid for the current tools I have over a few
years.  I do own Mathematica for Linux.

That all humans work better in a GUI _desktop_ is not true, some of us
work FAR better in a Unix shell-oriented environment, and if you
really want a graphical _desktop_ (again, note the difference between
a GUI application and desktop) use KDE or Gnome.  They're free.  95
and NT are a lot of $$$ for buggy software which doesn't have a
compiler or DDK.

Hopefully this provides you with at least a few reasons why I use
Linux--which I've been using since 1993.

-- 
Andrew Veliath
andrewtv@usa.net, veliaa@rpi.edu

>>>>>  Someone writes:

    > With all due respect, I do not understant why anybody likes
    > Linux.  It is obvious any UNIX like platform is fading
    > away. Check out the guys from SUN: their system looks more
    > and more like an NT.  The finally realized UNIX sucks.

    > UNIX was never designed for interfacing with humans. It was
    > rather designed to interface with phones!

    > The PCs were blessed with an operating system designed for
    > human beings (WIN 95 and even WIN NT). So why do you want to
    > make your machine stupid by adding LINUX?  Tell me about a
    > serious EDA tool in the market that is rational enough to
    > code for LINUX!!

    > In article <m3zpgzdhcl.fsf@ztransform.velsoft.com>, Andrew
    > Veliath <andrewtv@usa.net> wrote:
    >> Hi,
    >> 
    >> I'm using Xilinx Foundation M1.3 for a class, and am wondering
    >> if Xilinx will release a Linux version.  Under 95 things start
    >> to become unstable after a day or two for me (sometimes after a
    >> few hours even), and I have to reboot (I don't want NT either).
    >> 
    >> I know they do make some software for various Unices, but a
    >> Linux version would be excellent.
    >> 
    >> -- Andrew Veliath andrewtv@usa.net, veliaa@rpi.edu
Article: 10205
Subject: Re: Xilinx Foundation and Linux
From: Rickman <spamgoeshere1@yahoo.com>
Date: Sun, 03 May 1998 21:38:27 -0400
Links: << >>  << T >>  << A >>
Ingo Cyliax wrote:
> 
> Yes, I would love to have my FPGA place&route and Cad tools under Linux. I
> use Win95/NT4.0 for FPGA P&R and Word. Win95 typically crashes 2-3 times
> per work session, NT4.0 is better but needs to be rebooted for config.
> changes, it's also expensive. I do everything else under Linux on my
> notebook.  It never crashes and I can change PCCards and network configs.
> without rebooting. Sometimes my Linux sessions run for 1-2 weeks before
> I reboot usually just to run Win95.
> 
> I don't just read my Email under Linux. I lay out PCBs, have a VHDL simulator
> and much of my FPGA toolchain runs under Linux as well as the cross-compilers
> (gcc) that I use for micros.  Finally, I prefer to write all my articles
> documentation under Linux, and then convert them to Word as a final step.
> Granted, Linux needs some care and feeding just as Win95/NT4.0 does in a
> networked enrionment, but over all it crashes less for the workload I have
> and I wish I had access to more tools on that platform.
> 
> Overall, I would say that I'm 10-20% more productive under Linux than Win95,
> just because it crashes and hangs less. With NT4.0 my productivity more on
> par with Linux, except that it's more expensive to run (memory, software, disk
> space requirments). The user interface argument is irrelevent, since it
> doesn't effect my productivity.
> 
> Anyway, your mileage may vary. I just want to see more EDA tools for Linux.
> 
> See ya, -ingo
> 
> In article <m3zpgzdhcl.fsf@ztransform.velsoft.com>,
> Andrew Veliath  <andrewtv@usa.net> wrote:
> >Hi,
> >
> >I'm using Xilinx Foundation M1.3 for a class, and am wondering if
> >Xilinx will release a Linux version.  Under 95 things start to become
> >unstable after a day or two for me (sometimes after a few hours even),
> >and I have to reboot (I don't want NT either).
> >
> >I know they do make some software for various Unices, but a Linux
> >version would be excellent.
> >
> >--
> >Andrew Veliath
> >andrewtv@usa.net, veliaa@rpi.edu
> 
> --
> /* Ingo Cyliax, cyliax@derivation.com, Tel/Fax: 760-431-1400/1484 */

-- 
I don't have a strong opinion either way in this discussion. I am using
Win95 based tools mainly because I am rather Unix/Linux ignorant. 

I am curious about why no vendors have jumped in to offer any comments.
Can we find out what the vendors are planning, or thinking about
planning, or what questions they might have about this topic??? 

Hello vendors?? Anybody out there?


Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10206
Subject: Re: Xilinx Foundation and Linux
From: Zoltan Kocsi <root@127.0.0.1>
Date: 04 May 1998 12:38:27 +1000
Links: << >>  << T >>  << A >>
madarass@cats.ucsc.edu (Rita   Madarassy) writes:

> With all due respect, I do not understant why anybody likes Linux.
> It is obvious any UNIX like platform is fading away. Check out the guys

That's what Microsoft wants you to believe...

> from SUN: their system looks more and more like an NT. 

No, Solaris is not that bad.

> The finally realized UNIX sucks.

Well, does it ? In what sense does it suck ? Have you actually tried it ?

> UNIX was never designed for interfacing with humans. It was rather designed
> to interface with phones!

You may want to read the classic book "The UNIX Operating System" from 
Kernigham and Pike; just skip the techno part and read why and how unix
was designed. Also, the book "25 years of unix" gives some insight.
Unix *was* designed to interface with humans. At least, with a
subset of them - the ones who think :-). 
Anyway, could you tell me how to interface X11 with my phone ?
It sounds to be a cool idea, I just can't figure out how, because when I
try to plug my phone to the machine's video output it always sparcs.

> The PCs were blessed with an operating system designed for human beings
> (WIN 95 and even WIN NT). So why do you want to make your machine stupid
> by adding LINUX?

For example, because a) NT can not handle my hardware (I tried), b) Linux
is smaller, quicker, more stable c) Linux is unix-like therefore much more 
productive if you do development work d) Linux is free e) Linux is less
buggy and bugfixes/support is much better than even commercial unices not
to mention Windows f) I can do all sorts of remote X11 and distributed
computing so I don't have to run from machine to machine g) Linux talks
to my Sun Sparc and my 68k BSD box happily h) the availability of the source
allows me to write/use/modify all sorts of device drivers for weird HW
that I want to use i) it runs on almost any machine j) I could not get
useful info from NT's help/log system when I tried NT and had a problem
(and I had, lots) and I can always figure out what goes wrong on Linux 
k) I can configure it to suit my needs, environment and taste 
l) I like Linux :-)

Enough ?

One more (under the belt, I admit) comment: Your machine will not be 
smarter by putting Windows on it. It is only the ratio of the machine's
IQ and the user's IQ which makes it look like that after the user worked
with Windows for a while :-P

(Flame me if you like, I always wear my asbestos gloves when posting 
on usenet.)

> Tell me about a serious EDA tool in the market that is rational enough
> to code for LINUX!!

If by serious you mean expensive :-) :

Oliver Bartels GmbH: schematic capture and PCB designer w/ autorouter.
    (If you buy before July, Bartels gives you an about 50% discount on 
	 the Linux version and they had a 80% discount until 1st Jan, '98.)
Fintronic: Finsim Verilog simulator 
Veritools: Undertow waveform viewer for various Verilog simulators
InterHDL: VHDL <-> Verilog translator, Verilog linter
RTDA: VOV, a large design management tool
QuickTurn: Simulation and design verification

There are others, mostly in the simulation/support area. Unfortunately, 
the only synthesis tool I know for Linux was from Exemplar but AFAIK they 
ditched it. No P&R that I know of.

There are two projects, a free Verilog and a free VHDL simulator currently
running. A schematic entry/PCB design package is being written by a guy,
it's in early alpha now. They all will be free, so no serious stuff here,
I guess, but might be of interest of less serious unix users.

In addition, you may be surprised but private email conversations revealed
that some EDA tool makers actually use Linux for development, only they do
not release the Linux version for it "has no significant market share".

By the way, I wonder when will the free SW community jump on synthesys ?

Zoltan

-- 
+------------------------------------------------------------------+
| To reach me write to zoltan in the domain of:    bendor com au   |
+--------------------------------+---------------------------------+
| Zoltan Kocsi                   |   I don't believe in miracles   |  
| Bendor Research Pty. Ltd.      |   but I rely on them.           |
+--------------------------------+---------------------------------+
Article: 10207
Subject: How to make FIFO's in Altera FLEX8000 or FLEX6000
From: pesc@telindus.be
Date: Mon, 04 May 1998 01:46:40 -0600
Links: << >>  << T >>  << A >>
Does anyone know how to make a 'real' FIFO in a FLEX8000 or FLEX600.
With real I mean not the Cycle shared FIFO offered in the MAX+2 toolchain
but one with completely different read and write clocks (call it
an asynchronous FIFO if you'd like).

Due to the fact that Altera doesn't have dual port RAM (except in the
near future with FleX10KE series) this is a real problem.


-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10208
Subject: Re: Make a delay in Altera
From: staylor@dspsystems.com
Date: Mon, 04 May 1998 01:58:15 -0600
Links: << >>  << T >>  << A >>
In article <354C4B27.7D05@isee.zju.edu.cn>#1/1,
  zhangy@isee.zju.edu.cn wrote:
>
> I've seen so many discussion about the delay in Xilinx, Who knows how to
> make a dalay in Altera FPGA, EPF10k,EPF8k,etc.?
>

There is no way to make a predictable delay in an Altera devices except with
a clock, by pipelining, or an external delay line.

Scott Taylor - DSP Fibre Channel Systems

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
http://www.dejanews.com/   Now offering spam-free web-based newsreading
Article: 10209
Subject: Re: Creating a clock with a clock enable
From: "Richard Iachetta" <iachetta@us.ibm.com>
Date: 4 May 1998 16:49:32 GMT
Links: << >>  << T >>  << A >>
Nestor Caouras <nestor@ece.concordia.ca> wrote in article
<354A3A5B.7107@ece.concordia.ca>...
> Hi.
> 
> I was trying to write some VHDL code to generate a new clock based on
> another clock and a clock enable (CE) control pin.  The goal of my
> design is to output a clock pulse that is the same frequency as the
> input clock but would be zero if the CE would be zero. When the CE is
> one, then the generated clock should look exactly like the original
> input clock. Ideally, I would like the clocks to be exactly
> synchronized, but I can live with a delay of one clock period.
> 
> I guess this problem is similar to having a 2 input AND gate, whose one
> input accepts the original clock and the other input accepts the CE
> signal. 
> 
> I have tried to use the input clock (clk) that I am using in the 
> "if (clk'event and clk='1') then..." statement as an input to an and
> gate, but Synopsys doesn't like this syntax at all and generates an
> error.
> 
> I have also tried using variables, but this method only outputs a single
> pulse that is high when CE='1' and low when CE='0', but there are no
> transitions.  I'm attaching a part of my code for anyone who has dealt
> with such control signals.
> 
> 
> Any help would be greatly appreciated.
> 
> Thanks in advance.
> 
> Nestor Caouras
> nestor@ece.concordia.ca
> http://www.ece.concordia.ca/~nestor/addr.html 
> |-------------------------------------------|
> | Dept. of Electrical and Computer Eng.     |
> | Concordia University                      |
> | 1455 de Maisonneuve Blvd (West)           |
> | Montreal, Quebec, Canada H3G 1M8.         |
> | Tel: (514)848-8784    Fax: (514)848-2802  |
> |-------------------------------------------|
> library IEEE;
> use IEEE.STD_LOGIC_1164.all;
> use IEEE.std_logic_unsigned.all;
> 
> entity arctan_control2 is
>   port( ready, slowclk, reset: in std_logic;
> 	clkout : out std_logic);
> end arctan_control2;
> 
> -- slowclk is the original input clock operating at frequency Fz MHz
> -- ready is a signal that determines the value of the clock enable (CE) 
> --   input used for the generated output clock "clkout"
> 
> 
> architecture behv of arctan_control2 is
> signal ready_old : std_logic;
> signal clk_net : std_logic;
> 
> begin
> 
>   clk_net <= slowclk;
> 
>   control: process (slowclk,ready,reset)
>     variable valid  : boolean;
>     variable cnt : std_logic_vector(2 downto 0);
>     variable CE : std_logic;
>     variable clk_tmp : std_logic;
> 
>   begin
>     if (reset = '1') then
> 
>        ...
> 
>     elsif (slowclk'event and slowclk='1') then
>       clk_tmp := '1';	-- this could be changed or removed depending
>       if (ready_old = '0' and ready = '1') then	-- if a rising edge
transition was 
> 						-- detected from previous value of "ready"
> 						-- to current value of "ready", then set
> 						-- "valid" flag to TRUE
>         valid := true;
>         cnt := "000";	-- initialize the counter to zero
>       end if;
> 
>       if valid then
>         if cnt < 6 then		-- count for 6 clock cycles and keep
>   	  cnt := cnt + 1;	-- CE high
>   	  CE := '1';
>  	else
> 	  cnt := "000";		-- the max count was reached and CE is
> 	  CE := '0';		-- set back to low.
> 	  valid := false;	-- control flag "valid" also reset
>  	end if;
>       end if;
> 
>       ready_old <= ready;	-- store the current value of ready for 
> 				-- use in the next cycle
>       clkout <= clk_tmp and CE;	-- generate the output clock
> 
>     end if;
> 
>   end process;
> 
> end behv;

Forget about clk_tmp.  You want clkout <= slowclk and CE;  I don't like that
this statement is inside of an IF that only gets evaluated on rising clock
edges.  That is probably what Synopsys is complaining about.  Bring CE (or a
signal copy of it) out of this process and make the clkout <= slowclk and CE;
statement its own process.

-- 
Rich Iachetta
IBM Corporation
iachetta@us.ibm.com


Article: 10210
Subject: Re: How to make FIFO's in Altera FLEX8000 or FLEX6000
From: "Richard Iachetta" <iachetta@us.ibm.com>
Date: 4 May 1998 17:03:10 GMT
Links: << >>  << T >>  << A >>

pesc@telindus.be wrote in article <6ijo8g$r2a$1@nnrp1.dejanews.com>...
> Does anyone know how to make a 'real' FIFO in a FLEX8000 or FLEX600.
> With real I mean not the Cycle shared FIFO offered in the MAX+2 toolchain
> but one with completely different read and write clocks (call it
> an asynchronous FIFO if you'd like).
> 
> Due to the fact that Altera doesn't have dual port RAM (except in the
> near future with FleX10KE series) this is a real problem.
> 
> 
> -----== Posted via Deja News, The Leader in Internet Discussion ==-----
> http://www.dejanews.com/   Now offering spam-free web-based newsreading

One possiblity (if there are enough LC's): make the fifo out of flip-flops
instead of RAM.

-- 
Rich Iachetta
IBM Corporation
iachetta@us.ibm.com


Article: 10211
Subject: Re: DSP in an Altera or Xilinx?
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Mon, 04 May 1998 14:38:53 -0400
Links: << >>  << T >>  << A >>
Al wrote:
> 
> We're looking at implementing a good portion of our DSP algorithms in
> programmable parts due to the amount of parallelism required that typical
> DSPs cannot handle.  We currently have a product which uses several of the
> components and basic techniques we would like to use again but it's running
> awfully hot in an Altera 10K50 part.  I'm currently trying to evaluate
> which part, Altera or Xilnx, would be more fitting for DSP applications
> with better power/heat characteristics.  Can anyone provide arguments for
> one or the other?  Power consumption and dense designs for many 16-bit MACs
> and FIRs running at 50 MHz will be the primary resident in these parts.
> 
> Thanks for any input.
> 
> Al

In most DSP applications I find the Xilinx 4K architecture to be far
superior to the Altera 10K.  Here is my reasoning: 

1. The LUT structure in the ALtera is a 4 LUT, like the Xilinx. 
However, to use the built-in carry, Altera breaks it into a pair of 3
LUTs, one of which is the carry function and the other of which is your
arithmetic function. This effectively limits functions with carry to two
inputs if you wish to stay in one logic level (An adder-subtractor of
instance is forced to two logic levels).  If you decide to use clock
enable, it also uses up a LUT input, so it is difficult to combine the
CE with arithmetic. 
2. Because the Carry chain cannot skip LEs, you must go out on the row
connects to implement two or more level logic in combination with carry
chains.  This uses up routing and slows the result down.  There is no
dedicated route to adjacent LABs.
3. DSP functions are largely pipelined datapath.  Pipelined data path
has locally intensive routing, but has very little long distance or
global route.  This means in devices like the xilinx 4K there is little
problem with route congestion (assuming you floorplan).  In the Altera
10K, anything that is not in the 8 LEs of a LAB has to go out on the Row
or column routing, which is essentially a global route.  There are many
instances where you can use up routing long before you use up logic.  (a
CORDIC processor which is a chain of interconnected adder-subtractors is
such an example.  Each stage in the chain needs to use two global routes
per bit, one for the intermediate result and one for the
adder-subtractor sum.  The end result is to build this, you need to use
a device roughly twice as big as the logic alone dictates).  Of course
driving the long interconnect uses more power as well.
4.  DSP pipelines often involve delay queues to match pipeline delays in
parallel paths.  The ability to use Xilinx LUTs as memory makes a
compact 1 or 2 bit delay of up to 32 clocks using one LCA plus a small
LFSR counter (which can be shared among many delays).  Altera does not
have this small ram capability, so pipeline delay queues end up taking
an LE per bit per clock.

In applications where you can take advantage of the EABs, the Altera
device does a little better.  An example is a logarithm function, which
can be implemented as a 256x5 table plus a barrel shifter.  The table is
easily done in an EAB, and each stage of the barrel shift can be
implemented in a single logic level (the cascade connections make the
barrel shift more efficient too).  Unfortunately, the EABs are
relatively scarce, so their usability is limited.

Altera's use of global routing does make the device less sensitive to
placement, and makes for a more synthesis friendly architecture. The
cost for DSP applications is substantial, as outlined above.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka

The Andraka Consulting Group is a digital hardware design firm
specializing in high performance FPGA designs for digital signal
processing, computing and control applications.
Article: 10212
Subject: Reminder - The PLD & FPGA Conference & Exhibition 12/5/98
From: johnnyick@aol.com (Johnnyick)
Date: 04 May 1998 22:13:49 GMT
Links: << >>  << T >>  << A >>
For the latest developments in PLD & FPGA technology visit the Eighth Annual
Advanced PLD & FPGA Conference & Exhibition. For more details on the programme,
exhibitors and how to register on-line go to http://www.pldconf.com
Article: 10213
Subject: Re: Altera 10K20 Configuration problem
From: "Blaine" <blaine@flash.net>
Date: 5 May 1998 00:08:02 GMT
Links: << >>  << T >>  << A >>
Make sure nStatus and CONF_DONE are pulled up with about 1K.

Lev Razamat <lrazamat@netvision.net.il> wrote in article
<6hpl6k$ecg$1@news.netvision.net.il>...

John Huang wrote in message <353F9085.1156C0A4@tpts4.seed.net.tw>...
>Hi all:
>    I've use altera 10K20 (240 pin) in my design,
> but when I use the BYTEBlaster to download the
>sof file, I found the fpga didn't work, all I/O pins
>are present high or Hi-Z, I'm sure the download
>procedure was successful, the MaxPlus II tell me
>it work fine, and I had see the all signal is work when
>download(Status, DCLK, D0, Conf, CONF_DONE)
>and CE, MSEL0, MSEL1 is connected with ground,
>why the chip don't work, please someone help me
>thanks
>
>    John Huang
>

Please, check Global Project Device Options 
In this menu User-Supplied Start-Up Clock should be unchecked
Same option also present in device option.
After downloading ALTERA finished initialization procedure after additional
~10 clocks. And BYTEBlaster provides this clocks.
Good luck 
 Lev

----------

Article: 10214
Subject: Re: Hotworks G1 step clock
From: Steve Casselman <sc@vcc.com>
Date: Tue, 5 May 1998 01:59:22 GMT
Links: << >>  << T >>  << A >>
Reid Porter wrote:

> I'm having a bit of trouble getting the G1 step clock going on a
> Hotworks 6216 board. Has anybody had more success? Is there something
> tricky I should know about?
>

Look in the new pcitest program there is a function
called clkctl. Which controls the clock registers.
Its memory offset is 0xC00008
bit0 is gclk control when this is 1 bit1 controls
       single stepping mode.
bit1 single stepping mode (only when bit0 is set). The
       reference design uses 2 different I/O calls where as
       we just have one memory mapped call.
bit 2 => 1 set the g1 clock into continuous mode
        => 0 single step mode.
bit 3 => 1 turns on g1 tri-state buffer
        => 0 tri-states g1 buffer

so
XC6200DS Board;
unsigned int ctl = 8;
Board.writeRAM(0xC00008, &ctl, 1 );

sets the g1 clock on in single step mode
with gclk still respecting the old programmed
calls.

XC6200DS Board;
unsigned int ctl = c;
Board.writeRAM(0xC00008, &ctl, 1 );

sets g1 in continuous mode.

To be compatible with the xilinx reference I had to
start the g1 clock pin tri-stated so you much write
a value (in the code) that sets the g1 tri-state line
before you load any circuits (otherwise the g1
clock is a floating input to your design). In the
reference design both g1 and  g2 are tri-stated.

Now on g2 I ran the output of the programmable
clock so I would have a clock always going to the
xc6200 so I could reboot the xc4000 chip (only
supported on the Fat Hotworks). This allows
the user to completely swap out the PCI interface,
which of course gets reloaded with the PCI data
to continue on it's way. We are calling the HOT
Swapping and is a way to do PCI development,
as well as a way to research both course and
fine grain architectures together.

--
Steve Casselman, President
Virtual Computer Corporation
http://www.vcc.com


Article: 10215
Subject: Radix-4 CORDIC pipeline -- which chip?
From: "Prof. Vitit Kantabutra" <kantviti@isu.edu>
Date: Mon, 04 May 1998 21:29:04 -0600
Links: << >>  << T >>  << A >>
I'm new to fpga's, and am trying to implement a 12-bit input/output
(17-bit internal) parallel radix-4 CORDIC pipeline (using my own
algorithm).  I'm wondering whether I should use Xilinx 4K, Spartan, or
Atmel.  

By the way, I figured out how to do carry-save adders in my particular
application in Xilinx 4K (my application involves reducing 4 binary
operands into two, then with a regular adder from two down to one) --
Just use the two full adders that are stuck together in the same CLB on
different levels.  Then I don't seem to waste anything, so to speak.
Article: 10216
Subject: Re: DSP in an Altera or Xilinx?
From: Rickman <spamgoeshere1@yahoo.com>
Date: Mon, 04 May 1998 23:30:02 -0400
Links: << >>  << T >>  << A >>
Ray Andraka wrote:
> 
> Al wrote:
> >
> > We're looking at implementing a good portion of our DSP algorithms in
> > programmable parts due to the amount of parallelism required that typical
> > DSPs cannot handle.  We currently have a product which uses several of the
> > components and basic techniques we would like to use again but it's running
> > awfully hot in an Altera 10K50 part.  I'm currently trying to evaluate
> > which part, Altera or Xilnx, would be more fitting for DSP applications
> > with better power/heat characteristics.  Can anyone provide arguments for
> > one or the other?  Power consumption and dense designs for many 16-bit MACs
> > and FIRs running at 50 MHz will be the primary resident in these parts.
> >
> > Thanks for any input.
> >
> > Al
> 
> In most DSP applications I find the Xilinx 4K architecture to be far
> superior to the Altera 10K.  Here is my reasoning:
> 
> 1. The LUT structure in the ALtera is a 4 LUT, like the Xilinx.
> However, to use the built-in carry, Altera breaks it into a pair of 3
> LUTs, one of which is the carry function and the other of which is your
> arithmetic function. This effectively limits functions with carry to two
> inputs if you wish to stay in one logic level (An adder-subtractor of
> instance is forced to two logic levels).  If you decide to use clock
> enable, it also uses up a LUT input, so it is difficult to combine the
> CE with arithmetic.
> 2. Because the Carry chain cannot skip LEs, you must go out on the row
> connects to implement two or more level logic in combination with carry
> chains.  This uses up routing and slows the result down.  There is no
> dedicated route to adjacent LABs.
> 3. DSP functions are largely pipelined datapath.  Pipelined data path
> has locally intensive routing, but has very little long distance or
> global route.  This means in devices like the xilinx 4K there is little
> problem with route congestion (assuming you floorplan).  In the Altera
> 10K, anything that is not in the 8 LEs of a LAB has to go out on the Row
> or column routing, which is essentially a global route.  There are many
> instances where you can use up routing long before you use up logic.  (a
> CORDIC processor which is a chain of interconnected adder-subtractors is
> such an example.  Each stage in the chain needs to use two global routes
> per bit, one for the intermediate result and one for the
> adder-subtractor sum.  The end result is to build this, you need to use
> a device roughly twice as big as the logic alone dictates).  Of course
> driving the long interconnect uses more power as well.
> 4.  DSP pipelines often involve delay queues to match pipeline delays in
> parallel paths.  The ability to use Xilinx LUTs as memory makes a
> compact 1 or 2 bit delay of up to 32 clocks using one LCA plus a small
> LFSR counter (which can be shared among many delays).  Altera does not
> have this small ram capability, so pipeline delay queues end up taking
> an LE per bit per clock.
> 
> In applications where you can take advantage of the EABs, the Altera
> device does a little better.  An example is a logarithm function, which
> can be implemented as a 256x5 table plus a barrel shifter.  The table is
> easily done in an EAB, and each stage of the barrel shift can be
> implemented in a single logic level (the cascade connections make the
> barrel shift more efficient too).  Unfortunately, the EABs are
> relatively scarce, so their usability is limited.
> 
> Altera's use of global routing does make the device less sensitive to
> placement, and makes for a more synthesis friendly architecture. The
> cost for DSP applications is substantial, as outlined above.
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email randraka@ids.net
> http://users.ids.net/~randraka
> 
> The Andraka Consulting Group is a digital hardware design firm
> specializing in high performance FPGA designs for digital signal
> processing, computing and control applications.

-- 
I'm not trying to push Atmel on anyone, but I have always felt that
highly pipelined archtectures was the one place where their chips made
sense. This is especially true if your design is one which flows across
the chip so that each stage can directly connect output to the next
stage input. This is because of the limited routing resources. 

Have either of you looked at their products? I have been hearing some
good things about the 40K family. But it doesn't have the high number of
cells that you get with the 6K family. 


Rick Collins

rickman@XYwriteme.com

remove the XY to email me.



Article: 10217
Subject: Re: Xilinx Foundation and Linux
From: Gerhard Hoffmann <ghf@berlin.snafu.de>
Date: Tue, 05 May 1998 06:35:18 +0200
Links: << >>  << T >>  << A >>
Ingo Cyliax wrote:
> 
> Yes, I would love to have my FPGA place&route and Cad tools under Linux. I
> use Win95/NT4.0 for FPGA P&R and Word. Win95 typically crashes 2-3 times
> per work session, 

The Xilinx DOS based tools (Pre-M1) seem to work under 
Linux + DOSEMU, although file i/o seems to be very slooow
and XBLOX could not find the dongle. I did not try seriously
to run it, played only a little bit and my DOSEMU setup
may need some work.


Gerhard

-- 
on the air:    DK4XP
in the air:    D-8551
Article: 10218
Subject: Re: Xilinx Foundation and Linux
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: 5 May 1998 07:55:15 GMT
Links: << >>  << T >>  << A >>
Gerhard Hoffmann <ghf@berlin.snafu.de> wrote:
: Ingo Cyliax wrote:
:> 
:> Yes, I would love to have my FPGA place&route and Cad tools under Linux. I
:> use Win95/NT4.0 for FPGA P&R and Word. Win95 typically crashes 2-3 times
:> per work session, 

: The Xilinx DOS based tools (Pre-M1) seem to work under 
: Linux + DOSEMU, although file i/o seems to be very slooow
: and XBLOX could not find the dongle. I did not try seriously
: to run it, played only a little bit and my DOSEMU setup
: may need some work.

You probally have a bad parallel port setup in doesme. The semantics 
changed sometime about two years ago. Have someting like
ports { device /dev/lp1 fast range 0x378 0x37F}
in your dosemu.conf. For 0.97 the semantic changed again.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 10219
Subject: 3.3V design conversion
From: Jim McCloskey <jmccloskey@compuserve.com>
Date: Tue, 05 May 1998 06:49:14 -0400
Links: << >>  << T >>  << A >>
I'm currently migrating a 5V digital design to a mix of 5V and 3.3V
logic (mix of FPGAs and ASICS). Only a 5V supply is available. Any good
info on 5V to 3.3V migration, small DC-DC converters, layout
considerations, logic interfacing, etc. would be appreciated.
My main interest is in techniques for voltage conversion. I've heard of 
designs which use small DC-DC converters distributed across the board to 
provide ample current at 3.3V. Any experience or suggestions with this? 
Any suggestions on which DC-DCs to use?


Thanks much
Jim McCloskey
Article: 10220
Subject: STUDENT RESIDENCE IN MADRID
From: Liceo Herrera-Quick3 <quick3@arti.es>
Date: Tue, 05 May 1998 13:31:44 +0200
Links: << >>  << T >>  << A >>
Hello, this is a student residence located at the center of Madrid.
Buses, undergrounds, stores, fun, etc.
Stay with us if you come to our city!

ARTI RESIDENCE

Shared room (per person) B+B
Per night......................................2.800 pesetas per night
Single room B+B
Per night......................................3.400 pesetas per night

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Full board: plus 1.100 pesetas per night.

All prices with VAT included.
Special prices for a month stay, depending on the type of room.

Contact us at:  direccion@arti.es

WE ARE WAITING FOR YOU!








Article: 10221
Subject: Re: 3.3V design conversion
From: "Austin Franklin" <dar4kroom@ix.netcom.com>
Date: 5 May 1998 13:17:01 GMT
Links: << >>  << T >>  << A >>
Linear Technology makes a pretty canned +5 to +3.3V switcher.  LTC1504-3.3.
 It provides 400ma, no external switch or L...very nice part.

Austin Franklin
darkroom@ix.netcom.com

> I'm currently migrating a 5V digital design to a mix of 5V and 3.3V
> logic (mix of FPGAs and ASICS). Only a 5V supply is available. Any good
> info on 5V to 3.3V migration, small DC-DC converters, layout
> considerations, logic interfacing, etc. would be appreciated.
> My main interest is in techniques for voltage conversion. I've heard of 
> designs which use small DC-DC converters distributed across the board to 
> provide ample current at 3.3V. Any experience or suggestions with this? 
> Any suggestions on which DC-DCs to use?


Article: 10222
Subject: Re: 3.3V design conversion
From: husby@fnal.gov (Don Husby)
Date: Tue, 05 May 1998 13:27:16 GMT
Links: << >>  << T >>  << A >>
Jim McCloskey <jmccloskey@compuserve.com> wrote:
> My main interest is in techniques for voltage conversion. I've heard of 
> designs which use small DC-DC converters distributed across the board to 
> provide ample current at 3.3V. Any experience or suggestions with this? 
> Any suggestions on which DC-DCs to use?

The motherboard industry seems to be standardizing on programmable
converters for generating CPU core voltages.  PowerTrends, for example will
offer a converter that can generate 1.3V to 3.5V at 32 amps with 90% 
efficiency in a fairly small plug-in package.
 
     http://www.powertrends.com/


 


--
Don Husby <husby@fnal.gov>                        Phone: 630-840-3668
Fermi National Accelerator Lab                      Fax: 630-840-5406
Batavia, IL 60510
Article: 10223
Subject: Re: 3.3V design conversion
From: "Tom Meagher" <tomm@icshou.com>
Date: Tue, 5 May 1998 08:51:14 -0500
Links: << >>  << T >>  << A >>
This IS a nice part, but I believe it requires 100 uH external inductor, and some compensation components too...


Austin Franklin wrote in message <01bd7828$0ddc5390$4270d6ce@drt1>...
>Linear Technology makes a pretty canned +5 to +3.3V switcher.  LTC1504-3.3.
> It provides 400ma, no external switch or L...very nice part.
>
>Austin Franklin
>darkroom@ix.netcom.com
>


>> I'm currently migrating a 5V digital design to a mix of 5V and 3.3V
>> logic (mix of FPGAs and ASICS). Only a 5V supply is available. Any good
>> info on 5V to 3.3V migration, small DC-DC converters, layout
>> considerations, logic interfacing, etc. would be appreciated.
>> My main interest is in techniques for voltage conversion. I've heard of
>> designs which use small DC-DC converters distributed across the board to
>> provide ample current at 3.3V. Any experience or suggestions with this?
>> Any suggestions on which DC-DCs to use?
>
>


Article: 10224
Subject: Re: 3.3V design conversion
From: "Austin Franklin" <dar4kroom@ix.netcom.com>
Date: 5 May 1998 15:11:27 GMT
Links: << >>  << T >>  << A >>
You're right.  Actually a 33uH in my design (didn't notice the L when
writing the post...).  What compensation components are you talking about? 
All I use is a 47u cap on the output, a 100n on the input and 1n cap on the
COMP pin (is this what you are referring to?) and a 10k pullup on the /SHDN
pin.  'Seems' to work just fine ;-)

The data sheets are available on their web site, as well as an excellent
application note.

Austin


Tom Meagher <tomm@icshou.com> wrote in article
<6ilh3l$dvo$1@supernews.com>...
> This IS a nice part, but I believe it requires 100 uH external inductor,
and some compensation components too...
> 
> 
> Austin Franklin wrote in message <01bd7828$0ddc5390$4270d6ce@drt1>...
> >Linear Technology makes a pretty canned +5 to +3.3V switcher. 
LTC1504-3.3.
> > It provides 400ma, no external switch or L...very nice part.
> >
> >Austin Franklin
> >darkroom@ix.netcom.com
> >
> 
> 
> >> I'm currently migrating a 5V digital design to a mix of 5V and 3.3V
> >> logic (mix of FPGAs and ASICS). Only a 5V supply is available. Any
good
> >> info on 5V to 3.3V migration, small DC-DC converters, layout
> >> considerations, logic interfacing, etc. would be appreciated.
> >> My main interest is in techniques for voltage conversion. I've heard
of
> >> designs which use small DC-DC converters distributed across the board
to
> >> provide ample current at 3.3V. Any experience or suggestions with
this?
> >> Any suggestions on which DC-DCs to use?
> >
> >
> 
> 
> 


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