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> I too had the same thought. For a while. > > A platform USB cable from the Xilinx store costs $150. Given the time > to reverse engineer the protocol and design a board, and ... > > And let's not forget that Xilinx owns the USB Vendor ID for the device, > so one can't re-use it without their permission. > > You can't make one that's iMPACT compatable; might as well buy one of > the Digilent $38 versions. I came accross the Digilent JTAG-USB programming cable, but haven't been to find its protocol specifications. I asked Digilent for more information, but my e-mail seems to have been discarded. Do you know if the cable protocol is available somewhere ? Or will I have to reverse engineer it as well ? Laurent PinchartArticle: 102426
not directly available. RE neededArticle: 102427
"Ad" <adam.taylor@eads.com> schrieb im Newsbeitrag news:1147699530.387734.254350@i39g2000cwa.googlegroups.com... > Falk > > I have done three SIL4 fpga development on my last contract, we did not > use certified tools as I am not aware there are any however we used > very stringent RTL design guidelines, independantly developed test > benches for each module which must achieve 100 % in code coverage for > path, branch, statement, toggle, and condition at all levels. along > with independant reviews of rtl code and module specifications / test > specifications. Further more we used two synthesis tools targeting > different technologies i.e. xilinx and actel and then used formal > equivelence checking to ensure that the RTL against the implementation > actel devices (the devices used were actel) were the same with no > mismatches and then compared the xilinx against actel top ensure the > synthesis tools had not filled any holes with logic. There are a few > guidelines for coding RTL style to ensure all possible failure > conditions are detecteable, I would be happy to advise you further if > you would like to know more ? I think i have some documents I wrote on > saftey critcal fpga design somewhere. > > What is your intended application ? > > hope this helps > > Adam > Thanks for your reply! It gives a good first impression. Our application is a simple fall back braking system in a railway application. I am very interested in further advices. One special question: Do manufacturers give any reliability data on how reliable the program is stored in Flash (CPLD/external in case of FPGA)? Might this reliability be sufficient for SIL2 or do I have to do certain checks on the "program data" of the FPGA/CPLD? FalkArticle: 102428
> not directly available. RE needed Has anyone started working on that ? Laurent PinchartArticle: 102429
Falk I have sent you a message to your personal email let me know if you do not get it regards AdArticle: 102430
Brad Smallridge <bradsmallridge@dslextreme.com> wrote: >Does any one have any software (or experience) to share (or sell) concerning >bringing a USB2 camera image into a XILINX ML401, ML402, or ML403 board. Maybe you can use a driver from here: http://alpha.dyndns.org/ov511/cameras.html Other than that it's the RR route.Article: 102431
> The error on 3.3V is 1.3%, which will be nearest fit resistor values. > Normally, simplest design uses two resistors, and it is hard to nail > a value under 1% with available values. > > If this is loosing you sleep, then move to a 3 resistor design, and > also be prepared to pay for resistors under 1% tolerance. At the moment, the design is slated as having a three resistor design. I figured that was the most flexible in terms of layout. If my paranoia is unfounded then we'll throw in a zero-ohm resistor and go back to two. > In a real design, you should measure/verify the voltage AT THE DEVICE, > which means a few mV high allows for some trace/choke IR drop. OK, I've spec'd an alternative which measures high by about the same as the TI reference designs and I'll try both on the prototype, see how they come out. > Also check the dynamic power changes, and output impedance of your > regulators, as that is another error source. Thanks, for the advice, it is much appreciated. -- PeterArticle: 102432
> I would say that it is better to err slightly on the high side to > compensate for IR drop between the regulator and the part. Once you > build the prototype you can measure the actual drop (both ground and > high sides) and tweak your values accordingly. Thanks, I will do. I have two alternative designs each with three or two resistors, so I'm laying out three and will do playing at the prototyping stage. > I have used the TPS75003 in a ceramic capacitor configuration, because > tantalum and small electrolytic capacitors are prohibited in our > applications. In this case the divider network has to be designed > differently to provide AC feedback from the switch. I asked TI about > this, and they recommended that I follow the guidance in the TPS64200 > datasheet (see figure 27 and associated discussion). This has worked > well. Thanks for the advice, I'll take a look at that datasheet also. -- PeterArticle: 102433
> The distributor is not operating a charity. Selling you 5 chips for > about $ 50 is hardly a very profitable transaction, considering > paperwork etc. These are not little 7/11 stores... > Expecting to buy 5 chips at the million-quantity price is unrealistic. > The $40 difference between a real and a completely unrealistic price is > not too bad. > > Now, if you complain that you cannot get the chips at all, that would > be a valid complaint. > $ 40 is not! > Peter Alfke, Xilinx One thing I would complain about is being forced to buy a MOQ of 48 devices when building prototypes. I wouldn't have any problems paying normal_1off_price * 1.5 to be able to get any quantity I want, even if this meant a longer lead time than normal. (BTW, this is a complaint at all FPGA distributors). Nial. ---------------------------------------------------------- Nial Stewart Developments Ltd Tel: +44 131 561 6291 42/2 Hardengreen Business Park Fax: +44 131 561 6327 Dalkeith, Midlothian EH22 3NU www.nialstewartdevelopments.co.ukArticle: 102434
Has anyone implemented DDR2 333Mhz (667Mbps) using Altera or Xilinx FPGA's? ThanksArticle: 102435
Hi ! I'm a newbie in FPGA ( and i'm french,that's why my english is not good ). I have the Digilent Spartan 3 Starter kit and Xilinx ISE Webpack 8.1i ( with Impact ) I have a problem : I can't download files on the chip because Impact doesn't recognize my cable. I am using the "Digilent JTAG3 low cost parallel to JTAG cable" which is included with the starter kit. When I launch a Cable autodetect on Impact, I have this message : GUI --- Auto connect to cable... // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. PROGRESS_START - Starting Operation. Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. Connecting to cable (Parallel Port - LPT2). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. Connecting to cable (Parallel Port - LPT3). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. Connecting to cable (Parallel Port - LPT4). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. Connecting to cable (Usb Port - USB21). Checking cable driver. Driver xusbdfwu.sys version: 1018 (1018). Driver windrvr6.sys version = 7.0.0.0.Cable connection failed. PROGRESS_END - End Operation. Elapsed time = 3 sec. Cable autodetection failed. Can any one help me please ? ThanksArticle: 102436
I use Impact 8.1 When I want to download files on my starter kit, ( with the Digilent JTAG3 cable) Impact prompt this : WARNING:iMPACT:923 - Can not find cable, check cable setup !// *** BATCH CMD : setCable -port lpt1 Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0. LPT base address = 03F8h. ECP base address = FFFFFFFFh. Cable connection failed. What can I do ??? ThanksArticle: 102437
John_H schrieb: > "Peter Alfke" <peter@xilinx.com> wrote in message >>There are 6 levels of multiplexing, nothing we can do about it. >>Peter Alfke > > > So the luts are actually full multiplexers, not a memory array style of > addressing? I would have thought LUTs would work much better than general > multiplexors by using a nand/nand style of structure to drive one active > line in a 64-wide CMOS tree. Muxes? In a RAM you can reuse the decoder logic over many bitlines. For a single bit output adress decoders are larger, slower and have higher capacitance compared to pass transistor muxes. Maybe there is a sweet spot a little off from the extreme so maybe the tree has one or two levels less and uses one input as enable (or wordline if you like). But I am sure that most of it is a tree of pass transistors.... After all the technology used is highly optimized for pass transistors. Also: A MUX build with address decoders enabling a common bitline is still a MUX... Kolja SulimmaArticle: 102438
get a PC with decent real LPT port !! some PCI LTP ports (sunix chipset as example) are not revealing its LPT base address so tools that obtain the address automatically like Impact fail to use such LPT ports. With Lattice software you can enter the LPT base manually and still use such printer port cards. for impact to work a real LPT port is needed (not usb LPT) this may be on-motheboard LPT or PCI LPT card AnttiArticle: 102439
Hi, I am trying to connect my Spartan 3 borad with PC by RS232 , and am able to echo single input in hyper temial consol. What i am trying to do is sending "hi" from the board to the pc, by only hit 1 from hyper termial. Will follow steps design work? I am not sure if the RS232 (hypertermial) has any limitation on this. I have worked on this for sevral days, but still doesn't work. any idea will welcome. 1. read input 2. if input = '1' then go to 3 else back to 1 3. send 'h' 4. send 'i'Article: 102440
>I am trying to connect my Spartan 3 borad with PC by RS232 , and am >able to echo single input in hyper temial consol. What i am trying to >do is sending "hi" from the board to the pc, by only hit 1 from hyper >termial. Will follow steps design work? I am not sure if the RS232 >(hypertermial) has any limitation on this. I have worked on this for >sevral days, but still doesn't work. any idea will welcome. > >1. read input >2. if input = '1' then go to 3 else back to 1 >3. send 'h' >4. send 'i' You don't say in what way this isn't working. You may need to wait before step 4 until the hardware is ready to accept another character (if the transmitter has no buffer). That is, you may need to wait until the first character has been transmitted. If you need this "flow control", then the most likely behaviour without it is that only a single character is transmitted (either 'h' or a corrupted character, depending on the behaviour of the transmitter when you write a character to it when it isn't ready).Article: 102441
You can get most Altera parts from Digikey or from Altera directly, which I think is basically still Digikey. I recommend you use Altera until Xilinx gets their act together with their online store. (Thanks Peter and Austin for pushing for that) PC processors are a very different market than FPGAs. They have a different pricing structure as a result. The list prices target individual purchase. There are significant deals to be had, though, if you want to buy millions of them. Microsoft certainly didn't pay full price for all of those processors they bought from Intel for the XBox. Newegg can offer good prices on PC processors because millions of people buy individual processors from them. That is the fundamental difference. The scale is enough that with individual purchases they can be priced pretty low. The other reason they can be priced differently is that most processors end up in a different group of peoples' hands. Most processors are consumed by people running Windows wanting to browse the web, read and write email and balance their check book. FPGAs are all targetting engineers. Since engineers tend to push the technology, FPGA vendors have a significant amount of support to provide, whereas PC processor manufacturers mostly only deal with the distributors and pre-release developers. You can't expect this to change. It is the way it will be due to different markets. As for the minimum quantity problem, try Altera or Lattice. They both seem to be pretty good about getting the parts that you need at good prices. -ArlenArticle: 102442
I am sure it is safe. This circuit has proven to be glitchfree, as described in the words around it (metastability lass than half a clock period) In general: Whenever you change one input of a LUT, there is no glitch at the output if the two input addresses generate the same output level. I documented this 15 years ago... Peter Alfke, XilinxArticle: 102443
I got only only signal from the UART model saying that the transmit bus is empty(TBE) if 1 then empty. Here is what I do step by step: 1. until input arrive, then go to 1 2. read input if input = '1' then go to 3, else back to 1 3. put 'h' on the data bus, wait until TBE is 0 go to 4 4. wait until TBE = 1 then go to 5 5. put 'i' on the data bus, wait until TBE is 0 go to 6 6. wait until TBE = 1 then back to 1 it hang on step 5. wait for TBE to be 0Article: 102444
Hi Austin, LX datasheets says up to 10 DSP48E colums per device, but the largest of the LX family, LX330 only has 2 not 10 DSP48E columns? Are devices that actually have 10 columns already planned? Scary to think how larger would the be! AnttiArticle: 102445
Hi Peter, interesting, as much as I recall at the time Altera was claiming to support LUT input delay difference in their tools, Xilinx had no public info that the input delay are different or that they are actually calculated compensated in Xilinx software. "documented" in your wording means that this behaviour of Xilinx software was documented for the user of the software or that it internally uses it? oh well if it that info has been available earlier I have missed it (I am not so good doing that RTFM thing sometimes) and sure the last picosends do count also! AnttiArticle: 102446
by the way, if i go to 1 instead 5 on step 4. It is working, and it just a normal echo programArticle: 102447
Kevin Neilson wrote: > > That's pretty impressive. How did you implement the carry-kill chain, > or whatever they call the ciruit that finds the location of the leading > '1'? This can be made with a carry chain, but I don't know if it would > work with a 2.5ns period. -Kevin A clever use of DSP48 and BRAM blocks. The fabric carry chain definitely won't reach 400MHz, especially with 30 bits.Article: 102448
Peter Mendham wrote: > rickman wrote: > > But I think the OP is saying the values selected provide a voltage 40 > > mV too high. > > Yes, I am still on the drawing board at this point. > > > Or are you talking about the TI app notes? > > I am, I haven't found any Xilinx app notes about the part. Are there any? > > > Actually I don't see how > > you can say all three outputs are 40 mV too high when the 1.2 volt > > output does not use external resistors! > > Good point, my mistake. Sorry. Both Buck 2 and the LDO are approx 40mV > too high. > > > The values in the TI data > > sheet (figure 1) produce about 2.54 volts, 3.29 volts and of course, > > 1.2 volts. > > I am indeed. I am probably being stupid, but using the values in all > the TI example circuits (I have about 5 variations here) the Buck 2 > potential divider uses values of 61K9 and 36K5 (or 319K and 365K). By > equation 15 in the TI datasheet these values give a Vout of 3.343V. > Similarly, for the LDO the value 2.545V. These are 43mV and 45mV over > spec respectively. Now, it is extremely likely that I am either > worrying about nothing, or being very stupid. Is this over-voltage > specified deliberately, or is it simply a product of using nearest-fit > resistor values? Or have I done my calculations badly? If you can > clarify that for me I would be very grateful. I don't know about stupid, but I didn't see the equations... :) I just used the stated feedback voltage and the resistor ratios to get my numbers. I don't know why your numbers are different from mine. What equations did you use? I used Vf * (R1+R2/R2), where R1 is the resistor that connects to the output voltage and R2 is the resistor that connects to ground. Regardless, I would not worry about 40 mV on either of these supplies.Article: 102449
Antti wrote: > well, take PA3 price, multiply by 2 and then add 120 USD for ARM > license (in small qty) > its the best estimate for today. > > so qty 1 price over 200 USD Something is wrong with that. $120 per usage of a core that I can buy as a chip for under $5 with tons of peripherals seems a bit rediculous. Where did you get the PA3 price multiplier? I was not initially interested in the Fusion since typically combined analog and digital do not do justice to either. But I have an application where combining some basic analog functions such as a multichannel ADC with digital and potentially an MCU in a Flash based part would be very advantageous. It doesn't have to be an ARM, pretty much any MCU could do the job. I could use the Fusion without the ARM if the price point is ok. But a 2x multiplier seems a bit steep. Personally I have always felt it was not a good idea to try to duplicate a complex CPU in FPGA fabric. Both Xilinx and Altera have very nice CPU cores that are tightly coupled to their architectures and so efficiently use the fabric. But implementing an ARM in fabric is not efficient either in size or speed. It would be much more efficient to add the ARM as a hard peripheral like they do on the Virtex 2P parts. But they seem to charge a price premium even then. So the simple CPU cores seem to be a good tradeoff if your processing is not complex. NIOS II seems to be especially well matched to the Cyclone II chips!
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Compare FPGA features and resources
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