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Messages from 10250

Article: 10250
Subject: CPLD devices
From: "Paul Kraszewski" <PKraszewski@BigFoot.com>
Date: Thu, 7 May 1998 11:24:37 +0200
Links: << >>  << T >>  << A >>
Hello everybody!

    I know this question would be profan for the FPGA related list, but does
anybody work with Philips CoolRunner CPLD devices?
    I would like to know, whether they are available in quantities of single
pieces in Poland or eastern areas of Germany (Berlin, etc).


Thanks in advance,
   Paul Kraszewski

           Pawel Kraszewski - mailto:pkraszewski@BigFoot.COM
   /\                         http://www.bigfoot.com/~pkraszewski
__/  \  ______________________Tel/Fax: +48(91)4872905______________
      \/




Article: 10251
Subject: Re: EPF10K100ABC356-1 HELP US !
From: hayhoe@nortel.co.uk (Brent A. Hayhoe)
Date: 7 May 1998 09:26:44 GMT
Links: << >>  << T >>  << A >>

In article <353BF949.77C8D727@swin.edu.au>, David Braendler <dbraendler@swin.edu.au> writes:
>        I am trying to use the C++ code provided with the HOT Works
>board to interface with the board via software. Unfortunately I am
>having major difficultiies in doing this. There are a few reasons :
>(a) I dont know what is in the device driver, and hence have no idea if
>this is working correctly.(The code uses the device driver)
>(b) The code provided doesn't read in CAL files correctly, nor does the
>executables provided by VCC.
>
>I have contacted VCC a few times for help but there is a curious lack of
>response from them.....
>
>If anyone has used the C++ code to interface to the HOT Works board, I
>would love to get a couple of pointers on how to get started.
>
>
>Dave Braendler.
>Centre for Intelligent Systems.
>Swinburne University.
>
>


-- 

Regards,

 	Brent Hayhoe.

Nortel plc.,                                          Tel: +44 (0)1279-402937
Harlow Laboratories,  London Road,                    Fax: +44 (0)1279-439636
Harlow, Essex,  CM17 9NA,  U.K.                       Email: hayhoe@nortel.co.uk
                                                         or: hayhoe@nortel.ca


Article: 10252
Subject: Re: EPF10K100ABC356-1 HELP US !
From: hayhoe@nortel.ca (Brent A. Hayhoe)
Date: 7 May 1998 09:28:10 GMT
Links: << >>  << T >>  << A >>

In article <01bd7912$3ef72b40$45b530ce@gd30600.glo.be>, "peter Brandt" <familiebrandt@glo.be> writes:
>Hi,
>
>Is it true that there is no production anymore (due to problems) of the
>Altera EPF10K100 speedgrade 1, package BGA 356 pins?

>Please help us !!

>Peter.brandt@leu.ce.philips.com

Peter,

Have you tried Altera directly.  Their UK office covers Europe:-

> Altera UK Limited
> Holmers Farm Way
> High Wycombe
> Buckinghamshire
> HP12 4XF
> 
> Tel: 44 (0) 1494 602143
> Fax 44 (0) 1494 602021


-- 

Regards,

 	Brent Hayhoe.

Nortel plc.,                                          Tel: +44 (0)1279-402937
Harlow Laboratories,  London Road,                    Fax: +44 (0)1279-439636
Harlow, Essex,  CM17 9NA,  U.K.                       Email: hayhoe@nortel.co.uk
                                                         or: hayhoe@nortel.ca


Article: 10253
Subject: Low power FPGA design
From: Phil Cook <cook-pa@diesel.eelab.usyd.edu.au>
Date: Thu, 07 May 1998 19:57:37 +1000
Links: << >>  << T >>  << A >>
I am beginning research on doing using a FPGA to implement a
digital circuit for an implantable cardio defibrillator.  Due to the
nature of the product, low power consumption is a primary concern.
I was wondering if any one has any documentation or advice on
doing a low power, low frequency design using an FPGA.  The chip
will only need to be clocked at a few hundred hertz.

Any help would be appreciated.
TIA ,

Phillip Cook.


Article: 10254
Subject: Looking for Ultra 2 SCSI Synthesizable Core
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Thu, 7 May 1998 08:04:33 -0700
Links: << >>  << T >>  << A >>
Does anybody know where I might find an Ultra 2 SCSI core?  I'm primarily
interested in Slave operations.  Verilog is preferred but will take what I
can get.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Article: 10255
Subject: Re: Low power FPGA design
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 07 May 1998 10:19:18 -0700
Links: << >>  << T >>  << A >>


Phil Cook wrote:

> I am beginning research on doing using a FPGA to implement a
> digital circuit for an implantable cardio defibrillator.  Due to the
> nature of the product, low power consumption is a primary concern.
> I was wondering if any one has any documentation or advice on
> doing a low power, low frequency design using an FPGA.  The chip
> will only need to be clocked at a few hundred hertz.
>  

You can achieve microamp consumption with XC3000L, but also with the
more modern XC4000XL devices if you:

   * turn off the internal oscillator ( is already the default)
   * turn off all internal longline pull-ups
   * turn off all I/O pull-ups and pull-downs and define the voltage on
     every unconnected or unused pin by driving it High internally
   * minimize all internal activity :-)
   * run at a low voltage, closer to 3.0 than 3.6 V
   * avoid high temperatures 

Regarding the use in life support applications, I want to bring to your
attention a standard disclaimer issued by every semiconductor company I
know.
In our case it is phrased:

"Xilinx products are not intended for use in life support appliances,
devices, or systems. Use of a Xilinx product in such applications
without the written consent of the appropriate Xilinx officer is
prohibited."
( Last paragraph on the inside front cover of our data book).

As I said, every manufacturer who understands the danger of a liability
lawsuit has issued such a statement somewhere.

Peter Alfke, Xilinx Applications



Article: 10256
Subject: PLD & FPGA Conference & Exhibition 12/5/98
From: johnnyick@aol.com (Johnnyick)
Date: 07 May 1998 21:56:25 GMT
Links: << >>  << T >>  << A >>
For the latest developments in PLD & FPGA technology come to The Eighth Annual
Advanced PLD & FPGA event on 12 May at Royal Ascot Racecourse. For full
conference programme details, exhibitor list and how to register on-line visit
http://www.pldconf.com
Article: 10257
Subject: Re: Low power FPGA design
From: jhallen@world.std.com (Joseph H Allen)
Date: Fri, 8 May 1998 03:27:32 GMT
Links: << >>  << T >>  << A >>
In article <3551ED11.E6C0A354@xilinx.com>,
Peter Alfke  <peter.alfke@xilinx.com> wrote:

>"Xilinx products are not intended for use in life support appliances,
>devices, or systems. Use of a Xilinx product in such applications
>without the written consent of the appropriate Xilinx officer is
>prohibited."

>As I said, every manufacturer who understands the danger of a liability
>lawsuit has issued such a statement somewhere.

Has Xilinx (or any semiconductor manufacture for that matter) ever given
permission for the use of their devices in life support situations?  How do
people who make such devices do it?  Without permission I guess.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 10258
Subject: Altera relative placement
From: ivan@caseware.NOSPAM.com (Ivan)
Date: Fri, 08 May 1998 03:32:38 GMT
Links: << >>  << T >>  << A >>
	
	Is it possible to assign a relitave placement for the logic
using Maxplus2? I have a big pipeline, and maxplus simply cannot find
a way to fit everything (even though there is 3 times more logic in
the chip than required for the design). However, when I force each
register in fixed position, it manages to route without any problems.
	Also, my pipeline stages are identical. I was wondering if it
is possible to help the fitter fit and route one chunk of logic and
then replicate the logic wherever it's needed.
	If this is not possible, what would be the best options to
help Maxplus2 do the job correctly and completely?

	Ivan Hamer.
Article: 10259
Subject: Boundary Scan in XC4000: Help me
From: skitles <yjryu@hyowon.pusan.ac.kr>
Date: Fri, 08 May 1998 13:34:32 +0900
Links: << >>  << T >>  << A >>
Hi.

I want to use BSCAN in XC4010E..
The BSCAN symbol was inserted into my design with the correct syntax
before configuration, and I accessed the boundary-scan logic
through the TAP(TMS,TCK,TDI,TDO).
But boundary-scan logic didn't work.

Please explain to me how to use the boundary-scan logic
(with the simple VHDL code or Netlist).


Article: 10260
Subject: Xilinx Routing Delay
From: Ries Gilles <riesg@sh.bel.alcatel.be>
Date: Fri, 08 May 1998 08:51:52 +0200
Links: << >>  << T >>  << A >>
Hi !

I've just made a circuit with an Xilinx XC4044XL.

I was amazed that 85% of the critical path delay was due to the routing
delay. Can it be considered correct, or did something go wrong in the
placement/routing ?

In my case, I had 11 levels of logic, between a pad and a FF, and 20 ns
of logic, and 135 ns of Routing delay. I used the highest optimisation
effort possible with enough iteration.

Thanks.

        Gilles.
Article: 10261
Subject: Re: Low power FPGA design
From: murray@pa.dec.com (Hal Murray)
Date: 8 May 1998 06:57:10 GMT
Links: << >>  << T >>  << A >>
> "Xilinx products are not intended for use in life support appliances,
> devices, or systems. Use of a Xilinx product in such applications
> without the written consent of the appropriate Xilinx officer is
> prohibited."

I've seen similar things many times.

Suppose I have a good idea that needs electronics for a life-support
application.  What do I have to do to get the appropriate signatures?


How long before routers or mail servers are considered life support?
What about phone systems?  What about 911 systems?


-- 
These are my opinions, not necessarily my employers.
Article: 10262
Subject: Re: Xilinx Routing Delay
From: ccwest@ix.netcom.com (Bill Seiler)
Date: Fri, 8 May 1998 11:21:49 +0100
Links: << >>  << T >>  << A >>
Yes I have the same results. 80% route delay, 20% gate delay.
Who has the time to floor plan.  We are trying to do a real ASIC.  The 
Xilinx to verify the design and give software something to work with.

Bill Seiler
*****************************************************************

Article: 10263
Subject: Re: Low power FPGA design
From: peterc <peterc@hmgcc.gov.uk>
Date: Fri, 08 May 1998 12:04:39 +0100
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 

<snip> 

> You can achieve microamp consumption with XC3000L, but also with the
> more modern XC4000XL devices if you:
> 
>    * turn off the internal oscillator ( is already the default)
>    * turn off all internal longline pull-ups
>    * turn off all I/O pull-ups and pull-downs and define the voltage
>      on every unconnected or unused pin by driving it High internally
>    * minimize all internal activity :-)
>    * run at a low voltage, closer to 3.0 than 3.6 V
>    * avoid high temperatures
> 

The xilinx data book states 5mA Quiescent for 4000XL (1998 page 4-72).
This is with a note that all I/O is tri-state and floating, no output
load, no active input or longline pull-ups.

Does the current really come down to microamps by following your other
recommendations. It seems a large drop in current from the maximum
quiescent, or is the max quiescent specified quite high so that there
may be a large variation between batches.

Would Xilinx be able to gaurentee a lower max quiescent under certain
conditions?
Article: 10264
Subject: Re: Low power FPGA design
From: Achim Gratz <gratz@ite.inf.tu-dresden.de>
Date: 8 May 1998 13:26:53 +0200
Links: << >>  << T >>  << A >>
jhallen@world.std.com (Joseph H Allen) writes:

> Has Xilinx (or any semiconductor manufacture for that matter) ever given
> permission for the use of their devices in life support situations?  How do
> people who make such devices do it?  Without permission I guess.

By designing an ASIC and assuming the responsibility for themselves.
Of course only after extensive process and design qualification
failure mode analysis, test vector generation and so on.  This is not
done for the typical FPGA and thus the standard disclaimer.  I guess
it would be possible to qualify the parts, but since you'd have to
redo most of it for _every_ process change however slightly that
wouldn't rhyme well with the FPGA manufacturing model (esp. not
fabless).  Sometimes folks buy the wafer production of several weeks
just to be sure they have enough qualified parts in stock for the rest
of the expected lifetime of their products.

[Three or four years ago you could make good money off an early
Toshiba portable computer because it was qualified together with a
life-support system.  They were discontinued and seemingly the cost of
buying whatever was left in the market was far less than requalifying
for the later models.]


Achim Gratz.

--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW:    http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone:  +49 351 463 - 8325
Article: 10265
Subject: Re: Low power FPGA design
From: APS <resp@associatedpro.com>
Date: Fri, 08 May 1998 08:04:47 -0400
Links: << >>  << T >>  << A >>



Peter,

How does the 3000L compare with the 4000XLA. I take from your discussion
that the 3000L is the best solution that XILINX has now for low power. I
am also working some low power designs and was moving towards the
4000XLA.

Also what the largest 3000L series part, and what QFP packages are they
available in?

Peter Alfke wrote:

>  Phil Cook wrote:
>
>> I am beginning research on doing using a FPGA to implement a
>> digital circuit for an implantable cardio defibrillator.  Due to the
>>
>> nature of the product, low power consumption is a primary concern.
>> I was wondering if any one has any documentation or advice on
>> doing a low power, low frequency design using an FPGA.  The chip
>> will only need to be clocked at a few hundred hertz.
>>
>
> You can achieve microamp consumption with XC3000L, but also with the
> more modern XC4000XL devices if you:
>
>    * turn off the internal oscillator ( is already the default)
>    * turn off all internal longline pull-ups
>    * turn off all I/O pull-ups and pull-downs and define the voltage
>      on every unconnected or unused pin by driving it High internally
>    * minimize all internal activity :-)
>    * run at a low voltage, closer to 3.0 than 3.6 V
>    * avoid high temperatures
>
> Regarding the use in life support applications, I want to bring to
> your attention a standard disclaimer issued by every semiconductor
> company I know.
> In our case it is phrased:
>
> "Xilinx products are not intended for use in life support appliances,
> devices, or systems. Use of a Xilinx product in such applications
> without the written consent of the appropriate Xilinx officer is
> prohibited."
> ( Last paragraph on the inside front cover of our data book).
>
> As I said, every manufacturer who understands the danger of a
> liability lawsuit has issued such a statement somewhere.
>
> Peter Alfke, Xilinx Applications



--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/




Article: 10266
Subject: Synopsys Xpress and numeric_std.lib
From: APS <resp@associatedpro.com>
Date: Fri, 08 May 1998 08:30:31 -0400
Links: << >>  << T >>  << A >>
Has anyone had any success at all with using the ieee.numeric_std.lib
with Syopsys FPGA Xpress?  It seems that Synopsys does not support the
ALIAS features. Is there a work around?

--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/

Richard Schwarz, President              EDA & Engineering Tools
Associated Professional Systems (APS)   http://www.associatedpro.com
3003 Latrobe Court                      richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897                     Fax:410.661.2760

__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/


Article: 10267
Subject: Re: Xilinx Routing Delay
From: Ray Andraka <no_spam_randraka@ids.net>
Date: Fri, 08 May 1998 09:08:23 -0400
Links: << >>  << T >>  << A >>
Ries Gilles wrote:
> 
> Hi !
> 
> I've just made a circuit with an Xilinx XC4044XL.
> 
> I was amazed that 85% of the critical path delay was due to the routing
> delay. Can it be considered correct, or did something go wrong in the
> placement/routing ?
> 
> In my case, I had 11 levels of logic, between a pad and a FF, and 20 ns
> of logic, and 135 ns of Routing delay. I used the highest optimisation
> effort possible with enough iteration.
> 
> Thanks.
> 
>         Gilles.

Routing in FPGAs is becoming the limiting factor on speed.  Its almost
to the point that logic is free and the routing is what you are buying. 
Still, if you floorplan your design, you can greatly improve the delays
caused by routing.


-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka

The Andraka Consulting Group is a digital hardware design firm
specializing in high performance FPGA designs for digital signal
processing, computing and control applications.
Article: 10268
Subject: Re: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
From: Michael Schmid <mlschmid@iis.fhg.de>
Date: Fri, 08 May 1998 16:16:38 +0100
Links: << >>  << T >>  << A >>
Rickman wrote:
> 
> Vo To wrote:
> >
> > Hello,
> >
> > I'm using the Xilinx Foundation Series software to implement my FPGA
> > design. One of the biggest problem with my design are frequent hold time
> > errors (running at 25 Mhz, clock cycle = 40 ns) reported during timing
> > simulation.
> >
> > If I reduce the clock to 12.5 Mhz, the hold time errors disappear and
> > the signals are valid and my state machine works fine.
> >
> > Are the hold time errors caused from assigning too wide a signal bus?
> > For example, in a clock cycle, I need to drive 32 internal signals to
> > the external bidirection pins. Is it too much for the XC4025E to change
> > 32 flip-flops in 40ns?
> >
> > To test this out, I reduced to using 8 lines of signal. At 25 Mhz, the
> > simulation did not report hold time errors. If I increase to 16 lines,
> > hold time errors occurs.
> --
> I don't know the particulars of your circuit, but my guess is that you
> are not using the global clock routing. If you don't use the global
> clock routing, as you add more FFs, the data path does not slow down,
> but your clock routing does. This will have the data from the previous
> stage changing from the current clock edge, before the clock reaches the
> next stage.
> 
> To fix this, you need to bring the clock onto the chip through a BUFGS
> rather than an IBUF. Change this buffer and your hold time violation
> should go away. BTW, you should never get a hold time violation in any
> FPGA. This is caused by your data delay being too SHORT, which is
> something that should never happen. If your data path delay is too LONG,
> you will get setup time violations.
> 
> Rick Collins
> 
> rickman@XYwriteme.com
> 
> remove the XY to email me.
--

Hi,

I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL.
Now I have the same problem with a XC4013XL chip. Because of not using
the global clock buffers I have enormous clock skew.

So I've tried to use the BUFGS. I've clicked the "generic clock buffers"
button in the options-menu of XACT-M1. But after implementation the
buffers are not used.


Now my question:
	How can I use the BUFGS in VHDL ?
Article: 10269
Subject: Re: Low power FPGA design
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Fri, 8 May 1998 08:29:32 -0700
Links: << >>  << T >>  << A >>
>
>How long before routers or mail servers are considered life support?
>What about phone systems?  What about 911 systems?
>


I guess when some unscrupulous lawyers decide these are a money-making
opportunity.

-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Article: 10270
Subject: Re: Xilinx Routing Delay
From: Ray Ehrisman <ray.ehrisman@xilinx.com>
Date: Fri, 08 May 1998 10:54:11 -0500
Links: << >>  << T >>  << A >>


Ries Gilles wrote:

> Hi !
>
> I've just made a circuit with an Xilinx XC4044XL.
>
> I was amazed that 85% of the critical path delay was due to the
> routing
> delay. Can it be considered correct, or did something go wrong in the
> placement/routing ?
>
> In my case, I had 11 levels of logic, between a pad and a FF, and 20
> ns
> of logic, and 135 ns of Routing delay. I used the highest optimisation
>
> effort possible with enough iteration.
>
> Thanks.
>
>         Gilles.


Gilles,

Send me your "Post Layout Timing Report" (.twr) and I will try to help
(please zip it).

What you are seeing is NOT typical for logic vs. routing delays in a
4KXL device.  A 50/50 logic vs. routing ratio is a good rule of thumb,
however, 60/40 or 65/35 is not uncommon (depending on net fanout, CLB
logic-levels,  TBUF usage, etc...).

Best regards,
--
/ /\/  Ray Ehrisman
\ \    Field Applications Engineer
/ /    Xilinx Inc. Dallas, TX
\ \/\  Telephone: (972) 960-1043




Article: 10271
Subject: Re: Xilinx Routing Delay
From: Koenraad Schelfhout VH14 8993 <ksch@sh.bel.alcatel.be>
Date: Fri, 08 May 1998 18:02:22 +0200
Links: << >>  << T >>  << A >>
Hallo,

The point is that this block is a single module written in VHDL.
This means about 10K asic gates (look to it as about 20K FPGA gates)
and there is by no means any intention to do manual placing of some
parts (except for the IOpads which needs to have a fixed position).
Note that this module is part of a larger asic, which will be tested
out first based on several xilinxes.  The VHDL code contains very
little hierarchy (for this module actually no hierarchy), and it is
being synthesized with Synopsys FPGA-compiler.  Target frequency is
about 8MHz.  A delay of about 110ns is acceptable on itself, but since
this is one of the simpler modules, we expect a much better timing.
The constraints are put more severe, e.g. we require a 10MHz speed
for the constraints, and when the tool gives up with about 60% of
usage of the Fmaps and delay paths of single connections of up to
40ns I am wondering if the tools are doing really what they are
supposed to do (tool version is the M1.4 set).


-- 

 Koenraad SCHELFHOUT

 Switching Systems Division          http://www.alcatel.com/
 Microelectronics Department - VA21     _______________
________________________________________\             /-___
                                         \           / /
 Phone : (32/3) 240 89 93                 \ ALCATEL / /
 Fax   : (32/3) 240 99 88                  \       / /
 mailto:ksch@sh.bel.alcatel.be              \     / /
_____________________________________________\   / /______
                                              \ / /
 Francis Wellesplein, 1                        v\/
 B-2018  Antwerpen
 Belgium
Article: 10272
Subject: Re: Altera relative placement
From: staylor@dspsystems.com
Date: Fri, 08 May 1998 17:31:57 GMT
Links: << >>  << T >>  << A >>
In article <35527a8f.2043057@news.sprint.ca>,
  ivan@caseware.NOSPAM.com wrote:
>
>
> 	Is it possible to assign a relitave placement for the logic
> using Maxplus2?

Ivan,

Other than using cliques, I have not found a way, having used Maxplus2 since
version 1.1.

> I was wondering if it
> is possible to help the fitter fit and route one chunk of logic and
> then replicate the logic wherever it's needed.
> 	If this is not possible, what would be the best options to
> help Maxplus2 do the job correctly and completely?
>

The short answer is hand placing the design using the floor planner. You might
want to submit your design to Altera. I have found after each major
"improvement" in routing and placing, that some designs that used to fit, no
longer do. The following revision usually corrects that. It has happened many
times. I have also found things like allowing the fitter to fail and then
allowing it to ignore some or all assignments in the dialog box might acheive
a fit where selecting ignore up front might not. Further, the try harder
longer option has failed when the normal succeeds.

Scott Taylor - DSP Fibre Channel Systems

-----== Posted via Deja News, The Leader in Internet Discussion ==-----
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Article: 10273
Subject: Re: Help: 25Mhz XC4025E-2 FPGA having hold time errors during simulation
From: Rickman <spamgoeshere1@yahoo.com>
Date: Fri, 08 May 1998 13:41:04 -0400
Links: << >>  << T >>  << A >>
Michael Schmid wrote:
> Hi,
> 
> I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL.
> Now I have the same problem with a XC4013XL chip. Because of not using
> the global clock buffers I have enormous clock skew.
> 
> So I've tried to use the BUFGS. I've clicked the "generic clock buffers"
> button in the options-menu of XACT-M1. But after implementation the
> buffers are not used.
> 
> Now my question:
>         How can I use the BUFGS in VHDL ?

-- 
I have never done an entirely VHDL design. I use schematics at the top
level to link everything together. My suggestion would be to add a top
level schematic where you can manually place a BUFGS on the clock input. 

If you don't want to use a schematic, why not try giving Xilinx a call
at 800-624-4782? What are you using for the front end? Are you using
Foundation, or are you using one of the third party vendors? If you
don't have support, let me know and I will give them a call about this. 



Rick Collins

rickman@XYwriteme.com

remove the XY to email me.
Article: 10274
Subject: Re: Low power FPGA design
From: Scott Bronson <sbronson@opentv.com>
Date: Fri, 08 May 1998 11:18:12 -0700
Links: << >>  << T >>  << A >>
Xilnix makes great chips, but they are probably not the best choice if
power is an issue.  I've used Phillips CPLDs in the past.  Their
operating draw is typically less than 2 mA, with a quiescent of ~50 uA.

	http://www.coolpld.com/

	- Scott



peterc wrote:
> 
> Peter Alfke wrote:
> >
> 
> <snip>
> 
> > You can achieve microamp consumption with XC3000L, but also with the
> > more modern XC4000XL devices if you:
> >
> >    * turn off the internal oscillator ( is already the default)
> >    * turn off all internal longline pull-ups
> >    * turn off all I/O pull-ups and pull-downs and define the voltage
> >      on every unconnected or unused pin by driving it High internally
> >    * minimize all internal activity :-)
> >    * run at a low voltage, closer to 3.0 than 3.6 V
> >    * avoid high temperatures
> >
> 
> The xilinx data book states 5mA Quiescent for 4000XL (1998 page 4-72).
> This is with a note that all I/O is tri-state and floating, no output
> load, no active input or longline pull-ups.
> 
> Does the current really come down to microamps by following your other
> recommendations. It seems a large drop in current from the maximum
> quiescent, or is the max quiescent specified quite high so that there
> may be a large variation between batches.
> 
> Would Xilinx be able to gaurentee a lower max quiescent under certain
> conditions?


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